<s>
The	O
Alpha	B-General_Concept
21364	I-General_Concept
,	O
code-named	O
"	O
Marvel	O
"	O
,	O
also	O
known	O
as	O
EV7	O
is	O
a	O
microprocessor	B-Architecture
developed	O
by	O
Digital	O
Equipment	O
Corporation	O
(	O
DEC	O
)	O
,	O
later	O
Compaq	O
Computer	O
Corporation	O
,	O
that	O
implemented	O
the	O
Alpha	B-Device
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21364	I-General_Concept
was	O
revealed	O
in	O
October	O
1998	O
by	O
Compaq	O
at	O
the	O
11th	O
Annual	O
Microprocessor	B-Architecture
Forum	O
,	O
where	O
it	O
was	O
described	O
as	O
an	O
Alpha	B-General_Concept
21264	I-General_Concept
with	O
a	O
1.5	O
MB	O
6-way	O
set-associative	O
on-die	O
secondary	O
cache	O
,	O
an	O
integrated	O
Direct	O
Rambus	O
DRAM	O
memory	B-General_Concept
controller	I-General_Concept
and	O
an	O
integrated	O
network	O
controller	O
for	O
connecting	O
to	O
other	O
microprocessors	B-Architecture
.	O
</s>
<s>
Changes	O
to	O
the	O
Alpha	B-General_Concept
21264	I-General_Concept
core	O
included	O
a	O
larger	O
victim	B-General_Concept
buffer	I-General_Concept
,	O
which	O
was	O
quadrupled	O
in	O
capacity	O
to	O
32	O
entries	O
,	O
16	O
for	O
the	O
Dcache	O
and	O
16	O
for	O
the	O
Scache	O
.	O
</s>
<s>
It	O
was	O
reported	O
by	O
the	O
Microprocessor	B-Architecture
Report	O
that	O
Compaq	O
considered	O
implementing	O
minor	O
changes	O
to	O
branch	B-General_Concept
predictor	I-General_Concept
to	O
improve	O
branch	B-General_Concept
prediction	I-General_Concept
accuracy	O
and	O
doubling	O
the	O
miss	O
buffer	O
in	O
capacity	O
to	O
16	O
entries	O
instead	O
of	O
8	O
in	O
the	O
Alpha	B-General_Concept
21264	I-General_Concept
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21364	I-General_Concept
was	O
introduced	O
on	O
20	O
January	O
2002	O
when	O
systems	O
using	O
the	O
microprocessor	B-Architecture
debuted	O
.	O
</s>
<s>
It	O
operated	O
at	O
1.25GHz	O
,	O
but	O
production	O
models	O
in	O
the	O
AlphaServer	B-Device
ES47	O
,	O
ES80	O
and	O
GS1280	O
operated	O
at	O
1.0GHz	O
or	O
1.15GHz	O
.	O
</s>
<s>
Unlike	O
previous	O
Alpha	B-Device
microprocessors	B-Architecture
,	O
the	O
Alpha	B-General_Concept
21364	I-General_Concept
was	O
not	O
sold	O
on	O
the	O
open	O
market	O
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21364	I-General_Concept
was	O
originally	O
intended	O
to	O
be	O
succeeded	O
by	O
the	O
Alpha	B-General_Concept
21464	I-General_Concept
,	O
code-named	O
EV8	O
,	O
a	O
new	O
implementation	O
of	O
the	O
Alpha	B-Device
ISA	O
with	O
four-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
.	O
</s>
<s>
It	O
was	O
first	O
presented	O
in	O
October	O
1999	O
at	O
the	O
12th	O
Annual	O
Microprocessor	B-Architecture
Forum	O
,	O
but	O
was	O
cancelled	O
on	O
25	O
June	O
2001	O
at	O
a	O
late	O
stage	O
of	O
development	O
.	O
</s>
<s>
The	O
development	O
of	O
the	O
Alpha	B-General_Concept
21364	I-General_Concept
was	O
most	O
focused	O
on	O
features	O
that	O
would	O
improve	O
memory	O
performance	O
and	O
multiprocessor	B-Operating_System
scalability	O
.	O
</s>
<s>
The	O
focus	O
on	O
memory	O
performance	O
was	O
the	O
result	O
of	O
a	O
forward-looking	O
article	O
published	O
in	O
Microprocessor	B-Architecture
Report	O
titled	O
,	O
"	O
It	O
's	O
the	O
Memory	O
,	O
Stupid	O
!	O
"	O
</s>
<s>
written	O
by	O
Richard	O
L	O
.	O
Sites	O
,	O
who	O
co-led	O
the	O
definition	O
of	O
the	O
Alpha	B-Device
architecture	O
.	O
</s>
<s>
The	O
article	O
concluded	O
that	O
,	O
"	O
Over	O
the	O
coming	O
decade	O
,	O
memory	O
subsystem	O
design	O
will	O
be	O
the	O
only	O
important	O
design	O
issue	O
for	O
microprocessors.	O
"	O
</s>
<s>
The	O
Alpha	B-General_Concept
21364	I-General_Concept
was	O
an	O
Alpha	B-General_Concept
21264	I-General_Concept
with	O
a	O
1.75	O
MB	O
on-die	O
secondary	O
cache	O
,	O
two	O
integrated	B-General_Concept
memory	I-General_Concept
controllers	I-General_Concept
and	O
an	O
integrated	O
network	O
controller	O
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21364	I-General_Concept
's	O
core	O
is	O
based	O
on	O
the	O
EV68CB	O
,	O
a	O
derivative	O
of	O
the	O
Alpha	B-General_Concept
21264	I-General_Concept
.	O
</s>
<s>
The	O
only	O
modification	O
was	O
a	O
larger	O
victim	B-General_Concept
buffer	I-General_Concept
,	O
now	O
quadrupled	O
in	O
capacity	O
to	O
32	O
entries	O
.	O
</s>
<s>
The	O
32	O
entries	O
of	O
victim	B-General_Concept
buffer	I-General_Concept
is	O
divided	O
equally	O
into	O
16	O
entries	O
each	O
for	O
the	O
Dcache	O
and	O
Scache	O
.	O
</s>
<s>
Although	O
the	O
Alpha	B-General_Concept
21364	I-General_Concept
is	O
a	O
fourth-generation	O
implementation	O
of	O
the	O
Alpha	B-Device
Architecture	O
,	O
aside	O
from	O
this	O
modification	O
,	O
the	O
core	O
is	O
otherwise	O
identical	O
to	O
the	O
EV68CB	O
derivative	O
of	O
the	O
Alpha	B-General_Concept
21264	I-General_Concept
.	O
</s>
<s>
The	O
12-cycle	O
latency	O
was	O
considered	O
by	O
observers	O
,	O
such	O
as	O
the	O
Microprocessor	B-Architecture
Report	O
,	O
to	O
be	O
significant	O
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21264	I-General_Concept
core	O
upon	O
which	O
the	O
Alpha	B-General_Concept
21364	I-General_Concept
was	O
based	O
on	O
was	O
designed	O
to	O
use	O
an	O
external	O
cache	O
built	O
from	O
commodity	O
SRAM	O
,	O
which	O
has	O
a	O
significantly	O
higher	O
latency	O
than	O
the	O
on-die	O
Scache	O
of	O
the	O
Alpha	B-General_Concept
21364	I-General_Concept
.	O
</s>
<s>
Compaq	O
was	O
not	O
willing	O
to	O
remedy	O
this	O
deficiency	O
as	O
it	O
would	O
have	O
required	O
the	O
Alpha	B-General_Concept
21264	I-General_Concept
core	O
to	O
be	O
modified	O
significantly	O
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21364	I-General_Concept
has	O
two	O
integrated	B-General_Concept
memory	I-General_Concept
controllers	I-General_Concept
that	O
support	O
Rambus	O
DRAM	O
(	O
RDRAM	O
)	O
that	O
operate	O
at	O
two	O
thirds	O
of	O
the	O
microprocessor	B-Architecture
's	O
clock	O
frequency	O
,	O
or	O
800MHz	O
at	O
1.2GHz	O
.	O
</s>
<s>
Compaq	O
designed	O
custom	O
memory	B-General_Concept
controllers	I-General_Concept
for	O
the	O
Alpha	B-General_Concept
21364	I-General_Concept
,	O
giving	O
them	O
capabilities	O
not	O
found	O
in	O
standard	O
RDRAM	O
memory	B-General_Concept
controllers	I-General_Concept
such	O
as	O
having	O
all	O
the	O
128	O
pages	O
open	O
,	O
reducing	O
the	O
access	O
latency	O
to	O
those	O
pages	O
;	O
and	O
proprietary	O
fault-tolerant	O
features	O
.	O
</s>
<s>
Each	O
memory	B-General_Concept
controller	I-General_Concept
provides	O
five	O
RDRAM	O
channels	O
that	O
support	O
PC800	O
Rambus	O
inline	O
memory	O
modules	O
(	O
RIMMs	O
)	O
.	O
</s>
<s>
Four	O
of	O
the	O
channels	O
are	O
used	O
to	O
provide	O
memory	O
,	O
while	O
the	O
fifth	O
is	O
used	O
to	O
provide	O
RAID-like	O
redundancy	O
.	O
</s>
<s>
Cache	O
coherence	O
is	O
provided	O
by	O
the	O
memory	B-General_Concept
controllers	I-General_Concept
.	O
</s>
<s>
Each	O
memory	B-General_Concept
controller	I-General_Concept
has	O
a	O
cache	O
coherence	O
engine	O
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21364	I-General_Concept
uses	O
a	O
directory	O
cache	O
coherence	O
scheme	O
where	O
part	O
of	O
the	O
memory	O
is	O
used	O
to	O
store	O
Modified	B-General_Concept
,	I-General_Concept
Exclusive	I-General_Concept
,	I-General_Concept
Shared	I-General_Concept
,	I-General_Concept
Invalid	I-General_Concept
(	O
MESI	B-General_Concept
)	O
coherency	O
data	O
.	O
</s>
<s>
The	O
network	O
router	O
connected	O
the	O
microprocessor	B-Architecture
to	O
other	O
microprocessors	B-Architecture
using	O
four	O
ports	O
named	O
North	O
,	O
South	O
,	O
East	O
and	O
West	O
.	O
</s>
<s>
This	O
port	O
connects	O
to	O
an	O
IO7	O
application-specific	O
integrated	O
circuit	O
(	O
ASIC	O
)	O
,	O
which	O
was	O
a	O
bridge	O
to	O
an	O
AGP	B-Architecture
4x	O
channel	O
and	O
two	O
PCI-X	O
buses	O
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21364	I-General_Concept
can	O
connect	O
to	O
as	O
many	O
as	O
127	O
other	O
microprocessors	B-Architecture
using	O
two	O
network	O
topologies	O
:	O
shuffle	O
and	O
an	O
2D	O
torus	O
.	O
</s>
<s>
The	O
shuffle	O
topology	O
had	O
more	O
direct	O
paths	O
to	O
other	O
microprocessors	B-Architecture
,	O
reducing	O
latency	O
and	O
therefore	O
improving	O
performance	O
,	O
but	O
was	O
limited	O
to	O
connecting	O
up	O
to	O
eight	O
microprocessors	B-Architecture
as	O
a	O
result	O
of	O
its	O
nature	O
.	O
</s>
<s>
The	O
2D	O
torus	O
topology	O
enabled	O
the	O
network	O
to	O
feature	O
up	O
to	O
128	O
microprocessors	B-Architecture
.	O
</s>
<s>
In	O
multiprocessing	B-Operating_System
systems	O
,	O
each	O
microprocessor	B-Architecture
is	O
a	O
node	O
with	O
its	O
own	O
memory	O
.	O
</s>
<s>
The	O
latency	O
increases	O
with	O
distance	O
,	O
thus	O
the	O
Alpha	B-General_Concept
21364	I-General_Concept
implements	O
non-uniform	B-Operating_System
memory	I-Operating_System
access	I-Operating_System
(	O
NUMA	O
)	O
multiprocessing	B-Operating_System
.	O
</s>
<s>
An	O
Alpha	B-General_Concept
21364	I-General_Concept
microprocessor	B-Architecture
in	O
a	O
multiprocessing	B-Operating_System
system	O
did	O
not	O
have	O
to	O
have	O
its	O
RIMM	O
slots	O
populated	O
with	O
memory	O
or	O
its	O
I/O	O
port	O
populated	O
with	O
devices	O
.	O
</s>
<s>
It	O
could	O
use	O
another	O
microprocessor	B-Architecture
's	O
memory	O
and	O
I/O	O
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21364	I-General_Concept
could	O
operate	O
in	O
lock-step	O
for	O
fault-tolerant	O
computers	O
.	O
</s>
<s>
This	O
feature	O
was	O
a	O
result	O
in	O
Compaq	O
's	O
decision	O
to	O
migrate	O
Tandem	O
's	O
Himalaya	O
fault-tolerant	O
servers	O
from	O
the	O
MIPS	B-Device
architecture	I-Device
to	O
Alpha	B-Device
.	O
</s>
<s>
The	O
machines	O
however	O
never	O
used	O
the	O
microprocessor	B-Architecture
as	O
the	O
decision	O
to	O
phase	O
out	O
the	O
Alpha	B-Device
in	O
favor	O
of	O
the	O
Itanium	O
was	O
made	O
before	O
the	O
availability	O
of	O
the	O
Alpha	B-General_Concept
21364	I-General_Concept
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21364	I-General_Concept
contained	O
152	O
million	O
transistors	O
.	O
</s>
<s>
It	O
was	O
fabricated	O
by	O
International	O
Business	O
Machines	O
(	O
IBM	O
)	O
in	O
their	O
0.18µm	O
,	O
seven-level	O
copper	O
complementary	O
metal	O
–	O
oxide	O
–	O
semiconductor	O
(	O
CMOS	B-Device
)	O
process	B-Architecture
.	O
</s>
<s>
It	O
was	O
packaged	O
in	O
a	O
1,443	O
-land	O
flip-chip	B-Device
land	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
LGA	O
)	O
.	O
</s>
<s>
The	O
Alpha	B-Device
21364A	O
,	O
code-named	O
EV79	O
,	O
previously	O
EV78	O
,	O
was	O
a	O
further	O
development	O
of	O
the	O
Alpha	B-General_Concept
21364	I-General_Concept
.	O
</s>
<s>
It	O
was	O
intended	O
to	O
be	O
the	O
last	O
Alpha	B-Device
microprocessor	B-Architecture
developed	O
.	O
</s>
<s>
A	O
prototype	O
of	O
the	O
microprocessor	B-Architecture
was	O
presented	O
by	O
Hewlett-Packard	O
at	O
the	O
International	O
Solid-State	O
Circuits	O
Conference	O
in	O
February	O
2003	O
.	O
</s>
<s>
The	O
Alpha	B-Device
21364A	O
was	O
to	O
have	O
improved	O
upon	O
the	O
Alpha	B-General_Concept
21364	I-General_Concept
by	O
featuring	O
higher	O
clock	O
frequencies	O
in	O
the	O
range	O
of	O
~	O
1.6	O
to	O
~	O
1.7GHz	O
and	O
support	O
for	O
1066	O
Mbit/s	O
RDRAM	O
memory	O
.	O
</s>
<s>
It	O
was	O
to	O
be	O
fabricated	O
by	O
IBM	O
in	O
their	O
0.13µm	O
silicon	B-Algorithm
on	I-Algorithm
insulator	I-Algorithm
(	O
SOI	O
)	O
process	B-Architecture
.	O
</s>
<s>
As	O
a	O
result	O
of	O
the	O
more	O
advanced	O
process	B-Architecture
,	O
there	O
were	O
reductions	O
in	O
die	O
size	O
,	O
power	O
supply	O
voltage	O
(	O
1.2	O
V	O
compared	O
to	O
1.65	O
V	O
)	O
,	O
and	O
in	O
power	O
consumption	O
and	O
dissipation	O
.	O
</s>
<s>
The	O
EV7z	O
was	O
a	O
further	O
development	O
of	O
the	O
Alpha	B-General_Concept
21364	I-General_Concept
.	O
</s>
<s>
It	O
was	O
the	O
last	O
Alpha	B-Device
microprocessor	B-Architecture
developed	O
and	O
introduced	O
.	O
</s>
<s>
The	O
EV7z	O
became	O
known	O
on	O
23	O
October	O
2003	O
when	O
HP	O
announced	O
they	O
had	O
cancelled	O
the	O
Alpha	B-Device
21364A	O
and	O
would	O
be	O
replacing	O
it	O
with	O
the	O
EV7z	O
.	O
</s>
<s>
The	O
EV7z	O
was	O
introduced	O
on	O
16	O
August	O
2004	O
when	O
the	O
only	O
computer	O
using	O
the	O
microprocessor	B-Architecture
,	O
AlphaServer	B-Device
GS1280	I-Device
,	O
was	O
introduced	O
.	O
</s>
<s>
It	O
operated	O
at	O
1.3GHz	O
,	O
supported	O
PC1066	O
RIMMs	O
and	O
was	O
fabricated	O
in	O
the	O
same	O
0.18µm	O
process	B-Architecture
as	O
the	O
Alpha	B-General_Concept
21364	I-General_Concept
.	O
</s>
<s>
Compared	O
to	O
the	O
Alpha	B-General_Concept
21364	I-General_Concept
,	O
the	O
EV7z	O
was	O
14	O
to	O
16	O
percent	O
faster	O
,	O
but	O
was	O
still	O
slower	O
than	O
the	O
Alpha	B-Device
21364A	O
it	O
replaced	O
,	O
which	O
was	O
estimated	O
to	O
outperform	O
the	O
Alpha	B-General_Concept
21364	I-General_Concept
by	O
25	O
percent	O
at	O
1.5GHz	O
.	O
</s>
