<s>
The	O
Alpha	B-General_Concept
21264	I-General_Concept
is	O
a	O
Digital	O
Equipment	O
Corporation	O
RISC	B-Architecture
microprocessor	B-Architecture
launched	O
on	O
19	O
October	O
1998	O
.	O
</s>
<s>
The	O
21264	O
implemented	O
the	O
Alpha	B-Device
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21264	I-General_Concept
is	O
a	O
four-issue	O
superscalar	B-General_Concept
microprocessor	B-Architecture
with	O
out-of-order	B-General_Concept
execution	I-General_Concept
and	O
speculative	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
It	O
has	O
a	O
seven-stage	O
instruction	B-General_Concept
pipeline	I-General_Concept
.	O
</s>
<s>
At	O
any	O
given	O
stage	O
,	O
the	O
microprocessor	B-Architecture
could	O
have	O
up	O
to	O
80	O
instructions	O
in	O
various	O
stages	O
of	O
execution	O
,	O
surpassing	O
any	O
other	O
contemporary	O
microprocessor	B-Architecture
.	O
</s>
<s>
The	O
integer	O
queue	O
contained	O
20	O
entries	O
and	O
the	O
floating-point	B-Algorithm
queue	O
15	O
.	O
</s>
<s>
The	O
Ebox	O
executes	O
integer	O
,	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
.	O
</s>
<s>
It	O
has	O
two	O
integer	O
units	O
,	O
two	O
load	O
store	O
units	O
and	O
two	O
integer	O
register	B-General_Concept
files	I-General_Concept
.	O
</s>
<s>
Each	O
integer	O
register	B-General_Concept
file	I-General_Concept
contained	O
80	O
entries	O
,	O
of	O
which	O
32	O
are	O
architectural	O
registers	O
,	O
40	O
are	O
rename	O
registers	O
and	O
8	O
are	O
PAL	O
shadow	O
registers	O
.	O
</s>
<s>
There	O
was	O
no	O
entry	O
for	O
register	O
R31	O
because	O
in	O
the	O
Alpha	B-Device
architecture	O
,	O
R31	O
is	O
hardwired	O
to	O
zero	O
and	O
is	O
read-only	O
.	O
</s>
<s>
Each	O
register	B-General_Concept
file	I-General_Concept
served	O
an	O
integer	O
unit	O
and	O
a	O
load	O
store	O
unit	O
,	O
and	O
the	O
register	B-General_Concept
file	I-General_Concept
and	O
its	O
two	O
units	O
are	O
referred	O
to	O
as	O
a	O
"	O
cluster	O
"	O
.	O
</s>
<s>
This	O
scheme	O
was	O
used	O
as	O
it	O
reduced	O
the	O
number	O
of	O
write	O
and	O
read	O
ports	O
required	O
to	O
serve	O
operands	O
and	O
receive	O
results	O
,	O
thus	O
reducing	O
the	O
physical	O
size	O
of	O
the	O
register	B-General_Concept
file	I-General_Concept
,	O
enabling	O
the	O
microprocessor	B-Architecture
to	O
operate	O
at	O
higher	O
clock	O
frequencies	O
.	O
</s>
<s>
Writes	O
to	O
any	O
of	O
the	O
register	B-General_Concept
files	I-General_Concept
thus	O
have	O
to	O
be	O
synchronized	O
,	O
which	O
required	O
a	O
clock	O
cycle	O
to	O
complete	O
,	O
negatively	O
impacting	O
performance	O
by	O
one	O
percent	O
.	O
</s>
<s>
Secondly	O
,	O
the	O
logic	O
responsible	O
for	O
instruction	O
issue	O
avoided	O
creating	O
situations	O
where	O
the	O
register	B-General_Concept
file	I-General_Concept
had	O
to	O
be	O
synchronized	O
by	O
issuing	O
instructions	O
that	O
were	O
not	O
dependent	O
on	O
data	O
held	O
in	O
other	O
register	B-General_Concept
file	I-General_Concept
where	O
possible	O
.	O
</s>
<s>
The	O
clusters	O
are	O
near	O
identical	O
except	O
for	O
two	O
differences	O
:	O
U1	O
has	O
a	O
seven-cycle	O
pipelined	O
multiplier	O
while	O
U0	O
has	O
a	O
three-cycle	O
pipeline	O
for	O
executing	O
Motion	B-Device
Video	I-Device
Instructions	I-Device
(	O
MVI	O
)	O
,	O
an	O
extension	O
to	O
the	O
Alpha	B-Device
Architecture	O
defining	O
single	O
instruction	O
multiple	O
data	O
(	O
SIMD	O
)	O
instructions	O
for	O
multimedia	O
.	O
</s>
<s>
The	O
load	O
store	O
units	O
are	O
simple	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
used	O
to	O
calculate	O
virtual	O
addresses	O
for	O
memory	O
access	O
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21264	I-General_Concept
instruction	O
issue	O
logic	O
utilized	O
this	O
capability	O
,	O
issuing	O
instructions	O
to	O
these	O
units	O
when	O
they	O
were	O
available	O
for	O
use	O
(	O
not	O
performing	O
address	B-Architecture
arithmetic	O
)	O
.	O
</s>
<s>
The	O
Fbox	O
is	O
responsible	O
for	O
executing	O
floating-point	B-Algorithm
instructions	O
.	O
</s>
<s>
It	O
consists	O
of	O
two	O
floating-point	B-Algorithm
pipelines	O
and	O
a	O
floating-point	B-Algorithm
register	B-General_Concept
file	I-General_Concept
.	O
</s>
<s>
The	O
floating	B-Algorithm
point	I-Algorithm
register	B-General_Concept
file	I-General_Concept
contains	O
72	O
entries	O
,	O
of	O
which	O
32	O
are	O
architectural	O
registers	O
and	O
40	O
are	O
rename	O
registers	O
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21264	I-General_Concept
has	O
two	O
levels	O
of	O
cache	B-General_Concept
,	O
a	O
primary	O
cache	B-General_Concept
and	O
secondary	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
The	O
level	O
three	O
(	O
L3	O
,	O
or	O
"	O
victim	O
"	O
)	O
cache	B-General_Concept
of	O
the	O
Alpha	B-General_Concept
21164	I-General_Concept
was	O
not	O
used	O
due	O
to	O
problems	O
with	O
bandwidth	O
.	O
</s>
<s>
The	O
primary	O
cache	B-General_Concept
is	O
split	O
into	O
separate	O
caches	O
for	O
instructions	O
and	O
data	O
(	O
"	O
modified	B-Device
Harvard	I-Device
architecture	I-Device
"	O
)	O
,	O
the	O
I-cache	O
and	O
D-cache	O
,	O
respectively	O
.	O
</s>
<s>
The	O
D-cache	O
is	O
dual-ported	O
by	O
transferring	O
data	O
on	O
both	O
the	O
rising	O
and	O
falling	O
edges	O
of	O
the	O
clock	O
signal	O
.	O
</s>
<s>
This	O
method	O
of	O
dual-porting	O
enabled	O
any	O
combination	O
of	O
reads	O
or	O
writes	O
to	O
the	O
cache	B-General_Concept
every	O
processor	O
cycle	O
.	O
</s>
<s>
It	O
also	O
avoided	O
duplication	O
the	O
cache	B-General_Concept
so	O
there	O
are	O
two	O
,	O
as	O
in	O
the	O
Alpha	B-General_Concept
21164	I-General_Concept
.	O
</s>
<s>
Duplicating	O
the	O
cache	B-General_Concept
restricted	O
the	O
capacity	O
of	O
the	O
cache	B-General_Concept
,	O
as	O
it	O
required	O
more	O
transistors	O
to	O
provide	O
the	O
same	O
amount	O
of	O
capacity	O
,	O
and	O
in	O
turn	O
increased	O
the	O
area	O
required	O
and	O
power	O
consumed	O
.	O
</s>
<s>
The	O
secondary	B-General_Concept
cache	I-General_Concept
,	O
termed	O
the	O
B-cache	O
,	O
is	O
an	O
external	O
cache	B-General_Concept
with	O
a	O
capacity	O
of	O
1	O
to	O
16	O
MB	O
.	O
</s>
<s>
It	O
is	O
controlled	O
by	O
the	O
microprocessor	B-Architecture
and	O
is	O
implemented	O
by	O
synchronous	O
static	B-Architecture
random	I-Architecture
access	I-Architecture
memory	I-Architecture
(	O
SSRAM	O
)	O
chips	O
that	O
operate	O
at	O
two	O
thirds	O
,	O
half	O
,	O
one-third	O
or	O
one-fourth	O
the	O
internal	O
clock	O
frequency	O
,	O
or	O
133	O
to	O
333MHz	O
at	O
500MHz	O
.	O
</s>
<s>
The	O
B-cache	O
was	O
accessed	O
with	O
a	O
dedicated	O
128-bit	O
bus	O
that	O
operates	O
at	O
the	O
same	O
clock	O
frequency	O
as	O
the	O
SSRAM	O
or	O
at	O
twice	O
the	O
clock	O
frequency	O
if	O
double	O
data	O
rate	O
SSRAM	O
is	O
used	O
.	O
</s>
<s>
The	O
B-cache	O
is	O
direct-mapped	O
.	O
</s>
<s>
Branch	B-General_Concept
prediction	I-General_Concept
is	O
performed	O
by	O
a	O
tournament	O
branch	B-General_Concept
prediction	I-General_Concept
algorithm	O
.	O
</s>
<s>
This	O
predictor	O
was	O
used	O
as	O
the	O
Alpha	B-General_Concept
21264	I-General_Concept
has	O
a	O
minimum	O
branch	B-General_Concept
misprediction	I-General_Concept
penalty	O
of	O
seven	O
cycles	O
.	O
</s>
<s>
Due	O
to	O
the	O
instruction	O
cache	B-General_Concept
's	O
two	O
cycle	O
latency	O
and	O
the	O
instruction	O
queues	O
,	O
the	O
average	O
branch	B-General_Concept
misprediction	I-General_Concept
penalty	O
is	O
11	O
cycles	O
.	O
</s>
<s>
The	O
local	B-General_Concept
predictor	I-General_Concept
is	O
a	O
two-level	O
table	O
which	O
records	O
the	O
history	O
of	O
individual	O
branches	O
.	O
</s>
<s>
It	O
has	O
a	O
1,024	O
-entry	O
branch	B-General_Concept
prediction	I-General_Concept
table	O
.	O
</s>
<s>
The	O
global	B-General_Concept
predictor	I-General_Concept
is	O
a	O
single-level	O
,	O
4096-entry	O
branch	O
history	O
table	O
.	O
</s>
<s>
The	O
choice	O
predictor	O
records	O
the	O
history	O
of	O
the	O
local	O
and	O
global	B-General_Concept
predictors	I-General_Concept
to	O
determine	O
which	O
predictor	O
is	O
the	O
best	O
for	O
a	O
particular	O
branch	O
.	O
</s>
<s>
The	O
value	O
of	O
the	O
counter	O
determines	O
if	O
the	O
local	O
or	O
global	B-General_Concept
predictor	I-General_Concept
is	O
used	O
.	O
</s>
<s>
The	O
external	O
interface	O
consisted	O
of	O
a	O
bidirectional	O
64-bit	O
double	O
data	O
rate	O
(	O
DDR	O
)	O
data	B-General_Concept
bus	I-General_Concept
and	O
two	O
15-bit	O
unidirectional	O
time-multiplexed	O
address	B-Architecture
and	O
control	B-Architecture
buses	O
,	O
one	O
for	O
signals	O
originating	O
from	O
the	O
Alpha	B-General_Concept
21264	I-General_Concept
and	O
one	O
for	O
signals	O
originating	O
from	O
the	O
system	O
.	O
</s>
<s>
Digital	O
licensed	O
the	O
bus	O
to	O
Advanced	O
Micro	O
Devices	O
(	O
AMD	O
)	O
,	O
and	O
it	O
was	O
subsequently	O
used	O
in	O
their	O
Athlon	B-Architecture
microprocessors	B-Architecture
,	O
where	O
it	O
was	O
known	O
as	O
the	O
EV6	O
bus	O
.	O
</s>
<s>
Alpha	B-General_Concept
21264	I-General_Concept
CPU	O
supports	O
48-bit	O
or	O
43-bit	O
virtual	B-General_Concept
address	I-General_Concept
(	O
256	O
TiB	O
or	O
8	O
TiB	O
virtual	B-General_Concept
address	I-General_Concept
space	I-General_Concept
respectively	O
)	O
,	O
selectable	O
under	O
IPR	O
control	B-Architecture
(	O
using	O
VA_CTL	O
control	B-Architecture
register	O
)	O
.	O
</s>
<s>
Alpha	B-General_Concept
21264	I-General_Concept
supports	O
a	O
44-bit	O
physical	O
address	B-Architecture
(	O
up	O
to	O
16	O
TiB	O
of	O
physical	O
memory	O
)	O
.	O
</s>
<s>
This	O
is	O
an	O
increase	O
from	O
previous	O
Alpha	B-Device
CPUs	I-Device
(	O
43-bit	O
virtual	O
and	O
40-bit	O
physical	O
for	O
Alpha	B-General_Concept
21164	I-General_Concept
,	O
and	O
43-bit	O
virtual	O
and	O
34-bit	O
physical	O
for	O
Alpha	B-General_Concept
21064	I-General_Concept
)	O
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21264	I-General_Concept
contained	O
15.2	O
million	O
transistors	O
.	O
</s>
<s>
It	O
was	O
fabricated	O
in	O
a	O
0.35μm	O
complementary	O
metal	O
–	O
oxide	O
–	O
semiconductor	O
(	O
CMOS	B-Device
)	O
process	B-Architecture
with	O
six	O
levels	O
of	O
interconnect	B-General_Concept
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21264	I-General_Concept
was	O
packaged	O
in	O
a	O
587-pin	O
ceramic	O
interstitial	O
pin	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
IPGA	O
)	O
.	O
</s>
<s>
Alpha	B-Device
Processor	I-Device
,	O
Inc	O
.	O
later	O
sold	O
the	O
Alpha	B-General_Concept
21264	I-General_Concept
in	O
a	O
Slot	O
B	O
package	O
containing	O
the	O
microprocessor	B-Architecture
mounted	O
on	O
a	O
printed	O
circuit	O
board	O
with	O
the	O
B-cache	O
and	O
voltage	O
regulators	O
.	O
</s>
<s>
The	O
design	O
was	O
intended	O
to	O
use	O
the	O
success	O
of	O
slot-based	O
microprocessors	B-Architecture
from	O
Intel	O
and	O
AMD	O
.	O
</s>
<s>
Slot	O
B	O
was	O
originally	O
developed	O
to	O
be	O
used	O
by	O
AMD	O
's	O
Athlon	B-Architecture
as	O
well	O
,	O
so	O
that	O
API	O
could	O
obtain	O
materials	O
for	O
the	O
Slot	O
B	O
at	O
commodity	O
prices	O
in	O
order	O
to	O
reduce	O
the	O
cost	O
of	O
the	O
Alpha	B-General_Concept
21264	I-General_Concept
to	O
gain	O
a	O
wider	O
market	O
share	O
.	O
</s>
<s>
This	O
never	O
materialized	O
as	O
AMD	O
chose	O
to	O
use	O
Slot	O
A	O
for	O
their	O
slot-based	O
Athlons	B-Architecture
.	O
</s>
<s>
The	O
Alpha	B-Device
21264A	O
,	O
code-named	O
EV67	O
was	O
a	O
shrink	O
of	O
the	O
Alpha	B-General_Concept
21264	I-General_Concept
introduced	O
in	O
late	O
1999	O
.	O
</s>
<s>
The	O
EV67	O
was	O
the	O
first	O
Alpha	B-Device
microprocessor	B-Architecture
to	O
implement	O
the	O
count	O
extension	O
(	O
CIX	O
)	O
,	O
which	O
extended	O
the	O
instruction	B-General_Concept
set	I-General_Concept
with	O
instructions	O
for	O
performing	O
population	O
count	O
.	O
</s>
<s>
It	O
was	O
fabricated	O
by	O
Samsung	O
Electronics	O
in	O
a	O
0.25μm	O
CMOS	B-Device
process	B-Architecture
that	O
had	O
0.25μm	O
transistors	O
but	O
0.35μm	O
metal	O
layers	O
.	O
</s>
<s>
The	O
Alpha	B-Device
21264B	O
is	O
a	O
further	O
development	O
for	O
increased	O
clock	O
frequencies	O
.	O
</s>
<s>
The	O
EV68A	O
was	O
fabricated	O
in	O
a	O
0.18μm	O
CMOS	B-Device
process	B-Architecture
with	O
aluminium	O
interconnects	B-General_Concept
.	O
</s>
<s>
It	O
had	O
a	O
die	O
size	O
of	O
125mm²	O
,	O
a	O
third	O
smaller	O
than	O
the	O
Alpha	B-Device
21264A	O
,	O
and	O
used	O
a	O
1.7	O
V	O
power	O
supply	O
.	O
</s>
<s>
The	O
EV68C	O
was	O
fabricated	O
in	O
a	O
0.18μm	O
CMOS	B-Device
process	B-Architecture
with	O
copper	O
interconnects	B-General_Concept
.	O
</s>
<s>
In	O
September	O
1998	O
,	O
Samsung	O
announced	O
they	O
would	O
fabricate	O
a	O
variant	O
of	O
the	O
Alpha	B-Device
21264B	O
in	O
a	O
0.18μm	O
fully	O
depleted	O
silicon-on-insulator	B-Algorithm
(	O
SOI	O
)	O
process	B-Architecture
with	O
copper	O
interconnects	B-General_Concept
that	O
was	O
capable	O
of	O
achieving	O
a	O
clock	O
frequency	O
of	O
1.5GHz	O
.	O
</s>
<s>
The	O
Alpha	B-Device
21264C	O
,	O
code-named	O
EV68CB	O
was	O
a	O
derivative	O
of	O
the	O
Alpha	B-General_Concept
21264	I-General_Concept
.	O
</s>
<s>
It	O
was	O
fabricated	O
by	O
IBM	O
in	O
a	O
0.18μm	O
CMOS	B-Device
process	B-Architecture
with	O
seven	O
levels	O
of	O
copper	O
interconnect	B-General_Concept
and	O
low-K	B-Algorithm
dielectric	I-Algorithm
.	O
</s>
<s>
It	O
was	O
packaged	O
in	O
a	O
675-pad	O
flip-chip	B-Device
ceramic	B-Algorithm
land	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
CLGA	O
)	O
measuring	O
49.53	O
by	O
49.53mm	O
.	O
</s>
<s>
The	O
Alpha	B-Device
21264D	O
,	O
code-named	O
EV68CD	O
is	O
a	O
faster	O
derivative	O
fabricated	O
by	O
IBM	O
.	O
</s>
<s>
The	O
Alpha	B-Device
21264E	O
,	O
code-named	O
EV68E	O
,	O
was	O
a	O
cancelled	O
derivative	O
developed	O
by	O
Samsung	O
first	O
announced	O
on	O
10	O
October	O
2000	O
at	O
Microprocessor	B-Architecture
Forum	O
2000	O
slated	O
for	O
introduction	O
at	O
around	O
mid-2001	O
.	O
</s>
<s>
Improvements	O
were	O
a	O
higher	O
operating	O
frequency	O
of	O
1.25GHz	O
and	O
the	O
addition	O
of	O
an	O
on-die	O
1.85	O
MB	O
secondary	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
It	O
was	O
to	O
be	O
fabricated	O
in	O
a	O
0.18	O
micrometre	O
CMOS	B-Device
process	B-Architecture
with	O
copper	O
interconnects	B-General_Concept
.	O
</s>
<s>
Digital	O
and	O
Advanced	O
Micro	O
Devices	O
(	O
AMD	O
)	O
both	O
developed	O
chipsets	O
for	O
the	O
Alpha	B-General_Concept
21264	I-General_Concept
.	O
</s>
<s>
The	O
Digital	O
21272	O
,	O
also	O
known	O
as	O
the	O
Tsunami	O
,	O
and	O
the	O
21274	O
,	O
also	O
known	O
as	O
the	O
Typhoon	O
,	O
were	O
the	O
first	O
chipset	O
for	O
the	O
Alpha	B-General_Concept
21264	I-General_Concept
.	O
</s>
<s>
The	O
21272	O
chipset	O
supported	O
one	O
-	O
or	O
two-way	O
multiprocessing	O
and	O
up	O
to	O
8GB	O
of	O
memory	O
,	O
while	O
the	O
21274	O
supported	O
one-	O
,	O
two-	O
,	O
three	O
-	O
or	O
four-way	O
multiprocessing	O
,	O
up	O
to	O
64GB	O
of	O
memory	O
,	O
and	O
both	O
supported	O
one	O
or	O
two	O
64-bit	O
33MHz	O
PCI	B-Protocol
buses	O
.	O
</s>
<s>
The	O
C-chip	O
is	O
the	O
control	B-Architecture
chip	O
containing	O
the	O
memory	O
controller	O
.	O
</s>
<s>
One	O
C-chip	O
was	O
required	O
for	O
every	O
microprocessor	B-Architecture
.	O
</s>
<s>
The	O
P-chip	O
is	O
the	O
PCI	B-Protocol
controller	O
,	O
implementing	O
a	O
33MHz	O
PCI	B-Protocol
bus	I-Protocol
.	O
</s>
<s>
It	O
was	O
also	O
used	O
in	O
third-party	O
products	O
from	O
Alpha	B-Device
Processor	I-Device
,	O
Inc	O
.	O
(	O
later	O
known	O
as	O
API	O
NetWorks	O
)	O
such	O
as	O
their	O
UP2000+	O
motherboard	O
.	O
</s>
<s>
These	O
chipsets	O
were	O
developed	O
for	O
their	O
Athlon	B-Architecture
microprocessors	B-Architecture
but	O
due	O
to	O
AMD	O
licensing	O
the	O
EV6	O
bus	O
used	O
in	O
the	O
Alpha	B-Device
from	O
Digital	O
,	O
the	O
Athlon	B-Architecture
and	O
Alpha	B-General_Concept
21264	I-General_Concept
were	O
compatible	O
in	O
terms	O
of	O
bus	O
protocol	O
.	O
</s>
