<s>
The	O
Alpha	B-Device
21064	O
is	O
a	O
microprocessor	B-Architecture
developed	O
and	O
fabricated	O
by	O
Digital	O
Equipment	O
Corporation	O
that	O
implemented	O
the	O
Alpha	B-Device
(	O
introduced	O
as	O
the	O
Alpha	B-Device
AXP	I-Device
)	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
.	O
</s>
<s>
The	O
21064	O
was	O
the	O
first	O
commercial	O
implementation	O
of	O
the	O
Alpha	B-Device
ISA	O
,	O
and	O
the	O
first	O
microprocessor	B-Architecture
from	O
Digital	O
to	O
be	O
available	O
commercially	O
.	O
</s>
<s>
It	O
was	O
succeeded	O
by	O
a	O
derivative	O
,	O
the	O
Alpha	B-Device
21064A	I-Device
in	O
October	O
1993	O
.	O
</s>
<s>
This	O
last	O
version	O
was	O
replaced	O
by	O
the	O
Alpha	B-General_Concept
21164	I-General_Concept
in	O
1995	O
.	O
</s>
<s>
The	O
first	O
Alpha	B-Device
processor	I-Device
was	O
a	O
test	O
chip	O
codenamed	O
EV3	O
.	O
</s>
<s>
The	O
test	O
chip	O
lacked	O
a	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
and	O
only	O
had	O
1KB	O
caches	O
.	O
</s>
<s>
The	O
test	O
chip	O
,	O
along	O
with	O
simulators	O
and	O
emulators	O
,	O
was	O
also	O
used	O
to	O
bring	O
up	O
firmware	B-Application
and	O
the	O
various	O
operating	B-General_Concept
systems	I-General_Concept
that	O
the	O
company	O
supported	O
.	O
</s>
<s>
The	O
EV3	O
was	O
used	O
in	O
the	O
Alpha	B-Device
Demonstration	O
Unit	O
(	O
ADU	O
)	O
,	O
a	O
multiprocessor	B-Operating_System
system	O
used	O
by	O
Digital	O
to	O
develop	O
software	O
for	O
the	O
Alpha	B-Device
platform	O
before	O
the	O
availability	O
of	O
EV4	O
parts	O
.	O
</s>
<s>
With	O
the	O
introduction	O
of	O
the	O
Alpha	B-Device
21066	O
and	O
the	O
Alpha	B-Device
21068	O
on	O
10	O
September	O
1993	O
,	O
Digital	O
adjusted	O
the	O
positioning	O
of	O
the	O
existing	O
21064s	O
and	O
introduced	O
a	O
166MHz	O
version	O
priced	O
at	O
$499	O
per	O
unit	O
in	O
quantities	O
of	O
5,000	O
.	O
</s>
<s>
The	O
Alpha	B-Device
21064	O
was	O
fabricated	O
at	O
Digital	O
's	O
Hudson	O
,	O
Massachusetts	O
and	O
South	O
Queensferry	O
,	O
Scotland	O
facilities	B-Algorithm
.	O
</s>
<s>
The	O
21064	O
was	O
mostly	O
used	O
in	O
high-end	O
computers	O
such	O
as	O
workstations	B-Device
and	O
servers	O
.	O
</s>
<s>
The	O
21064	O
was	O
the	O
highest	O
performing	O
microprocessor	B-Architecture
from	O
when	O
it	O
was	O
introduced	O
until	O
1993	O
,	O
after	O
International	O
Business	O
Machines	O
(	O
IBM	O
)	O
introduced	O
the	O
multi-chip	O
POWER2	B-General_Concept
.	O
</s>
<s>
It	O
subsequently	O
became	O
the	O
highest	O
performing	O
single-chip	O
microprocessor	B-Architecture
,	O
a	O
position	O
it	O
held	O
until	O
the	O
275MHz	O
21064A	O
was	O
introduced	O
in	O
October	O
1993	O
.	O
</s>
<s>
The	O
Alpha	B-Device
21064	O
is	O
a	O
superpipelined	B-General_Concept
dual-issue	O
superscalar	B-General_Concept
microprocessor	B-Architecture
that	O
executes	O
instructions	O
in-order	O
.	O
</s>
<s>
It	O
is	O
capable	O
of	O
issuing	O
up	O
to	O
two	O
instructions	O
every	O
clock	O
cycle	O
to	O
four	O
functional	O
units	O
:	O
an	O
integer	B-General_Concept
unit	I-General_Concept
,	O
a	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
,	O
an	O
address	O
unit	O
,	O
and	O
a	O
branch	O
unit	O
.	O
</s>
<s>
The	O
integer	O
pipeline	B-General_Concept
is	O
seven	O
stages	O
long	O
,	O
and	O
the	O
floating-point	O
pipeline	B-General_Concept
ten	O
stages	O
.	O
</s>
<s>
The	O
I-box	O
is	O
the	O
control	B-General_Concept
unit	I-General_Concept
;	O
it	O
fetches	O
,	O
decodes	O
,	O
and	O
issues	O
instructions	O
and	O
controls	O
the	O
pipeline	B-General_Concept
.	O
</s>
<s>
During	O
stage	O
one	O
,	O
two	O
instructions	O
are	O
fetched	O
from	O
the	O
I-cache	O
.	O
</s>
<s>
Branch	B-General_Concept
prediction	I-General_Concept
is	O
performed	O
by	O
logic	O
in	O
the	O
I-box	O
during	O
stage	O
two	O
.	O
</s>
<s>
Static	O
prediction	O
examined	O
the	O
sign	B-Algorithm
bit	I-Algorithm
of	O
the	O
displacement	O
field	O
of	O
a	O
branch	B-General_Concept
instruction	I-General_Concept
,	O
predicted	O
the	O
branch	O
as	O
taken	O
if	O
the	O
sign	B-Algorithm
bit	I-Algorithm
indicated	O
a	O
backwards	O
branch	O
(	O
if	O
sign	B-Algorithm
bit	I-Algorithm
contained	O
1	O
)	O
.	O
</s>
<s>
If	O
dynamic	O
prediction	O
was	O
utilized	O
,	O
the	O
branch	B-General_Concept
prediction	I-General_Concept
is	O
approximately	O
80%	O
accurate	O
for	O
most	O
programs	O
.	O
</s>
<s>
The	O
branch	B-General_Concept
misprediction	I-General_Concept
penalty	O
is	O
four	O
cycles	O
.	O
</s>
<s>
Which	O
instructions	O
could	O
be	O
paired	O
was	O
determined	O
by	O
the	O
number	O
of	O
read	O
and	O
write	O
ports	O
in	O
the	O
integer	O
register	B-General_Concept
file	I-General_Concept
.	O
</s>
<s>
The	O
21064	O
could	O
issue	O
:	O
an	O
integer	O
operate	O
with	O
a	O
floating-point	O
operate	O
,	O
any	O
load/store	B-General_Concept
instruction	I-General_Concept
with	O
any	O
operate	O
instruction	O
,	O
an	O
integer	O
operate	O
with	O
an	O
integer	O
branch	O
,	O
or	O
a	O
floating-point	O
operate	O
with	O
a	O
floating-point	O
branch	O
.	O
</s>
<s>
The	O
I-box	O
contains	O
two	O
translation	B-Architecture
lookaside	I-Architecture
buffers	I-Architecture
(	O
TLBs	O
)	O
for	O
translating	O
virtual	O
addresses	O
to	O
physical	O
addresses	O
.	O
</s>
<s>
The	O
ITBs	O
cache	B-General_Concept
recently	O
used	O
page	B-General_Concept
table	I-General_Concept
entries	I-General_Concept
for	O
the	O
instruction	O
stream	O
.	O
</s>
<s>
The	O
register	B-General_Concept
files	I-General_Concept
are	O
read	O
during	O
stage	O
four	O
.	O
</s>
<s>
The	O
integer	B-General_Concept
unit	I-General_Concept
is	O
responsible	O
for	O
executing	O
integer	O
instructions	O
.	O
</s>
<s>
It	O
consists	O
of	O
the	O
integer	O
register	B-General_Concept
file	I-General_Concept
(	O
IRF	O
)	O
and	O
the	O
E-box	O
.	O
</s>
<s>
The	O
IRF	O
contains	O
thirty-two	O
64-bit	O
registers	O
and	O
has	O
four	O
read	O
ports	O
and	O
two	O
write	O
ports	O
that	O
are	O
equally	O
divided	O
between	O
the	O
integer	B-General_Concept
unit	I-General_Concept
and	O
the	O
branch	O
unit	O
.	O
</s>
<s>
The	O
address	O
unit	O
,	O
also	O
known	O
as	O
the	O
"	O
A-box	O
"	O
,	O
executed	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
.	O
</s>
<s>
To	O
enable	O
the	O
address	O
unit	O
and	O
integer	B-General_Concept
unit	I-General_Concept
to	O
operate	O
in	O
parallel	O
,	O
the	O
address	O
unit	O
has	O
its	O
own	O
displacement	O
adder	O
,	O
which	O
it	O
uses	O
to	O
calculate	O
virtual	O
addresses	O
,	O
instead	O
of	O
using	O
the	O
adder	O
in	O
the	O
integer	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
A	O
32-entry	O
fully	O
associative	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	O
)	O
is	O
used	O
to	O
translate	O
virtual	O
addresses	O
into	O
physical	O
addresses	O
.	O
</s>
<s>
The	O
21064	O
implemented	O
a	O
43-bit	O
virtual	B-General_Concept
address	I-General_Concept
and	O
a	O
34-bit	O
physical	B-General_Concept
address	I-General_Concept
,	O
and	O
is	O
therefore	O
capable	O
of	O
addressing	O
8TB	O
of	O
virtual	B-Architecture
memory	I-Architecture
and	O
16GB	O
of	O
physical	O
memory	O
.	O
</s>
<s>
The	O
floating-point	B-General_Concept
unit	I-General_Concept
consists	O
of	O
the	O
floating-point	O
register	B-General_Concept
file	I-General_Concept
(	O
FRF	O
)	O
and	O
the	O
F-box	O
.	O
</s>
<s>
The	O
F-box	O
contained	O
a	O
floating-point	O
pipeline	B-General_Concept
and	O
a	O
non-pipelined	O
divide	O
unit	O
which	O
retired	O
one	O
bit	O
per	O
cycle	O
.	O
</s>
<s>
The	O
floating-point	O
register	B-General_Concept
file	I-General_Concept
is	O
read	O
and	O
the	O
data	O
formatted	O
into	O
fraction	O
,	O
exponent	O
,	O
and	O
sign	O
in	O
stage	O
four	O
.	O
</s>
<s>
Instructions	O
executed	O
in	O
the	O
pipeline	B-General_Concept
have	O
a	O
six-cycle	O
latency	O
.	O
</s>
<s>
The	O
21064	O
has	O
two	O
on-die	O
primary	O
caches	O
:	O
an	O
8KB	O
data	B-General_Concept
cache	I-General_Concept
(	O
known	O
as	O
the	O
D-cache	O
)	O
using	O
a	O
write-through	O
write	O
policy	O
and	O
an	O
8KB	O
instruction	O
cache	B-General_Concept
(	O
known	O
as	O
the	O
I-cache	O
)	O
.	O
</s>
<s>
The	O
caches	O
are	O
built	O
with	O
six-transistor	O
static	B-Architecture
random	I-Architecture
access	I-Architecture
memory	I-Architecture
(	O
SRAM	O
)	O
cells	O
that	O
have	O
an	O
area	O
of	O
98μm2	O
.	O
</s>
<s>
An	O
optional	O
external	O
secondary	B-General_Concept
cache	I-General_Concept
,	O
known	O
as	O
the	O
B-cache	O
,	O
with	O
capacities	O
of	O
128KB	O
to	O
16MB	O
was	O
supported	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
operated	O
at	O
one-third	O
to	O
one-sixteenth	O
of	O
the	O
internal	O
clock	O
frequency	O
,	O
or	O
12.5	O
to	O
66.67MHz	O
at	O
200MHz	O
.	O
</s>
<s>
The	O
B-cache	O
is	O
direct-mapped	O
and	O
has	O
a	O
128-byte	O
line	O
size	O
by	O
default	O
that	O
could	O
be	O
configured	O
to	O
use	O
larger	O
quantities	O
.	O
</s>
<s>
The	O
B-cache	O
is	O
accessed	O
via	O
the	O
system	O
bus	O
.	O
</s>
<s>
The	O
external	O
interface	O
is	O
a	O
128-bit	O
data	B-General_Concept
bus	I-General_Concept
that	O
operated	O
at	O
half	O
to	O
one-eighth	O
the	O
internal	O
clock	O
rate	O
,	O
or	O
25	O
to	O
100MHz	O
at	O
200MHz	O
.	O
</s>
<s>
The	O
external	O
interface	O
also	O
consisted	O
of	O
a	O
34-bit	O
address	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
The	O
original	O
EV4	O
was	O
fabricated	O
by	O
Digital	O
in	O
its	O
CMOS-4	O
process	O
,	O
which	O
has	O
a	O
0.75μm	O
feature	O
size	O
and	O
three	O
levels	O
of	O
aluminium	O
interconnect	B-General_Concept
.	O
</s>
<s>
The	O
Alpha	B-Device
21064A	I-Device
,	O
introduced	O
as	O
the	O
DECchip	O
21064A	O
,	O
code-named	O
EV45	O
,	O
is	O
a	O
further	O
development	O
of	O
the	O
Alpha	B-Device
21064	O
introduced	O
in	O
October	O
1993	O
.	O
</s>
<s>
There	O
was	O
also	O
one	O
model	O
,	O
the	O
21064A-275-PC	O
,	O
that	O
was	O
restricted	O
to	O
running	O
the	O
Windows	B-Device
NT	I-Device
or	O
operating	B-General_Concept
systems	I-General_Concept
that	O
use	O
the	O
Windows	B-Device
NT	I-Device
memory	O
management	O
model	O
.	O
</s>
<s>
The	O
21064A	O
succeeded	O
the	O
original	O
21064	O
as	O
the	O
high-end	O
Alpha	B-Device
microprocessor	B-Architecture
.	O
</s>
<s>
The	O
primary	O
caches	O
were	O
improved	O
in	O
two	O
ways	O
:	O
the	O
capacity	O
of	O
the	O
I-cache	O
and	O
D-cache	O
was	O
doubled	O
from	O
8KB	O
to	O
16KB	O
and	O
parity	B-Error_Name
protection	O
was	O
added	O
to	O
the	O
cache	B-General_Concept
tag	O
and	O
cache	B-General_Concept
data	O
arrays	O
.	O
</s>
<s>
Branch	B-General_Concept
prediction	I-General_Concept
was	O
improved	O
by	O
a	O
larger	O
4,096	O
-entry	O
by	O
2-bit	O
BHT	O
.	O
</s>
<s>
It	O
was	O
fabricated	O
by	O
Digital	O
in	O
their	O
fifth-generation	O
CMOS	O
process	O
,	O
CMOS-5	O
,	O
a	O
0.5μm	O
process	O
with	O
four	O
levels	O
of	O
aluminium	O
interconnect	B-General_Concept
.	O
</s>
<s>
The	O
Alpha	B-Device
21066	O
,	O
introduced	O
as	O
the	O
DECchip	O
21066	O
,	O
code-named	O
LCA4	O
(	O
Low	O
Cost	O
Alpha	B-Device
)	O
,	O
is	O
a	O
low-cost	O
variant	O
of	O
Alpha	B-Device
21064	O
.	O
</s>
<s>
At	O
the	O
time	O
of	O
introduction	O
,	O
the	O
166MHz	O
Alpha	B-Device
21066	O
was	O
priced	O
at	O
US$385	O
in	O
quantities	O
of	O
5,000	O
.	O
</s>
<s>
A	O
100MHz	O
model	O
,	O
intended	O
for	O
embedded	B-Architecture
systems	I-Architecture
,	O
also	O
existed	O
.	O
</s>
<s>
The	O
Microprocessor	B-Architecture
Report	O
recognized	O
the	O
Alpha	B-Device
21066	O
as	O
the	O
first	O
microprocessor	B-Architecture
with	O
an	O
integrated	O
PCI	O
controller	O
.	O
</s>
<s>
The	O
Alpha	B-Device
21066	O
was	O
intended	O
for	O
use	O
in	O
low-cost	O
applications	O
,	O
specifically	O
personal	B-Device
computers	I-Device
running	O
Windows	B-Device
NT	I-Device
.	O
</s>
<s>
Digital	O
used	O
various	O
models	O
of	O
the	O
Alpha	B-Device
21066	O
in	O
their	O
Multia	B-Device
clients	O
,	O
AXPpci	O
33	O
original	O
equipment	O
manufacturer	O
(	O
OEM	O
)	O
motherboards	O
and	O
AXPvme	O
single-board	B-Device
computers	I-Device
.	O
</s>
<s>
Outside	O
of	O
Digital	O
,	O
users	O
included	O
Aspen	O
Systems	O
in	O
its	O
Alpine	O
workstation	B-Device
,	O
Carrera	O
Computers	O
in	O
its	O
Pantera	O
I	O
workstation	B-Device
,	O
NekoTech	O
used	O
a	O
166MHz	O
model	O
in	O
its	O
Mach	O
1-166	O
personal	B-Device
computer	I-Device
,	O
and	O
Parsys	O
in	O
its	O
TransAlpha	O
TA9000	O
Series	O
supercomputers	B-Architecture
.	O
</s>
<s>
Due	O
to	O
the	O
process	O
shrink	O
,	O
it	O
was	O
able	O
to	O
include	O
features	O
that	O
were	O
desirable	O
in	O
cost-sensitive	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
These	O
features	O
include	O
an	O
on-die	O
B-cache	O
and	O
memory	B-General_Concept
controller	I-General_Concept
with	O
ECC	B-General_Concept
support	O
,	O
a	O
functionally	O
limited	O
graphics	B-Architecture
accelerator	I-Architecture
supporting	O
up	O
to	O
8	O
MB	O
of	O
VRAM	O
for	O
implementing	O
a	O
framebuffer	B-Algorithm
,	O
a	O
PCI	O
controller	O
and	O
a	O
phase-locked	O
loop	O
(	O
PLL	O
)	O
clock	O
generator	O
for	O
multiplying	O
a	O
33MHz	O
external	O
clock	O
signal	O
to	O
the	O
desired	O
internal	O
clock	O
frequency	O
.	O
</s>
<s>
The	O
memory	B-General_Concept
controller	I-General_Concept
supported	O
64	O
KB	O
to	O
2	O
MB	O
of	O
B-cache	O
and	O
2	O
to	O
512	O
MB	O
of	O
memory	O
.	O
</s>
<s>
The	O
ECC	B-General_Concept
implementation	O
was	O
capable	O
of	O
detecting	O
1-	O
,	O
2	O
-	O
and	O
4-bit	O
errors	O
and	O
correcting	O
1-bit	O
errors	O
.	O
</s>
<s>
To	O
reduce	O
cost	O
,	O
the	O
Alpha	B-Device
21066	O
has	O
a	O
64-bit	O
system	O
bus	O
,	O
which	O
reduced	O
the	O
number	O
of	O
pins	O
and	O
thus	O
the	O
size	O
of	O
the	O
package	O
.	O
</s>
<s>
It	O
was	O
fabricated	O
in	O
CMOS-4S	O
,	O
a	O
0.675μm	O
process	O
with	O
three	O
levels	O
of	O
interconnect	B-General_Concept
.	O
</s>
<s>
The	O
Alpha	B-Device
21066A	O
,	O
code-named	O
LCA45	O
,	O
is	O
a	O
low-cost	O
variant	O
of	O
the	O
Alpha	B-Device
21064A	I-Device
.	O
</s>
<s>
It	O
was	O
the	O
first	O
Alpha	B-Device
microprocessor	B-Architecture
to	O
be	O
fabricated	O
by	O
the	O
company	O
.	O
</s>
<s>
Although	O
it	O
was	O
based	O
on	O
the	O
21064A	O
,	O
the	O
21066A	O
did	O
not	O
have	O
the	O
16	O
KB	O
instruction	O
and	O
data	B-General_Concept
caches	I-General_Concept
.	O
</s>
<s>
A	O
feature	O
specific	O
to	O
the	O
21066A	O
was	O
power	O
management	O
–	O
the	O
microprocessor	B-Architecture
's	O
internal	O
clock	O
frequency	O
could	O
be	O
adjusted	O
by	O
software	O
.	O
</s>
<s>
Outside	O
of	O
Digital	O
,	O
Tadpole	B-Architecture
Technology	I-Architecture
used	O
a	O
233MHz	O
model	O
in	O
their	O
ALPHAbook	O
1	O
notebook	B-Device
.	O
</s>
<s>
It	O
was	O
fabricated	O
in	O
Digital	O
's	O
fifth-generation	O
CMOS	O
process	O
,	O
CMOS-5	O
,	O
a	O
0.5μm	O
process	O
with	O
three	O
levels	O
of	O
interconnect	B-General_Concept
.	O
</s>
<s>
The	O
Alpha	B-Device
21068	O
,	O
introduced	O
as	O
the	O
DECchip	O
21068	O
,	O
is	O
a	O
version	O
of	O
the	O
21066	O
positioned	O
for	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
The	O
Alpha	B-Device
21068	O
was	O
used	O
by	O
Digital	O
in	O
their	O
AXPpci	O
33	O
motherboard	O
and	O
the	O
AXPvme	O
64	O
and	O
64LC	O
single-board	B-Device
computers	I-Device
.	O
</s>
<s>
The	O
Alpha	B-Device
21068A	O
,	O
introduced	O
as	O
the	O
DECchip	O
21068A	O
,	O
is	O
a	O
variant	O
of	O
the	O
Alpha	B-Device
21066A	O
for	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
Initially	O
,	O
there	O
was	O
no	O
standard	O
chipset	B-Device
for	O
the	O
21064	O
and	O
21064A	O
.	O
</s>
<s>
Digital	O
's	O
computers	O
used	O
custom	O
application-specific	O
integrated	O
circuits	O
(	O
ASICs	O
)	O
to	O
interface	O
the	O
microprocessor	B-Architecture
to	O
the	O
system	O
.	O
</s>
<s>
As	O
this	O
raised	O
development	O
cost	O
for	O
third	O
parties	O
who	O
wished	O
to	O
develop	O
Alpha-based	O
products	O
,	O
Digital	O
developed	O
a	O
standard	O
chipset	B-Device
,	O
the	O
DECchip	O
21070	O
(	O
Apecs	O
)	O
,	O
for	O
original	O
equipment	O
manufacturers	O
(	O
OEMs	O
)	O
.	O
</s>
<s>
The	O
21071	O
was	O
intended	O
for	O
workstations	B-Device
whereas	O
the	O
21072	O
was	O
intended	O
for	O
high-end	O
workstations	B-Device
or	O
low-end	O
uniprocessor	B-Operating_System
servers	O
.	O
</s>
<s>
The	O
two	O
models	O
differed	O
in	O
memory	O
subsystem	O
features	O
:	O
the	O
21071	O
has	O
a	O
64-bit	O
memory	O
bus	O
and	O
supports	O
8MB	O
to	O
2GB	O
of	O
parity-protected	O
memory	O
whereas	O
the	O
21072	O
has	O
a	O
128-bit	O
memory	O
bus	O
and	O
supports	O
16MB	O
to	O
4GB	O
of	O
ECC-protected	O
memory	O
.	O
</s>
<s>
The	O
chipset	B-Device
consisted	O
of	O
three	O
chip	O
designs	O
:	O
the	O
COMANCHE	O
B-cache	O
and	O
memory	B-General_Concept
controller	I-General_Concept
,	O
the	O
DECADE	O
data	O
slice	O
,	O
and	O
the	O
EPIC	O
PCI	O
controller	O
.	O
</s>
<s>
21070	O
users	O
included	O
Carrera	O
Computers	O
for	O
its	O
Pantera	O
workstations	B-Device
and	O
Digital	O
in	O
some	O
models	O
of	O
its	O
AlphaStations	B-Device
and	O
uniprocessor	B-Operating_System
AlphaServers	B-Device
.	O
</s>
