<s>
An	O
aligner	B-Algorithm
,	O
or	O
mask	O
aligner	B-Algorithm
,	O
is	O
a	O
system	O
that	O
produces	O
integrated	O
circuits	O
(	O
IC	O
)	O
using	O
the	O
photolithography	B-Algorithm
process	O
.	O
</s>
<s>
It	O
holds	O
the	O
photomask	B-Algorithm
over	O
the	O
silicon	B-Architecture
wafer	I-Architecture
while	O
a	O
bright	O
light	O
is	O
shone	O
through	O
the	O
mask	O
and	O
onto	O
the	O
photoresist	O
.	O
</s>
<s>
Aligners	B-Algorithm
were	O
a	O
major	O
part	O
of	O
IC	O
manufacture	O
from	O
the	O
1960s	O
into	O
the	O
late	O
1970s	O
,	O
when	O
they	O
began	O
to	O
be	O
replaced	O
by	O
the	O
stepper	B-Algorithm
.	O
</s>
<s>
There	O
are	O
several	O
distinct	O
generations	O
of	O
aligner	B-Algorithm
technology	O
.	O
</s>
<s>
The	O
early	O
contact	O
aligners	B-Algorithm
placed	O
the	O
mask	O
in	O
direct	O
contact	O
with	O
the	O
top	O
surface	O
of	O
the	O
wafer	B-Architecture
,	O
which	O
often	O
damaged	O
the	O
pattern	O
when	O
the	O
mask	O
was	O
lifted	O
off	O
again	O
.	O
</s>
<s>
Used	O
only	O
briefly	O
,	O
proximity	O
aligners	B-Algorithm
held	O
the	O
mask	O
slightly	O
above	O
the	O
surface	O
to	O
avoid	O
this	O
problem	O
,	O
but	O
were	O
difficult	O
to	O
work	O
with	O
and	O
required	O
considerable	O
manual	O
adjustment	O
.	O
</s>
<s>
Finally	O
,	O
the	O
Micralign	B-Algorithm
projection	O
aligner	B-Algorithm
,	O
introduced	O
by	O
Perkin-Elmer	O
in	O
1973	O
,	O
held	O
the	O
mask	O
entirely	O
separate	O
from	O
the	O
chip	O
and	O
made	O
the	O
adjustment	O
of	O
the	O
image	O
much	O
simpler	O
.	O
</s>
<s>
The	O
stepper	B-Algorithm
is	O
similar	O
to	O
an	O
aligner	B-Algorithm
in	O
concept	O
,	O
but	O
with	O
one	O
key	O
difference	O
.	O
</s>
<s>
The	O
aligner	B-Algorithm
uses	O
a	O
mask	O
that	O
holds	O
the	O
pattern	O
for	O
the	O
entire	O
wafer	B-Architecture
,	O
which	O
may	O
require	O
large	O
masks	O
.	O
</s>
<s>
The	O
stepper	B-Algorithm
uses	O
a	O
mask	O
on	O
the	O
wafer	B-Architecture
repeatedly	O
,	O
and	O
steps	O
across	O
the	O
surface	O
to	O
repeat	O
the	O
pattern	O
of	O
the	O
chip	O
layer	O
.	O
</s>
<s>
This	O
reduces	O
mask	O
costs	O
dramatically	O
and	O
allows	O
a	O
single	O
wafer	B-Architecture
to	O
be	O
used	O
for	O
different	O
mask	O
designs	O
in	O
a	O
single	O
run	O
.	O
</s>
<s>
More	O
importantly	O
,	O
by	O
focussing	O
the	O
light	O
source	O
onto	O
a	O
single	O
area	O
of	O
the	O
wafer	B-Architecture
,	O
the	O
stepper	B-Algorithm
can	O
produce	O
much	O
higher	O
resolutions	O
,	O
thus	O
allowing	O
for	O
smaller	O
features	O
on	O
chips	O
(	O
minimum	O
feature	O
size	O
)	O
.	O
</s>
<s>
The	O
disadvantage	O
to	O
the	O
stepper	B-Algorithm
is	O
that	O
each	O
chip	O
on	O
the	O
wafer	B-Architecture
has	O
to	O
be	O
individually	O
imaged	O
,	O
and	O
thus	O
the	O
process	O
of	O
exposing	O
the	O
wafer	B-Architecture
as	O
a	O
whole	O
is	O
much	O
slower	O
.	O
</s>
