<s>
Alchemy	B-Device
is	O
a	O
family	O
of	O
ultra	O
low	O
power	O
embedded	O
microprocessors	O
originally	O
designed	O
by	O
Alchemy	B-Device
Semiconductor	O
for	O
communication	O
and	O
media	O
devices	O
.	O
</s>
<s>
Alchemy	B-Device
processors	O
are	O
SoCs	O
integrating	O
a	O
CPU	O
core	O
,	O
a	O
memory	O
controller	O
,	O
and	O
a	O
varying	O
set	O
of	O
peripherals	O
.	O
</s>
<s>
All	O
members	O
of	O
the	O
family	O
use	O
the	O
Au1	O
CPU	O
core	O
implementing	O
the	O
MIPS32	O
instruction	B-General_Concept
set	I-General_Concept
by	O
MIPS	O
Technologies	O
.	O
</s>
<s>
Alchemy	B-Device
Semiconductor	O
was	O
a	O
fabless	B-Algorithm
semiconductor	I-Algorithm
company	I-Algorithm
based	O
in	O
Austin	O
,	O
Texas	O
.	O
</s>
<s>
The	O
founding	O
team	O
included	O
former	O
members	O
of	O
DEC	O
's	O
Austin	O
Research	O
and	O
Design	O
Center	O
working	O
on	O
the	O
StrongARM	B-Device
project	O
,	O
dissolved	O
after	O
DEC	O
sold	O
its	O
microprocessors	O
business	O
to	O
Intel	O
.	O
</s>
<s>
In	O
May	O
2000	O
Alchemy	B-Device
Semiconductor	O
became	O
an	O
independent	O
company	O
.	O
</s>
<s>
Alchemy	B-Device
Semiconductor	O
unveiled	O
the	O
first	O
member	O
of	O
the	O
family	O
,	O
the	O
Au1000	O
processor	O
,	O
at	O
the	O
Embedded	O
Processor	O
Forum	O
in	O
San	O
Jose	O
,	O
CA	O
,	O
on	O
June	O
13	O
,	O
2000	O
,	O
with	O
limited	O
customer	O
sampling	O
in	O
February	O
2001	O
and	O
availability	O
in	O
production	O
quantities	O
in	O
Q2	O
of	O
that	O
year	O
,	O
followed	O
in	O
2001	O
and	O
2002	O
by	O
the	O
Au1500	O
and	O
Au1100	O
.	O
</s>
<s>
In	O
February	O
2002	O
AMD	O
acquired	O
Alchemy	B-Device
in	O
order	O
to	O
compete	O
with	O
Intel	O
's	O
ARM-based	O
XScale	B-Application
processors	O
,	O
successor	O
to	O
the	O
StrongARM	B-Device
line	O
.	O
</s>
<s>
In	O
Summer	O
2006	O
AMD	O
sold	O
its	O
Alchemy	B-Device
assets	O
to	O
Raza	O
Microelectronics	O
,	O
later	O
renamed	O
RMI	O
Corporation	O
.	O
</s>
<s>
Broadcom	O
continued	O
to	O
sell	O
Alchemy	B-Device
processors	O
,	O
if	O
only	O
under	O
long	O
term	O
availability	O
obligations	O
,	O
until	O
at	O
least	O
2017	O
.	O
</s>
<s>
The	O
Au1	O
CPU	O
core	O
designed	O
by	O
Alchemy	B-Device
implements	O
the	O
MIPS32	O
ISA	O
Release	O
1	O
and	O
supports	O
the	O
MIPS	O
EJTAG	O
interface	O
.	O
</s>
<s>
A	O
floating-point	B-Algorithm
unit	O
is	O
not	O
present	O
,	O
FP	O
instructions	O
generate	O
an	O
exception	O
and	O
can	O
be	O
emulated	O
by	O
software	O
.	O
</s>
<s>
Virtual	O
address	O
translation	O
is	O
TLB-based	O
and	O
relies	O
on	O
a	O
fast	O
exception	O
handler	O
rather	O
than	O
a	O
hardware	O
table	O
walker	O
.	O
</s>
<s>
Au1	O
is	O
a	O
scalar	O
,	O
in-order	O
microarchitecture	O
with	O
a	O
classic	B-General_Concept
five	I-General_Concept
stage	I-General_Concept
RISC	I-General_Concept
pipeline	I-General_Concept
enhanced	O
by	O
several	O
optimizations	O
.	O
</s>
<s>
The	O
Au1000	O
SoC	B-Architecture
is	O
rated	O
for	O
core	O
frequencies	O
up	O
to	O
500MHz	O
.	O
</s>
<s>
At	O
400MHz	O
it	O
operates	O
at	O
1.5V	O
and	O
the	O
chip	O
consumes	O
no	O
more	O
than	O
500mW	O
,	O
with	O
a	O
performance	O
of	O
over	O
900	O
Dhrystone-2.1	O
MIPS/Watt	O
according	O
to	O
Alchemy	B-Device
Semiconductor	O
.	O
</s>
<s>
All	O
Alchemy	B-Device
processors	O
integrate	O
a	O
DRAM	O
controller	O
,	O
a	O
static	O
bus	O
controller	O
,	O
an	O
8-channel	O
DMA	O
controller	O
for	O
data	O
transfers	O
between	O
memory	O
and	O
peripherals	O
,	O
interrupt	O
controllers	O
,	O
timers	O
,	O
and	O
a	O
power	O
management	O
unit	O
.	O
</s>
<s>
The	O
static	O
bus	O
controller	O
supports	O
SRAM	B-Architecture
,	O
ROM	B-Device
,	O
NAND/NOR	B-Device
Flash	I-Device
(	O
Au1550	O
)	O
,	O
page	O
mode	O
Flash/ROM	O
,	O
PCMCIA/CompactFlash	O
devices	O
,	O
and	O
I/O	O
peripherals	O
such	O
as	O
an	O
external	O
LCD	B-Device
controller	O
,	O
IDE	O
PIO	O
mode	O
up	O
to	O
≈	O
80Mbit/s	O
(	O
Au12xx	O
)	O
,	O
or	O
ATA-6/UDMA	O
mode	O
5	O
(	O
Au13xx	O
)	O
.	O
</s>
<s>
The	O
Au1550	O
integrates	O
a	O
SafeNet	O
Security	O
Engine	O
providing	O
an	O
entropy-based	O
random	O
number	O
generator	O
and	O
accelerating	O
the	O
DES	B-Algorithm
,	O
3DES	B-Algorithm
,	O
AES	B-Algorithm
,	O
and	O
RC4	B-Algorithm
encryption	O
algorithms	O
,	O
and	O
the	O
MD5	B-Algorithm
and	O
SHA-1	B-Algorithm
hash	I-Algorithm
algorithms	O
.	O
</s>
<s>
Au1100	O
processors	O
integrate	O
an	O
LCD	B-Device
controller	O
which	O
supports	O
panels	O
up	O
to	O
800	O
×	O
600	O
pixels	O
with	O
16	O
bit	O
color	O
depth	O
.	O
</s>
<s>
The	O
LCD	B-Device
controller	O
of	O
Au12xx	O
processors	O
supports	O
up	O
to	O
2K	O
resolution	O
and	O
up	O
to	O
24	O
bits	O
per	O
pixel	O
,	O
four	O
overlay	O
windows	O
,	O
alpha	O
blending	O
,	O
and	O
gamma	O
correction	O
.	O
</s>
<s>
The	O
Camera	O
Interface	O
Module	O
pins	O
out	O
an	O
ITU-R	B-Device
BT.656	I-Device
compatible	O
8/9/10	O
-bit	O
bus	O
running	O
at	O
up	O
to	O
33MHz	O
,	O
and	O
supports	O
UYVY	O
(	O
YUV	O
4:2:2	O
)	O
and	O
Bayer	B-Algorithm
RGB	I-Algorithm
to	O
planar	O
format	O
conversion	O
.	O
</s>
<s>
The	O
Media	O
Acceleration	O
Engine	O
accelerates	O
video	O
decoding	O
and	O
supports	O
the	O
formats	O
MPEG-1/2/4	O
,	O
DivX-3/4/5	B-Application
,	O
H.263	B-Algorithm
,	O
and	O
WMV	B-Device
9/VC	I-Device
-1	I-Device
at	O
resolutions	O
up	O
to	O
720	O
×	O
576	O
.	O
</s>
<s>
The	O
MAE2	O
peripheral	O
of	O
Au13xx	O
processors	O
adds	O
support	O
for	O
the	O
H.264	B-Application
and	O
JPEG	O
standards	O
,	O
hardware	O
bit	O
stream	O
decoding	O
,	O
and	O
resolutions	O
up	O
to	O
720p	O
.	O
</s>
<s>
The	O
Graphics	O
Processing	O
Engine	O
available	O
on	O
some	O
Au13xx	O
processors	O
is	O
an	O
ARM	B-General_Concept
Mali-200	I-General_Concept
and	O
accelerates	O
2D	O
and	O
3D	O
graphics	O
compatible	O
with	O
OpenVG	B-Library
1.1	O
and	O
OpenGL	B-Application
ES	I-Application
1.1	O
and	O
2.0	O
.	O
</s>
<s>
(	O
MHz	O
)	O
TDP	B-General_Concept
(	O
mW	O
)	O
DRAM	O
Static	O
Bus	O
Integrated	O
Peripherals	O
Datasheet	O
Notes	O
PCI	B-Protocol
LCD	B-Device
Hardware	O
de/encrypt	O
.	O
</s>
<s>
USB	B-Protocol
host	O
ports	O
USB	B-Protocol
device	O
port	O
Ethernet	O
SD	B-Device
card	I-Device
Low	O
speed	O
busses	O
GPIOs	B-Architecture
max	O
.	O
</s>
<s>
by	O
Alchemy	B-Device
Semiconductor	O
(	O
2000	O
–	O
2002	O
)	O
Au1000	O
2000-06-13	O
(	O
announced	O
)	O
2001-Q2	O
(	O
available	O
)	O
266-500	O
300-900	O
typ	O
.	O
</s>
<s>
32-bit	O
SDR-133	O
32-bit	O
data/address	O
-	O
-	O
-	O
-	O
-	O
-	O
2	O
×	O
1.1	O
1.1	O
2	O
×	O
10/100	O
-	O
AC'97	O
,	O
I²S	O
,	O
IrDA	O
,	O
2	O
×	O
SSI	B-Protocol
,	O
4	O
×	O
UART	O
32	O
Au1500	O
2001-06-11	O
(	O
announced	O
)	O
2001-12	O
(	O
available	O
)	O
333-500	O
400-1200	O
typ	O
.	O
</s>
<s>
32-bit	O
SDR-133	O
2.5V/3.3V	O
-	O
v1	O
-	O
-	O
-	O
-	O
2	O
×	O
1.1	O
1.1	O
1	O
×	O
10/100	O
2	O
×	O
1.1	O
AC'97	O
,	O
I²S	O
,	O
IrDA	O
,	O
2	O
×	O
SSI	B-Protocol
,	O
3	O
×	O
UART	O
48	O
by	O
AMD	O
(	O
2002	O
–	O
2006	O
)	O
Au1550	O
2004-02-24	O
(	O
announced	O
)	O
333-500	O
400-600	O
typ.	O
,	O
1460	O
max	O
.	O
</s>
<s>
-	O
v2	O
-	O
v1	O
v1	O
AES-128	B-Algorithm
1	O
×	O
2.0	O
2.0	O
OTG	O
-	O
2	O
×	O
1.1	O
4	O
×	O
PSC	O
,	O
2	O
×	O
UART	O
48	O
by	O
RMI	O
(	O
2006	O
–	O
2009	O
)	O
,	O
NetLogic	O
(	O
2009	O
–	O
2011	O
)	O
,	O
Broadcom	O
(	O
2011	O
–	O
current	O
)	O
Au1210	O
2007-01-09	O
(	O
announced	O
)	O
2007-06	O
(	O
available	O
)	O
333-400	O
360-420	O
typ.	O
,	O
1000	O
max	O
.	O
</s>
<s>
AES-128	B-Algorithm
1	O
×	O
2.0	O
2.0	O
OTG	O
-	O
2	O
×	O
1.1	O
Au1310	O
2009-01	O
(	O
announced	O
)	O
533	O
2	O
×	O
16-bit	O
DDR2-667	O
16-bit	O
data	O
,	O
15/30	O
-bit	O
addr	O
.	O
</s>
<s>
Programmable	O
Serial	O
Controller	O
configurable	O
as	O
AC'97	O
,	O
I²S	O
,	O
SPI	B-Architecture
,	O
SMBus	B-Algorithm
interface	O
.	O
</s>
<s>
Alchemy	B-Device
processors	O
were	O
marketed	O
for	O
wireless	O
gateways	B-Application
and	O
access	B-Device
points	I-Device
;	O
VoIP	B-Application
,	O
navigation	O
,	O
and	O
NAS	B-Application
devices	O
;	O
STBs	O
,	O
thin	B-Device
clients	I-Device
,	O
portable	O
and	O
automotive	O
TV	O
and	O
media	O
players	O
,	O
and	O
digital	B-Algorithm
photo	I-Algorithm
frames	I-Algorithm
.	O
</s>
