<s>
The	O
Advanced	B-Protocol
eXtensible	I-Protocol
Interface	I-Protocol
(	O
AXI	O
)	O
is	O
an	O
on-chip	O
communication	O
bus	B-General_Concept
protocol	O
developed	O
by	O
ARM	O
.	O
</s>
<s>
It	O
is	O
part	O
of	O
the	O
Advanced	B-Architecture
Microcontroller	I-Architecture
Bus	I-Architecture
Architecture	I-Architecture
3	O
(	O
AXI3	O
)	O
and	O
4	O
(	O
AXI4	O
)	O
specifications	O
.	O
</s>
<s>
In	O
2010	O
,	O
a	O
new	O
revision	O
of	O
AMBA	B-Architecture
,	O
AMBA4	O
,	O
defined	O
the	O
AXI4	O
,	O
AXI4-Lite	O
and	O
AXI4-Stream	O
protocol	O
.	O
</s>
<s>
AMBA	B-Architecture
AXI	O
specifies	O
many	O
optional	O
signals	O
,	O
which	O
can	O
be	O
included	O
depending	O
on	O
the	O
specific	O
requirements	O
of	O
the	O
design	O
,	O
making	O
AXI	O
a	O
versatile	O
bus	B-General_Concept
for	O
numerous	O
applications	O
.	O
</s>
<s>
While	O
the	O
communication	O
over	O
an	O
AXI	O
bus	B-General_Concept
is	O
between	O
a	O
single	O
initiator	O
and	O
a	O
single	O
target	O
,	O
the	O
specification	O
includes	O
detailed	O
description	O
and	O
signals	O
to	O
include	O
N:M	O
interconnects	B-General_Concept
,	O
able	O
to	O
extend	O
the	O
bus	B-General_Concept
to	O
topologies	O
with	O
more	O
initiators	O
and	O
targets	O
.	O
</s>
<s>
AMBA	B-Architecture
AXI4	O
,	O
AXI4-Lite	O
and	O
AXI4-Stream	O
have	O
been	O
adopted	O
by	O
Xilinx	O
and	O
many	O
of	O
its	O
partners	O
as	O
main	O
communication	O
buses	O
in	O
their	O
products	O
.	O
</s>
<s>
Axi-lite	O
bus	B-General_Concept
is	O
an	O
AXI	O
bus	B-General_Concept
that	O
only	O
supports	O
a	O
single	O
ID	O
thread	O
per	O
initiator	O
.	O
</s>
<s>
This	O
bus	B-General_Concept
is	O
typically	O
used	O
for	O
an	O
end	O
point	O
that	O
only	O
needs	O
to	O
communicate	O
with	O
a	O
single	O
initiator	O
device	O
at	O
a	O
time	O
,	O
example	O
,	O
a	O
simple	O
peripheral	O
such	O
as	O
a	O
UART	O
.	O
</s>
<s>
This	O
is	O
why	O
a	O
CPU	O
will	O
typically	O
support	O
a	O
full	O
spec	O
AXI	O
bus	B-General_Concept
.	O
</s>
<s>
(	O
Additionally	O
,	O
the	O
AXI-lite	O
bus	B-General_Concept
is	O
restricted	O
to	O
only	O
support	O
transaction	O
lengths	O
of	O
a	O
single	O
data	O
word	O
per	O
transaction	O
.	O
)	O
</s>
<s>
AXI	O
defines	O
a	O
basic	O
handshake	B-Protocol
mechanism	I-Protocol
,	O
composed	O
by	O
an	O
xVALID	O
and	O
xREADY	O
signal	O
.	O
</s>
<s>
Once	O
asserted	O
,	O
a	O
source	O
must	O
keep	O
a	O
high	O
xVALID	O
until	O
a	O
handshake	B-Protocol
occurs	O
.	O
</s>
<s>
Thanks	O
to	O
this	O
handshake	B-Protocol
mechanism	I-Protocol
,	O
both	O
the	O
source	O
and	O
the	O
destination	O
can	O
control	O
the	O
flow	O
of	O
data	O
,	O
throttling	O
the	O
speed	O
if	O
needed	O
.	O
</s>
<s>
Other	O
than	O
some	O
basic	O
ordering	O
rules	O
,	O
each	O
channel	O
is	O
independent	O
from	O
each	O
other	O
and	O
has	O
its	O
own	O
couple	O
of	O
xVALID/xREADY	O
handshake	B-Protocol
signals	O
.	O
</s>
<s>
AXI	O
is	O
a	O
burst-based	B-Architecture
protocol	O
,	O
meaning	O
that	O
there	O
may	O
be	O
multiple	O
data	O
transfers	O
(	O
or	O
beats	O
)	O
for	O
a	O
single	O
request	O
.	O
</s>
<s>
This	O
is	O
useful	O
for	O
repeated	O
access	O
at	O
the	O
same	O
memory	O
location	O
,	O
such	O
as	O
when	O
reading	O
or	O
writing	O
a	O
FIFO	B-Operating_System
.	O
</s>
<s>
After	O
the	O
usual	O
ARVALID/ARREADY	O
handshake	B-Protocol
,	O
the	O
target	O
has	O
to	O
provide	O
on	O
the	O
Read	O
data	O
channel	O
:	O
</s>
<s>
Each	O
beat	O
of	O
the	O
target	O
's	O
response	O
is	O
done	O
with	O
a	O
RVALID/RREADY	O
handshake	B-Protocol
and	O
,	O
on	O
the	O
last	O
transfer	O
,	O
the	O
target	O
has	O
to	O
assert	O
RLAST	O
to	O
inform	O
that	O
no	O
more	O
beats	O
will	O
follow	O
without	O
a	O
new	O
read	O
request	O
.	O
</s>
<s>
AXI4-Lite	O
is	O
a	O
subset	O
of	O
the	O
AXI4	O
protocol	O
,	O
providing	O
a	O
register-like	B-General_Concept
structure	O
with	O
reduced	O
features	O
and	O
complexity	O
.	O
</s>
