<s>
Advanced	B-General_Concept
Vector	I-General_Concept
Extensions	I-General_Concept
(	O
AVX	O
)	O
are	O
extensions	O
to	O
the	O
x86	B-Operating_System
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
for	O
microprocessors	B-Architecture
from	O
Intel	O
and	O
Advanced	O
Micro	O
Devices	O
(	O
AMD	O
)	O
.	O
</s>
<s>
They	O
were	O
proposed	O
by	O
Intel	O
in	O
March	O
2008	O
and	O
first	O
supported	O
by	O
Intel	O
with	O
the	O
Sandy	B-Device
Bridge	I-Device
processor	O
shipping	O
in	O
Q1	O
2011	O
and	O
later	O
by	O
AMD	O
with	O
the	O
Bulldozer	O
processor	O
shipping	O
in	O
Q3	O
2011	O
.	O
</s>
<s>
AVX2	O
(	O
also	O
known	O
as	O
Haswell	B-Device
New	O
Instructions	O
)	O
expands	O
most	O
integer	O
commands	O
to	O
256	O
bits	O
and	O
introduces	O
new	O
instructions	O
.	O
</s>
<s>
They	O
were	O
first	O
supported	O
by	O
Intel	O
with	O
the	O
Haswell	B-Device
processor	O
,	O
which	O
shipped	O
in	O
2013	O
.	O
</s>
<s>
AVX-512	B-General_Concept
expands	O
AVX	O
to	O
512-bit	O
support	O
using	O
a	O
new	O
EVEX	B-General_Concept
prefix	I-General_Concept
encoding	O
proposed	O
by	O
Intel	O
in	O
July	O
2013	O
and	O
first	O
supported	O
by	O
Intel	O
with	O
the	O
Knights	O
Landing	O
co-processor	O
,	O
which	O
shipped	O
in	O
2016	O
.	O
</s>
<s>
In	O
conventional	O
processors	O
,	O
AVX-512	B-General_Concept
was	O
introduced	O
with	O
Skylake	B-Architecture
server	O
and	O
HEDT	O
processors	O
in	O
2017	O
.	O
</s>
<s>
AVX	O
uses	O
sixteen	O
YMM	O
registers	O
to	O
perform	O
a	O
single	O
instruction	O
on	O
multiple	O
pieces	O
of	O
data	O
(	O
see	O
SIMD	B-Device
)	O
.	O
</s>
<s>
four	O
64-bit	O
double-precision	O
floating	B-Algorithm
point	I-Algorithm
numbers	I-Algorithm
.	O
</s>
<s>
The	O
width	O
of	O
the	O
SIMD	B-Device
registers	O
is	O
increased	O
from	O
128	O
bits	O
to	O
256	O
bits	O
,	O
and	O
renamed	O
from	O
XMM0	O
–	O
XMM7	O
to	O
YMM0	O
–	O
YMM7	O
(	O
in	O
x86-64	B-Device
mode	O
,	O
from	O
XMM0	O
–	O
XMM15	O
to	O
YMM0	O
–	O
YMM15	O
)	O
.	O
</s>
<s>
The	O
legacy	O
SSE	B-General_Concept
instructions	I-General_Concept
can	O
be	O
still	O
utilized	O
via	O
the	O
VEX	B-General_Concept
prefix	I-General_Concept
to	O
operate	O
on	O
the	O
lower	O
128	O
bits	O
of	O
the	O
YMM	O
registers	O
.	O
</s>
<s>
AVX	O
introduces	O
a	O
three-operand	O
SIMD	B-Device
instruction	O
format	O
called	O
VEX	B-General_Concept
coding	I-General_Concept
scheme	I-General_Concept
,	O
where	O
the	O
destination	O
register	O
is	O
distinct	O
from	O
the	O
two	O
source	O
operands	O
.	O
</s>
<s>
For	O
example	O
,	O
an	O
SSE	B-General_Concept
instruction	O
using	O
the	O
conventional	O
two-operand	O
form	O
can	O
now	O
use	O
a	O
non-destructive	O
three-operand	O
form	O
,	O
preserving	O
both	O
source	O
operands	O
.	O
</s>
<s>
Originally	O
,	O
AVX	O
's	O
three-operand	O
format	O
was	O
limited	O
to	O
the	O
instructions	O
with	O
SIMD	B-Device
operands	O
(	O
YMM	O
)	O
,	O
and	O
did	O
not	O
include	O
instructions	O
with	O
general	O
purpose	O
registers	O
(	O
e.g.	O
</s>
<s>
It	O
was	O
later	O
used	O
for	O
coding	O
new	O
instructions	O
on	O
general	O
purpose	O
registers	O
in	O
later	O
extensions	O
,	O
such	O
as	O
BMI	B-Device
.	O
</s>
<s>
VEX	B-General_Concept
coding	O
is	O
also	O
used	O
for	O
instructions	O
operating	O
on	O
the	O
k0-k7	O
mask	O
registers	O
that	O
were	O
introduced	O
with	O
AVX-512	B-General_Concept
.	O
</s>
<s>
The	O
alignment	B-Application
requirement	O
of	O
SIMD	B-Device
memory	O
operands	O
is	O
relaxed	O
.	O
</s>
<s>
Unlike	O
their	O
non-VEX	O
coded	O
counterparts	O
,	O
most	O
VEX	B-General_Concept
coded	O
vector	O
instructions	O
no	O
longer	O
require	O
their	O
memory	O
operands	O
to	O
be	O
aligned	O
to	O
the	O
vector	O
size	O
.	O
</s>
<s>
The	O
new	O
VEX	B-General_Concept
coding	I-General_Concept
scheme	I-General_Concept
introduces	O
a	O
new	O
set	O
of	O
code	O
prefixes	O
that	O
extends	O
the	O
opcode	B-Language
space	O
,	O
allows	O
instructions	O
to	O
have	O
more	O
than	O
two	O
operands	O
,	O
and	O
allows	O
SIMD	B-Device
vector	O
registers	O
to	O
be	O
longer	O
than	O
128	O
bits	O
.	O
</s>
<s>
The	O
VEX	B-General_Concept
prefix	I-General_Concept
can	O
also	O
be	O
used	O
on	O
the	O
legacy	O
SSE	B-General_Concept
instructions	I-General_Concept
giving	O
them	O
a	O
three-operand	O
form	O
,	O
and	O
making	O
them	O
interact	O
more	O
efficiently	O
with	O
AVX	O
instructions	O
without	O
the	O
need	O
for	O
VZEROUPPER	O
and	O
VZEROALL	O
.	O
</s>
<s>
The	O
AVX	O
instructions	O
support	O
both	O
128-bit	O
and	O
256-bit	O
SIMD	B-Device
.	O
</s>
<s>
The	O
128-bit	O
versions	O
can	O
be	O
useful	O
to	O
improve	O
old	O
code	O
without	O
needing	O
to	O
widen	O
the	O
vectorization	O
,	O
and	O
avoid	O
the	O
penalty	O
of	O
going	O
from	O
SSE	B-General_Concept
to	O
AVX	O
,	O
they	O
are	O
also	O
faster	O
on	O
some	O
early	O
AMD	O
implementations	O
of	O
AVX	O
.	O
</s>
<s>
These	O
AVX	O
instructions	O
are	O
in	O
addition	O
to	O
the	O
ones	O
that	O
are	O
256-bit	O
extensions	O
of	O
the	O
legacy	O
128-bit	O
SSE	B-General_Concept
instructions	I-General_Concept
;	O
most	O
are	O
usable	O
on	O
both	O
128-bit	O
and	O
256-bit	O
operands	O
.	O
</s>
<s>
VMASKMOVPS	O
,	O
VMASKMOVPD	O
Conditionally	O
reads	O
any	O
number	O
of	O
elements	O
from	O
a	O
SIMD	B-Device
vector	O
memory	O
operand	O
into	O
a	O
destination	O
register	O
,	O
leaving	O
the	O
remaining	O
vector	O
elements	O
unread	O
and	O
setting	O
the	O
corresponding	O
elements	O
in	O
the	O
destination	O
register	O
to	O
zero	O
.	O
</s>
<s>
Alternatively	O
,	O
conditionally	O
writes	O
any	O
number	O
of	O
elements	O
from	O
a	O
SIMD	B-Device
vector	O
register	O
operand	O
to	O
a	O
vector	O
memory	O
operand	O
,	O
leaving	O
the	O
remaining	O
elements	O
of	O
the	O
memory	O
operand	O
unchanged	O
.	O
</s>
<s>
VTESTPS	O
,	O
VTESTPD	O
Packed	O
bit	O
test	O
of	O
the	O
packed	O
single-precision	O
or	O
double-precision	O
floating-point	B-Algorithm
sign	O
bits	O
,	O
setting	O
or	O
clearing	O
the	O
ZF	O
flag	O
based	O
on	O
AND	O
and	O
CF	O
flag	O
based	O
on	O
ANDN	O
.	O
</s>
<s>
Alder	B-Device
Lake	I-Device
(	O
Xeon	O
,	O
Core	O
,	O
Pentium	O
and	O
Celeron	O
branded	O
)	O
processors	O
,	O
Q4	O
2021	O
.	O
</s>
<s>
Supported	O
both	O
in	O
Golden	B-Device
Cove	I-Device
P-cores	O
and	O
Gracemont	B-Device
E-cores	O
.	O
</s>
<s>
Generally	O
,	O
CPUs	O
with	O
the	O
commercial	O
denomination	O
Core	O
i3/i5/i7/i9	O
support	O
them	O
,	O
whereas	O
Pentium	O
and	O
Celeron	O
CPUs	O
before	O
Tiger	B-Device
Lake	I-Device
do	O
not	O
.	O
</s>
<s>
Issues	O
regarding	O
compatibility	O
between	O
future	O
Intel	O
and	O
AMD	O
processors	O
are	O
discussed	O
under	O
XOP	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Zhaoxin	B-Device
:	O
</s>
<s>
Absoft	B-Application
supports	O
with	O
-	O
flag	O
.	O
</s>
<s>
The	O
Free	B-Operating_System
Pascal	I-Operating_System
compiler	I-Operating_System
supports	O
AVX	O
and	O
AVX2	O
with	O
the	O
-CfAVX	O
and	O
-CfAVX2	O
switches	O
from	O
version	O
2.7.1	O
.	O
</s>
<s>
RAD	B-Language
studio	I-Language
(	O
v11.0	O
Alexandria	O
)	O
supports	O
AVX2	O
and	O
AVX512	B-General_Concept
.	O
</s>
<s>
The	O
GNU	B-Application
Assembler	I-Application
(	O
GAS	O
)	O
inline	O
assembly	O
functions	O
support	O
these	O
instructions	O
(	O
accessible	O
via	O
GCC	B-Application
)	O
,	O
as	O
do	O
Intel	O
primitives	O
and	O
the	O
Intel	O
inline	O
assembler	O
(	O
closely	O
compatible	O
to	O
GAS	O
,	O
although	O
more	O
general	O
in	O
its	O
handling	O
of	O
local	O
references	O
within	O
inline	O
code	O
)	O
.	O
</s>
<s>
GCC	B-Application
starting	O
with	O
version	O
4.6	O
(	O
although	O
there	O
was	O
a	O
4.3	O
branch	O
with	O
certain	O
support	O
)	O
and	O
the	O
Intel	O
Compiler	O
Suite	O
starting	O
with	O
version	O
11.1	O
support	O
AVX	O
.	O
</s>
<s>
The	O
Open64	B-Application
compiler	O
version	O
4.5.1	O
supports	O
AVX	O
with	O
-	O
flag	O
.	O
</s>
<s>
PathScale	B-Language
supports	O
via	O
the	O
-	O
flag	O
.	O
</s>
<s>
The	O
Vector	B-Language
Pascal	I-Language
compiler	O
supports	O
AVX	O
via	O
the	O
-	O
flag	O
.	O
</s>
<s>
Other	O
assemblers	O
such	O
as	O
MASM	B-Application
VS2010	O
version	O
,	O
YASM	O
,	O
FASM	B-Application
,	O
NASM	B-Application
and	O
JWASM	B-Application
.	O
</s>
<s>
AVX	O
adds	O
new	O
register-state	O
through	O
the	O
256-bit	O
wide	O
YMM	O
register	O
file	O
,	O
so	O
explicit	O
operating	B-General_Concept
system	I-General_Concept
support	O
is	O
required	O
to	O
properly	O
save	O
and	O
restore	O
AVX	O
's	O
expanded	O
registers	O
between	O
context	B-Operating_System
switches	I-Operating_System
.	O
</s>
<s>
The	O
following	O
operating	B-General_Concept
system	I-General_Concept
versions	O
support	O
AVX	O
:	O
</s>
<s>
DragonFly	B-Application
BSD	I-Application
:	O
support	O
added	O
in	O
early	O
2013	O
.	O
</s>
<s>
Linux	B-Operating_System
:	O
supported	O
since	O
kernel	B-Operating_System
version	O
2.6.30	O
,	O
released	O
on	O
June	O
9	O
,	O
2009	O
.	O
</s>
<s>
macOS	B-Application
:	O
support	O
added	O
in	O
10.6.8	O
(	O
Snow	B-Device
Leopard	I-Device
)	O
update	O
released	O
on	O
June	O
23	O
,	O
2011	O
.	O
</s>
<s>
In	O
fact	O
,	O
macOS	B-Application
Ventura	O
does	O
not	O
support	O
processors	O
without	O
the	O
AVX2	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
OpenBSD	B-Operating_System
:	O
support	O
added	O
on	O
March	O
21	O
,	O
2015	O
.	O
</s>
<s>
Windows	B-Device
Server	I-Device
2008	I-Device
R2	I-Device
SP1	O
with	O
Hyper-V	O
requires	O
a	O
hotfix	O
to	O
support	O
AMD	O
AVX	O
(	O
Opteron	O
6200	O
and	O
4200	O
series	O
)	O
processors	O
,	O
</s>
<s>
Advanced	B-General_Concept
Vector	I-General_Concept
Extensions	I-General_Concept
2	O
(	O
AVX2	O
)	O
,	O
also	O
known	O
as	O
Haswell	B-Device
New	O
Instructions	O
,	O
is	O
an	O
expansion	O
of	O
the	O
AVX	O
instruction	B-General_Concept
set	I-General_Concept
introduced	O
in	O
Intel	O
's	O
Haswell	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
Sometimes	O
three-operand	O
fused	B-General_Concept
multiply-accumulate	I-General_Concept
(	O
FMA3	B-General_Concept
)	O
extension	O
is	O
considered	O
part	O
of	O
AVX2	O
,	O
as	O
it	O
was	O
introduced	O
by	O
Intel	O
in	O
the	O
same	O
processor	O
microarchitecture	O
.	O
</s>
<s>
This	O
is	O
a	O
separate	O
extension	O
using	O
its	O
own	O
CPUID	B-Architecture
flag	O
and	O
is	O
described	O
on	O
its	O
own	O
page	O
and	O
not	O
below	O
.	O
</s>
<s>
VGATHERDPD	O
,	O
VGATHERQPD	O
,	O
VGATHERDPS	O
,	O
VGATHERQPS	O
Gathers	B-General_Concept
single	O
or	O
double	O
precision	O
floating	B-Algorithm
point	I-Algorithm
values	I-Algorithm
using	O
either	O
32	O
or	O
64-bit	O
indices	O
and	O
scale	O
.	O
</s>
<s>
VPGATHERDD	O
,	O
VPGATHERDQ	O
,	O
VPGATHERQD	O
,	O
VPGATHERQQ	O
Gathers	B-General_Concept
32	O
or	O
64-bit	O
integer	O
values	O
using	O
either	O
32	O
or	O
64-bit	O
indices	O
and	O
scale	O
.	O
</s>
<s>
VPMASKMOVD	O
,	O
VPMASKMOVQ	O
Conditionally	O
reads	O
any	O
number	O
of	O
elements	O
from	O
a	O
SIMD	B-Device
vector	O
memory	O
operand	O
into	O
a	O
destination	O
register	O
,	O
leaving	O
the	O
remaining	O
vector	O
elements	O
unread	O
and	O
setting	O
the	O
corresponding	O
elements	O
in	O
the	O
destination	O
register	O
to	O
zero	O
.	O
</s>
<s>
Alternatively	O
,	O
conditionally	O
writes	O
any	O
number	O
of	O
elements	O
from	O
a	O
SIMD	B-Device
vector	O
register	O
operand	O
to	O
a	O
vector	O
memory	O
operand	O
,	O
leaving	O
the	O
remaining	O
elements	O
of	O
the	O
memory	O
operand	O
unchanged	O
.	O
</s>
<s>
VPBLENDD	O
Doubleword	O
immediate	O
version	O
of	O
the	O
PBLEND	O
instructions	O
from	O
SSE4	B-General_Concept
.	O
</s>
<s>
Alder	B-Device
Lake	I-Device
(	O
Xeon	O
,	O
Core	O
,	O
Pentium	O
and	O
Celeron	O
branded	O
)	O
processors	O
,	O
Q4	O
2021	O
.	O
</s>
<s>
Supported	O
both	O
in	O
Golden	B-Device
Cove	I-Device
P-cores	O
and	O
Gracemont	B-Device
E-cores	O
.	O
</s>
<s>
AVX-512	B-General_Concept
are	O
512-bit	O
extensions	O
to	O
the	O
256-bit	O
Advanced	B-General_Concept
Vector	I-General_Concept
Extensions	I-General_Concept
SIMD	B-Device
instructions	O
for	O
x86	B-Operating_System
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
proposed	O
by	O
Intel	O
in	O
July	O
2013	O
,	O
and	O
are	O
supported	O
with	O
Intel	O
's	O
Knights	O
Landing	O
processor	O
.	O
</s>
<s>
AVX-512	B-General_Concept
instructions	O
are	O
encoded	O
with	O
the	O
new	O
EVEX	B-General_Concept
prefix	I-General_Concept
.	O
</s>
<s>
It	O
allows	O
4	O
operands	O
,	O
8	O
new	O
64-bit	O
opmask	O
registers	O
,	O
scalar	O
memory	O
mode	O
with	O
automatic	O
broadcast	O
,	O
explicit	O
rounding	O
control	O
,	O
and	O
compressed	O
displacement	O
memory	O
addressing	B-Language
mode	I-Language
.	O
</s>
<s>
The	O
width	O
of	O
the	O
register	O
file	O
is	O
increased	O
to	O
512	O
bits	O
and	O
total	O
register	O
count	O
increased	O
to	O
32	O
(	O
registers	O
ZMM0-ZMM31	O
)	O
in	O
x86-64	B-Device
mode	O
.	O
</s>
<s>
AVX-512	B-General_Concept
consists	O
of	O
multiple	O
instruction	O
subsets	O
,	O
not	O
all	O
of	O
which	O
are	O
meant	O
to	O
be	O
supported	O
by	O
all	O
processors	O
implementing	O
them	O
.	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
consists	O
of	O
the	O
following	O
:	O
</s>
<s>
AVX-512	B-General_Concept
Integer	O
Fused	O
Multiply	O
Add	O
(	O
IFMA	O
)	O
fused	O
multiply	O
add	O
for	O
512-bit	O
integers	O
.	O
</s>
<s>
AVX-512	B-General_Concept
Vector	O
Byte	O
Manipulation	O
Instructions	O
(	O
VBMI	O
)	O
adds	O
vector	O
byte	O
permutation	O
instructions	O
which	O
are	O
not	O
present	O
in	O
AVX-512BW	O
.	O
</s>
<s>
AVX-512	B-General_Concept
Vector	O
Neural	O
Network	O
Instructions	O
Word	O
variable	O
precision	O
(	O
4VNNIW	O
)	O
vector	O
instructions	O
for	O
deep	O
learning	O
.	O
</s>
<s>
AVX-512	B-General_Concept
Fused	O
Multiply	O
Accumulation	O
Packed	O
Single	O
precision	O
(	O
4FMAPS	O
)	O
vector	O
instructions	O
for	O
deep	O
learning	O
.	O
</s>
<s>
AVX-512	B-General_Concept
Vector	O
Neural	O
Network	O
Instructions	O
(	O
VNNI	O
)	O
vector	O
instructions	O
for	O
deep	O
learning	O
.	O
</s>
<s>
AVX-512	B-General_Concept
Galois	O
Field	O
New	O
Instructions	O
(	O
GFNI	O
)	O
vector	O
instructions	O
for	O
calculating	O
Galois	O
field	O
.	O
</s>
<s>
AVX-512	B-General_Concept
Vector	O
AES	B-Algorithm
instructions	O
(	O
VAES	O
)	O
vector	O
instructions	O
for	O
AES	B-Algorithm
coding	O
.	O
</s>
<s>
AVX-512	B-General_Concept
Vector	O
Byte	O
Manipulation	O
Instructions	O
2	O
(	O
VBMI2	O
)	O
byte/word	O
load	O
,	O
store	O
and	O
concatenation	O
with	O
shift	O
.	O
</s>
<s>
AVX-512	B-General_Concept
Bit	O
Algorithms	O
(	O
BITALG	O
)	O
byte/word	O
bit	B-Device
manipulation	I-Device
instructions	I-Device
expanding	O
VPOPCNTDQ	O
.	O
</s>
<s>
AVX-512	B-General_Concept
Bfloat16	O
Floating-Point	B-Algorithm
Instructions	O
(	O
BF16	O
)	O
vector	O
instructions	O
for	O
AI	O
acceleration	O
.	O
</s>
<s>
AVX-512	B-General_Concept
Half-Precision	O
Floating-Point	B-Algorithm
Instructions	O
(	O
FP16	O
)	O
vector	O
instructions	O
for	O
operating	O
on	O
floating-point	B-Algorithm
and	O
complex	O
numbers	O
with	O
reduced	O
precision	O
.	O
</s>
<s>
Only	O
the	O
core	O
extension	O
AVX-512F	O
(	O
AVX-512	B-General_Concept
Foundation	O
)	O
is	O
required	O
by	O
all	O
implementations	O
,	O
though	O
all	O
current	O
processors	O
also	O
support	O
CD	O
(	O
conflict	O
detection	O
)	O
;	O
computing	O
coprocessors	O
will	O
additionally	O
support	O
ER	O
,	O
PF	O
,	O
4VNNIW	O
,	O
4FMAPS	O
,	O
and	O
VPOPCNTDQ	O
,	O
while	O
central	O
processors	O
will	O
support	O
VL	O
,	O
DQ	O
,	O
BW	O
,	O
IFMA	O
,	O
VBMI	O
,	O
VPOPCNTDQ	O
,	O
VPCLMULQDQ	O
etc	O
.	O
</s>
<s>
The	O
updated	O
SSE/AVX	O
instructions	O
in	O
AVX-512F	O
use	O
the	O
same	O
mnemonics	O
as	O
AVX	O
versions	O
;	O
they	O
can	O
operate	O
on	O
512-bit	O
ZMM	O
registers	O
,	O
and	O
will	O
also	O
support	O
128/256	O
bit	O
XMM/YMM	O
registers	O
(	O
with	O
AVX-512VL	O
)	O
and	O
byte	O
,	O
word	O
,	O
doubleword	O
and	O
quadword	O
integer	O
operands	O
(	O
with	O
AVX-512BW/DQ	O
and	O
VBMI	O
)	O
.	O
</s>
<s>
:	O
AVX-512	B-General_Concept
is	O
disabled	O
by	O
default	O
in	O
Alder	B-Device
Lake	I-Device
processors	O
.	O
</s>
<s>
On	O
some	O
motherboards	O
with	O
some	O
BIOS	O
versions	O
,	O
AVX-512	B-General_Concept
can	O
be	O
enabled	O
in	O
the	O
BIOS	O
,	O
but	O
this	O
requires	O
disabling	O
E-cores	O
.	O
</s>
<s>
However	O
,	O
Intel	O
has	O
begun	O
fusing	O
AVX-512	B-General_Concept
off	O
of	O
new	O
Alder	B-Device
Lake	I-Device
processors	O
.	O
</s>
<s>
AVX-VNNI	O
is	O
a	O
VEX-coded	O
variant	O
of	O
the	O
AVX512-VNNI	O
instruction	B-General_Concept
set	I-General_Concept
extension	O
.	O
</s>
<s>
It	O
provides	O
the	O
same	O
set	O
of	O
operations	O
,	O
but	O
is	O
limited	O
to	O
256-bit	O
vectors	O
and	O
does	O
not	O
support	O
any	O
additional	O
features	O
of	O
EVEX	B-General_Concept
encoding	O
,	O
such	O
as	O
broadcasting	O
,	O
opmask	O
registers	O
or	O
accessing	O
more	O
than	O
16	O
vector	O
registers	O
.	O
</s>
<s>
This	O
extension	O
allows	O
to	O
support	O
VNNI	O
operations	O
even	O
when	O
full	O
AVX-512	B-General_Concept
support	O
is	O
not	O
implemented	O
in	O
the	O
processor	O
.	O
</s>
<s>
Increases	O
parallelism	O
and	O
throughput	O
in	O
floating	B-Algorithm
point	I-Algorithm
SIMD	B-Device
calculations	O
.	O
</s>
<s>
Blender	B-Application
uses	O
AVX	O
,	O
AVX2	O
and	O
AVX-512	B-General_Concept
in	O
the	O
Cycles	O
render	O
engine	O
.	O
</s>
<s>
Bloombase	O
uses	O
AVX	O
,	O
AVX2	O
and	O
AVX-512	B-General_Concept
in	O
their	O
Bloombase	O
Cryptographic	O
Module	O
(	O
BCM	O
)	O
.	O
</s>
<s>
Botan	B-Protocol
uses	O
both	O
AVX	O
and	O
AVX2	O
when	O
available	O
to	O
accelerate	O
some	O
algorithms	O
,	O
like	O
ChaCha	O
.	O
</s>
<s>
Crypto++	B-Language
uses	O
both	O
AVX	O
and	O
AVX2	O
when	O
available	O
to	O
accelerate	O
some	O
algorithms	O
,	O
like	O
Salsa	O
and	O
ChaCha	O
.	O
</s>
<s>
OpenSSL	B-Language
uses	O
AVX	O
-	O
and	O
AVX2-optimized	O
cryptographic	O
functions	O
since	O
version	O
1.0.2	O
.	O
</s>
<s>
Support	O
for	O
AVX-512	B-General_Concept
was	O
added	O
in	O
version	O
3.0.0	O
.	O
</s>
<s>
Prime95/MPrime	O
,	O
the	O
software	O
used	O
for	O
GIMPS	B-Application
,	O
started	O
using	O
the	O
AVX	O
instructions	O
since	O
version	O
27.1	O
,	O
AVX2	O
since	O
28.6	O
and	O
AVX-512	B-General_Concept
since	O
29.1	O
.	O
</s>
<s>
dav1d	O
AV1	B-Application
decoder	O
can	O
use	O
AVX2	O
and	O
AVX-512	B-General_Concept
on	O
supported	O
CPUs	O
.	O
</s>
<s>
SVT-AV1	O
AV1	B-Application
encoder	O
can	O
use	O
AVX2	O
and	O
AVX-512	B-General_Concept
to	O
accelerate	O
video	O
encoding	O
.	O
</s>
<s>
Einstein	B-Operating_System
@Home	I-Operating_System
uses	O
AVX	O
in	O
some	O
of	O
their	O
distributed	O
applications	O
that	O
search	O
for	O
gravitational	O
waves	O
.	O
</s>
<s>
Folding	B-Application
@home	I-Application
uses	O
AVX	O
on	O
calculation	O
cores	O
implemented	O
with	O
GROMACS	B-Application
library	O
.	O
</s>
<s>
Helios	O
uses	O
AVX	O
and	O
AVX2	O
hardware	O
acceleration	O
on	O
64-bit	B-Device
x86	I-Device
hardware	O
.	O
</s>
<s>
Horizon	B-Application
:	I-Application
Zero	I-Application
Dawn	I-Application
uses	O
AVX	O
in	O
its	O
Decima	O
game	O
engine	O
.	O
</s>
<s>
RPCS3	B-Language
,	O
an	O
open	O
source	O
PlayStation	B-Operating_System
3	I-Operating_System
emulator	O
,	O
uses	O
AVX2	O
and	O
AVX-512	B-General_Concept
instructions	O
to	O
emulate	O
PS3	B-Operating_System
games	O
.	O
</s>
<s>
Network	B-Protocol
Device	I-Protocol
Interface	I-Protocol
,	O
an	O
IP	O
video/audio	O
protocol	O
developed	O
by	O
NewTek	O
for	O
live	O
broadcast	O
production	O
,	O
uses	O
AVX	O
and	O
AVX2	O
for	O
increased	O
performance	O
.	O
</s>
<s>
TensorFlow	B-Language
since	O
version	O
1.6	O
and	O
tensorflow	B-Language
above	O
versions	O
requires	O
CPU	O
supporting	O
at	O
least	O
AVX	O
.	O
</s>
<s>
x264	B-Language
,	O
x265	B-Language
and	O
VTM	B-Algorithm
video	O
encoders	O
can	O
use	O
AVX2	O
or	O
AVX-512	B-General_Concept
to	O
speed	O
up	O
encoding	O
.	O
</s>
<s>
Various	O
CPU-based	O
cryptocurrency	O
miners	O
(	O
like	O
pooler	O
's	O
cpuminer	O
for	O
Bitcoin	B-Protocol
and	O
Litecoin	B-Protocol
)	O
use	O
AVX	O
and	O
AVX2	O
for	O
various	O
cryptography-related	O
routines	O
,	O
including	O
SHA-256	B-Algorithm
and	O
scrypt	B-Algorithm
.	O
</s>
<s>
libsodium	O
uses	O
AVX	O
in	O
the	O
implementation	O
of	O
scalar	O
multiplication	O
for	O
Curve25519	O
and	O
Ed25519	O
algorithms	O
,	O
AVX2	O
for	O
BLAKE2b	B-Algorithm
,	O
Salsa20	B-Algorithm
,	O
ChaCha20	O
,	O
and	O
AVX2	O
and	O
AVX-512	B-General_Concept
in	O
implementation	O
of	O
Argon2	B-Algorithm
algorithm	O
.	O
</s>
<s>
libvpx	B-Language
open	O
source	O
reference	O
implementation	O
of	O
VP8/VP9	O
encoder/decoder	O
,	O
uses	O
AVX2	O
or	O
AVX-512	B-General_Concept
when	O
available	O
.	O
</s>
<s>
FFTW	B-Application
can	O
utilize	O
AVX	O
,	O
AVX2	O
and	O
AVX-512	B-General_Concept
when	O
available	O
.	O
</s>
<s>
LLVMpipe	O
,	O
a	O
software	O
OpenGL	O
renderer	O
in	O
Mesa	B-Application
using	O
Gallium	O
and	O
LLVM	B-Application
infrastructure	O
,	O
uses	O
AVX2	O
when	O
available	O
.	O
</s>
<s>
glibc	B-Language
uses	O
AVX2	O
(	O
with	O
FMA	B-General_Concept
)	O
and	O
AVX-512	B-General_Concept
for	O
optimized	O
implementation	O
of	O
various	O
mathematical	O
(	O
i.e.	O
</s>
<s>
functions	O
in	O
libc	B-Language
.	O
</s>
<s>
Linux	B-Operating_System
kernel	I-Operating_System
can	O
use	O
AVX	O
or	O
AVX2	O
,	O
together	O
with	O
AES-NI	O
as	O
optimized	O
implementation	O
of	O
AES-GCM	B-Algorithm
cryptographic	O
algorithm	O
.	O
</s>
<s>
Linux	B-Operating_System
kernel	I-Operating_System
uses	O
AVX	O
or	O
AVX2	O
when	O
available	O
,	O
in	O
optimized	O
implementation	O
of	O
multiple	O
other	O
cryptographic	O
ciphers	O
:	O
Camellia	B-Algorithm
,	O
CAST5	B-Algorithm
,	O
CAST6	B-Algorithm
,	O
Serpent	B-Algorithm
,	O
Twofish	B-Algorithm
,	O
MORUS-1280	O
,	O
and	O
other	O
primitives	O
:	O
Poly1305	B-Algorithm
,	O
SHA-1	B-Algorithm
,	O
SHA-256	B-Algorithm
,	O
SHA-512	B-Algorithm
,	O
ChaCha20	O
.	O
</s>
<s>
POCL	O
,	O
a	O
portable	O
Computing	O
Language	O
,	O
that	O
provides	O
implementation	O
of	O
OpenCL	B-Application
,	O
makes	O
use	O
of	O
AVX	O
,	O
AVX2	O
and	O
AVX-512	B-General_Concept
when	O
possible	O
.	O
</s>
<s>
.NET	B-Application
and	O
.NET	B-Application
Framework	I-Application
can	O
utilize	O
AVX	O
,	O
AVX2	O
through	O
the	O
generic	O
System.Numerics.Vectors	O
namespace	O
.	O
</s>
<s>
.NET	B-Application
Core	I-Application
,	O
starting	O
from	O
version	O
2.1	O
and	O
more	O
extensively	O
after	O
version	O
3.0	O
can	O
directly	O
use	O
all	O
AVX	O
,	O
AVX2	O
intrinsics	O
through	O
the	O
System.Runtime.Intrinsics.X86	O
namespace	O
.	O
</s>
<s>
EmEditor	B-Application
19.0	O
and	O
above	O
uses	O
AVX2	O
to	O
speed	O
up	O
processing	O
.	O
</s>
<s>
Microsoft	B-Application
Teams	I-Application
uses	O
AVX2	O
instructions	O
to	O
create	O
a	O
blurred	O
or	O
custom	O
background	O
behind	O
video	O
chat	O
participants	O
,	O
and	O
for	O
background	O
noise	O
suppression	O
.	O
</s>
<s>
Pale	B-Protocol
Moon	I-Protocol
custom	O
Windows	B-Application
builds	O
greatly	O
increase	O
browsing	O
speed	O
due	O
to	O
the	O
use	O
of	O
AVX2	O
.	O
</s>
<s>
,	O
a	O
JSON	B-General_Concept
parsing	O
library	O
,	O
uses	O
AVX2	O
and	O
AVX-512	B-General_Concept
to	O
achieve	O
improved	O
decoding	O
speed	O
.	O
</s>
<s>
Tesseract	B-Language
OCR	I-Language
engine	O
uses	O
AVX	O
,	O
AVX2	O
and	O
AVX-512	B-General_Concept
to	O
accelerate	O
character	O
recognition	O
.	O
</s>
<s>
Since	O
AVX	O
instructions	O
are	O
wider	O
and	O
generate	O
more	O
heat	O
,	O
some	O
Intel	O
processors	O
have	O
provisions	O
to	O
reduce	O
the	O
Turbo	B-Device
Boost	I-Device
frequency	O
limit	O
when	O
such	O
instructions	O
are	O
being	O
executed	O
.	O
</s>
<s>
On	O
Skylake	B-Architecture
and	O
its	O
derivatives	O
,	O
the	O
throttling	O
is	O
divided	O
into	O
three	O
levels	O
:	O
</s>
<s>
L0	O
(	O
100%	O
)	O
:	O
The	O
normal	O
turbo	B-Device
boost	I-Device
limit	O
.	O
</s>
<s>
Soft-triggered	O
by	O
256-bit	O
"	O
heavy	O
"	O
(	O
floating-point	B-Algorithm
unit	O
:	O
FP	O
math	O
and	O
integer	O
multiplication	O
)	O
instructions	O
.	O
</s>
<s>
L2	O
(	O
~	O
60%	O
)	O
:	O
The	O
"	O
AVX-512	B-General_Concept
boost	O
"	O
limit	O
.	O
</s>
<s>
In	O
Ice	B-Device
Lake	I-Device
,	O
only	O
two	O
levels	O
persist	O
:	O
</s>
<s>
L0	O
(	O
100%	O
)	O
:	O
The	O
normal	O
turbo	B-Device
boost	I-Device
limit	O
.	O
</s>
<s>
Rocket	B-Device
Lake	I-Device
processors	O
do	O
not	O
trigger	O
frequency	O
reduction	O
upon	O
executing	O
any	O
kind	O
of	O
vector	O
instructions	O
regardless	O
of	O
the	O
vector	O
size	O
.	O
</s>
<s>
AVX-512VL	O
allows	O
for	O
using	O
256-bit	O
or	O
128-bit	O
operands	O
in	O
AVX-512	B-General_Concept
,	O
making	O
it	O
a	O
sensible	O
default	O
for	O
mixed	O
loads	O
.	O
</s>
