<s>
In	O
computing	O
,	O
Intel	O
's	O
Advanced	B-Device
Programmable	I-Device
Interrupt	I-Device
Controller	I-Device
(	O
APIC	O
)	O
is	O
a	O
family	O
of	O
interrupt	B-Architecture
controllers	I-Architecture
.	O
</s>
<s>
As	O
its	O
name	O
suggests	O
,	O
the	O
APIC	O
is	O
more	O
advanced	O
than	O
Intel	O
's	O
8259	B-Device
Programmable	B-Architecture
Interrupt	I-Architecture
Controller	I-Architecture
(	O
PIC	O
)	O
,	O
particularly	O
enabling	O
the	O
construction	O
of	O
multiprocessor	B-Operating_System
systems	O
.	O
</s>
<s>
It	O
is	O
one	O
of	O
several	O
architectural	O
designs	O
intended	O
to	O
solve	O
interrupt	B-Application
routing	O
efficiency	O
issues	O
in	O
multiprocessor	B-Operating_System
computer	O
systems	O
.	O
</s>
<s>
The	O
APIC	O
is	O
a	O
split	O
architecture	O
design	O
,	O
with	O
a	O
local	O
component	O
(	O
LAPIC	B-Device
)	O
usually	O
integrated	O
into	O
the	O
processor	O
itself	O
,	O
and	O
an	O
optional	O
I/O	B-Device
APIC	I-Device
on	O
a	O
system	O
bus	O
.	O
</s>
<s>
The	O
first	O
APIC	O
was	O
the	O
82489DX	B-Device
it	O
was	O
a	O
discrete	O
chip	O
that	O
functioned	O
both	O
as	O
local	O
and	O
I/O	B-Device
APIC	I-Device
.	O
</s>
<s>
The	O
82489DX	B-Device
enabled	O
construction	O
of	O
symmetric	B-Operating_System
multiprocessor	I-Operating_System
(	O
SMP	O
)	O
systems	O
with	O
the	O
Intel	B-General_Concept
486	I-General_Concept
and	O
early	O
Pentium	B-General_Concept
processors	O
;	O
for	O
example	O
,	O
the	O
reference	O
two-way	O
486	B-General_Concept
SMP	O
system	O
used	O
three	O
82489DX	B-Device
chips	O
,	O
two	O
as	O
local	B-Device
APICs	I-Device
and	O
one	O
as	O
I/O	B-Device
APIC	I-Device
.	O
</s>
<s>
Starting	O
with	O
the	O
P54C	O
processor	O
,	O
the	O
local	B-Device
APIC	I-Device
functionality	O
was	O
integrated	O
into	O
the	O
Intel	O
processors	O
 '	O
silicon	O
.	O
</s>
<s>
The	O
first	O
dedicated	O
I/O	B-Device
APIC	I-Device
was	O
the	O
Intel	O
82093AA	O
,	O
which	O
was	O
intended	O
for	O
PIIX3-based	O
systems	O
.	O
</s>
<s>
There	O
are	O
two	O
components	O
in	O
the	O
Intel	O
APIC	O
system	O
,	O
the	O
local	B-Device
APIC	I-Device
(	O
LAPIC	B-Device
)	O
and	O
the	O
I/O	B-Device
APIC	I-Device
.	O
</s>
<s>
There	O
is	O
one	O
LAPIC	B-Device
in	O
each	O
CPU	O
in	O
the	O
system	O
.	O
</s>
<s>
In	O
the	O
very	O
first	O
implementation	O
(	O
82489DX	B-Device
)	O
,	O
the	O
LAPIC	B-Device
was	O
a	O
discrete	O
circuit	O
,	O
as	O
opposed	O
to	O
its	O
later	O
implementation	O
in	O
Intel	O
processors	O
 '	O
silicon	O
.	O
</s>
<s>
There	O
is	O
typically	O
one	O
I/O	B-Device
APIC	I-Device
for	O
each	O
peripheral	O
bus	O
in	O
the	O
system	O
.	O
</s>
<s>
In	O
original	O
system	O
designs	O
,	O
LAPICs	B-Device
and	O
I/O	B-Device
APICs	I-Device
were	O
connected	O
by	O
a	O
dedicated	O
APIC	O
bus	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
82489DX	B-Device
has	O
an	O
APIC	O
version	O
number	O
of	O
0	O
,	O
while	O
version	O
1	O
was	O
assigned	O
to	O
the	O
first	O
generation	O
of	O
local	B-Device
APICs	I-Device
integrated	O
in	O
the	O
Pentium	B-General_Concept
90	O
and	O
100	O
processors	O
.	O
</s>
<s>
In	O
systems	O
containing	O
an	O
8259	B-Device
PIC	I-Device
,	O
the	O
8259	B-Device
may	O
be	O
connected	O
to	O
the	O
LAPIC	B-Device
in	O
the	O
system	O
's	O
bootstrap	O
processor	O
(	O
BSP	O
)	O
,	O
one	O
of	O
the	O
system	O
's	O
I/O	B-Device
APICs	I-Device
,	O
or	O
both	O
.	O
</s>
<s>
Logically	O
,	O
however	O
,	O
the	O
8259	B-Device
is	O
only	O
connected	O
once	O
at	O
any	O
given	O
time	O
.	O
</s>
<s>
The	O
first-generation	O
Intel	O
APIC	O
chip	O
,	O
the	O
82489DX	B-Device
,	O
which	O
was	O
meant	O
to	O
be	O
used	O
with	O
Intel	B-General_Concept
80486	I-General_Concept
and	O
early	O
Pentium	B-General_Concept
processors	O
,	O
is	O
actually	O
an	O
external	O
local	O
and	O
I/O	B-Device
APIC	I-Device
in	O
one	O
circuit	O
.	O
</s>
<s>
The	O
Intel	O
MP	O
1.4	O
specification	O
refers	O
to	O
it	O
as	O
"	O
discrete	O
APIC	O
"	O
in	O
contrast	O
with	O
the	O
"	O
integrated	O
APIC	O
"	O
found	O
in	O
most	O
of	O
the	O
Pentium	B-General_Concept
processors	O
.	O
</s>
<s>
The	O
82489DX	B-Device
had	O
16	O
interrupt	B-Application
lines	I-Application
;	O
it	O
also	O
had	O
a	O
quirk	O
that	O
it	O
could	O
lose	O
some	O
ISA	O
interrupts	B-Application
.	O
</s>
<s>
In	O
a	O
multiprocessor	B-Operating_System
486	B-General_Concept
system	O
,	O
each	O
CPU	O
had	O
to	O
be	O
paired	O
with	O
its	O
own	O
82489DX	B-Device
;	O
additionally	O
a	O
supplementary	O
82489DX	B-Device
had	O
to	O
be	O
used	O
as	O
I/O	B-Device
APIC	I-Device
.	O
</s>
<s>
The	O
82489DX	B-Device
could	O
not	O
emulate	O
the	O
8259A	B-Device
(	O
XT-PIC	O
)	O
so	O
these	O
also	O
had	O
to	O
be	O
included	O
as	O
physical	O
chips	O
for	O
backwards	O
compatibility	O
.	O
</s>
<s>
The	O
82489DX	B-Device
was	O
a	O
packaged	O
as	O
a	O
132-pin	O
PQFP	O
.	O
</s>
<s>
Local	B-Device
APICs	I-Device
(	O
LAPICs	B-Device
)	O
manage	O
all	O
external	O
interrupts	B-Application
for	O
some	O
specific	O
processor	O
in	O
an	O
SMP	O
system	O
.	O
</s>
<s>
In	O
addition	O
,	O
they	O
are	O
able	O
to	O
accept	O
and	O
generate	O
inter-processor	B-Device
interrupts	I-Device
(	O
IPIs	O
)	O
between	O
LAPICs	B-Device
.	O
</s>
<s>
LAPICs	B-Device
may	O
support	O
up	O
to	O
224	O
usable	O
interrupt	B-Application
vectors	O
from	O
an	O
I/O	B-Device
APIC	I-Device
.	O
</s>
<s>
All	O
Intel	O
processors	O
starting	O
with	O
the	O
P5	B-General_Concept
microarchitecture	O
(	O
P54C	O
)	O
have	O
a	O
built-in	O
local	B-Device
APIC	I-Device
.	O
</s>
<s>
However	O
,	O
if	O
the	O
local	B-Device
APIC	I-Device
is	O
disabled	O
in	O
a	O
P5	B-General_Concept
processor	O
,	O
it	O
cannot	O
be	O
re-enabled	O
by	O
software	O
;	O
this	O
limitation	O
no	O
longer	O
exists	O
in	O
the	O
P6	B-Device
processors	I-Device
and	O
later	O
ones	O
.	O
</s>
<s>
The	O
Message	B-Architecture
Signaled	I-Architecture
Interrupts	I-Architecture
(	O
MSI	O
)	O
feature	O
of	O
the	O
PCI	O
2.2	O
and	O
later	O
specifications	O
cannot	O
be	O
used	O
without	O
the	O
local	B-Device
APIC	I-Device
being	O
enabled	O
.	O
</s>
<s>
Use	O
of	O
MSI	O
obviates	O
the	O
need	O
for	O
an	O
I/O	B-Device
APIC	I-Device
.	O
</s>
<s>
Additionally	O
,	O
up	O
to	O
224	O
interrupts	B-Application
are	O
supported	O
in	O
MSI	O
mode	O
,	O
and	O
IRQ	O
sharing	O
is	O
not	O
allowed	O
.	O
</s>
<s>
Another	O
advantage	O
of	O
the	O
local	B-Device
APIC	I-Device
is	O
that	O
it	O
also	O
provides	O
a	O
high-resolution	O
(	O
on	O
the	O
order	O
of	O
one	O
microsecond	O
or	O
better	O
)	O
timer	O
that	O
can	O
be	O
used	O
in	O
both	O
interval	O
and	O
one-off	O
mode	O
.	O
</s>
<s>
A	O
Microsoft	O
document	O
from	O
2002	O
(	O
which	O
advocated	O
for	O
the	O
adoption	O
of	O
High	O
Precision	O
Event	O
Timer	O
instead	O
)	O
criticized	O
the	O
LAPIC	B-Device
timer	O
for	O
having	O
"	O
poor	O
resolution	O
"	O
and	O
stating	O
that	O
"	O
the	O
clocks	O
silicon	O
is	O
sometimes	O
very	O
buggy	O
"	O
.	O
</s>
<s>
Nevertheless	O
,	O
the	O
APIC	O
timer	O
is	O
used	O
for	O
example	O
by	O
Windows	B-Device
7	I-Device
when	O
profiling	O
is	O
enabled	O
,	O
and	O
by	O
Windows	B-Application
8	I-Application
in	O
all	O
circumstances	O
.	O
</s>
<s>
(	O
Before	O
Windows	B-Application
8	I-Application
claimed	O
exclusive	O
rights	O
to	O
this	O
timer	O
,	O
it	O
was	O
also	O
used	O
by	O
some	O
programs	O
like	O
CPU-Z	B-Application
.	O
)	O
</s>
<s>
When	O
enabled	O
on	O
a	O
computer	O
with	O
an	O
APIC	O
timer	O
,	O
the	O
kernel	B-Operating_System
does	O
not	O
use	O
the	O
8253	B-Device
programmable	B-Device
interval	I-Device
timer	I-Device
for	O
timekeeping	O
.	O
</s>
<s>
Generally	O
,	O
the	O
only	O
way	O
to	O
determine	O
the	O
local	B-Device
APIC	I-Device
timer	O
’s	O
frequency	O
is	O
to	O
measure	O
it	O
using	O
the	O
PIT	O
or	O
CMOS	O
timer	O
,	O
which	O
yields	O
only	O
an	O
approximate	O
result.	O
"	O
</s>
<s>
I/O	B-Device
APICs	I-Device
contain	O
a	O
redirection	O
table	O
,	O
which	O
is	O
used	O
to	O
route	O
the	O
interrupts	B-Application
it	O
receives	O
from	O
peripheral	O
buses	O
to	O
one	O
or	O
more	O
local	B-Device
APICs	I-Device
.	O
</s>
<s>
Early	O
I/O	B-Device
APICs	I-Device
(	O
like	O
82489DX	B-Device
,	O
SIO.A	O
and	O
PCEB/ESC	O
)	O
only	O
had	O
support	O
for	O
16	O
interrupt	B-Application
lines	I-Application
,	O
but	O
later	O
ones	O
like	O
82093AA	O
(	O
separate	O
chip	O
for	O
PIIX3/PIIX4	O
)	O
had	O
support	O
for	O
24	O
interrupt	B-Application
lines	I-Application
.	O
</s>
<s>
The	O
82093AA	O
normally	O
connected	O
to	O
the	O
PIIX3/PIIX4	O
and	O
used	O
its	O
integrated	O
legacy	O
8259	B-Device
PICs	B-Architecture
.	O
</s>
<s>
The	O
ICH1	O
and	O
Intel	O
815	O
integrated	O
the	O
I/O	B-Device
APIC	I-Device
.	O
</s>
<s>
According	O
to	O
a	O
2009	O
Intel	O
benchmark	O
using	O
Linux	B-Application
,	O
the	O
I/O	B-Device
APIC	I-Device
reduced	O
interrupt	B-General_Concept
latency	I-General_Concept
by	O
a	O
factor	O
of	O
almost	O
three	O
relative	O
to	O
the	O
8259	B-Device
emulation	O
(	O
XT-PIC	O
)	O
,	O
while	O
using	O
MSI	O
reduced	O
the	O
latency	O
even	O
more	O
,	O
by	O
a	O
factor	O
of	O
nearly	O
seven	O
relative	O
to	O
the	O
XT-PIC	O
baseline	O
.	O
</s>
<s>
The	O
xAPIC	O
was	O
introduced	O
with	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
,	O
while	O
the	O
x2APIC	O
is	O
the	O
most	O
recent	O
generation	O
of	O
the	O
Intel	O
's	O
programmable	B-Architecture
interrupt	I-Architecture
controller	I-Architecture
,	O
introduced	O
with	O
the	O
Nehalem	B-Device
microarchitecture	I-Device
in	O
November	O
2008	O
.	O
</s>
<s>
The	O
improved	O
interface	O
reduces	O
the	O
number	O
of	O
needed	O
APIC	O
register	O
accesses	O
for	O
sending	O
inter-processor	B-Device
interrupts	I-Device
(	O
IPIs	O
)	O
.	O
</s>
<s>
Because	O
of	O
this	O
advantage	O
,	O
KVM	B-Application
can	O
and	O
does	O
emulate	O
the	O
x2APIC	O
for	O
older	O
processors	O
that	O
do	O
not	O
physically	O
support	O
it	O
,	O
and	O
this	O
support	O
is	O
exposed	O
from	O
QEMU	B-Application
going	O
back	O
to	O
Conroe	O
and	O
even	O
for	O
AMD	B-General_Concept
Opteron	I-General_Concept
G-series	O
processors	O
(	O
neither	O
of	O
which	O
natively	O
support	O
x2APIC	O
)	O
.	O
</s>
<s>
APICv	O
is	O
the	O
Intel	O
's	O
brand	O
name	O
for	O
hardware	B-General_Concept
virtualization	I-General_Concept
support	O
aimed	O
at	O
reducing	O
interrupt	B-Application
overhead	O
in	O
guests	O
.	O
</s>
<s>
There	O
are	O
a	O
number	O
of	O
known	O
bugs	O
in	O
implementations	O
of	O
APIC	O
systems	O
,	O
especially	O
with	O
concern	O
to	O
how	O
the	O
8254	B-Device
is	O
connected	O
.	O
</s>
<s>
Defective	O
BIOSes	O
may	O
not	O
set	O
up	O
interrupt	B-Application
routing	O
properly	O
,	O
or	O
provide	O
incorrect	O
ACPI	B-Device
tables	O
and	O
Intel	O
MultiProcessor	B-Device
Specification	I-Device
(	O
MPS	O
)	O
tables	O
.	O
</s>
<s>
On	O
older	O
operating	O
systems	O
,	O
the	O
I/O	O
and	O
local	B-Device
APICs	I-Device
often	O
had	O
to	O
be	O
disabled	O
.	O
</s>
<s>
While	O
this	O
is	O
not	O
possible	O
anymore	O
due	O
to	O
the	O
prevalence	O
of	O
symmetric	B-Operating_System
multiprocessor	I-Operating_System
and	O
multi-core	B-Architecture
systems	O
,	O
the	O
bugs	O
in	O
the	O
firmware	O
and	O
the	O
operating	O
systems	O
are	O
now	O
a	O
rare	O
occurrence	O
.	O
</s>
<s>
AMD	O
and	O
Cyrix	O
once	O
proposed	O
a	O
somewhat	O
similar-in-purpose	O
OpenPIC	B-Device
architecture	O
supporting	O
up	O
to	O
32	O
processors	O
;	O
it	O
had	O
at	O
least	O
declarative	O
support	O
from	O
IBM	O
and	O
Compaq	O
around	O
1995	O
.	O
</s>
<s>
No	O
x86	O
motherboard	O
was	O
released	O
with	O
OpenPIC	B-Device
however	O
.	O
</s>
<s>
After	O
the	O
OpenPIC	B-Device
's	O
failure	O
in	O
the	O
x86	O
market	O
,	O
AMD	O
licensed	O
Intel	O
's	O
APIC	O
for	O
its	O
AMD	B-Architecture
Athlon	I-Architecture
and	O
later	O
processors	O
.	O
</s>
<s>
IBM	O
however	O
developed	O
their	O
MultiProcessor	B-Device
Interrupt	I-Device
Controller	I-Device
(	O
MPIC	O
)	O
based	O
on	O
the	O
OpenPIC	B-Device
register	O
specifications	O
.	O
</s>
<s>
MPIC	O
was	O
used	O
in	O
PowerPC	B-Architecture
based	O
designs	O
,	O
including	O
those	O
of	O
IBM	O
,	O
for	O
instance	O
in	O
some	O
RS/6000	B-Device
systems	O
,	O
but	O
also	O
by	O
Apple	O
,	O
as	O
late	O
as	O
their	O
Power	B-Device
Mac	I-Device
G5s	I-Device
.	O
</s>
