<s>
The	O
ARM	O
Advanced	B-Architecture
Microcontroller	I-Architecture
Bus	I-Architecture
Architecture	I-Architecture
(	O
AMBA	B-Architecture
)	O
is	O
an	O
open-standard	O
,	O
on-chip	O
interconnect	B-General_Concept
specification	O
for	O
the	O
connection	O
and	O
management	O
of	O
functional	B-General_Concept
blocks	I-General_Concept
in	O
system-on-a-chip	B-Architecture
(	O
SoC	B-Architecture
)	O
designs	O
.	O
</s>
<s>
It	O
facilitates	O
development	O
of	O
multi-processor	O
designs	O
with	O
large	O
numbers	O
of	O
controllers	O
and	O
components	O
with	O
a	O
bus	B-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
Since	O
its	O
inception	O
,	O
the	O
scope	O
of	O
AMBA	B-Architecture
has	O
,	O
despite	O
its	O
name	O
,	O
gone	O
far	O
beyond	O
microcontroller	O
devices	O
.	O
</s>
<s>
Today	O
,	O
AMBA	B-Architecture
is	O
widely	O
used	O
on	O
a	O
range	O
of	O
ASIC	O
and	O
SoC	B-Architecture
parts	O
including	O
applications	O
processors	O
used	O
in	O
modern	O
portable	O
mobile	O
devices	O
like	O
smartphones	B-Application
.	O
</s>
<s>
AMBA	B-Architecture
is	O
a	O
registered	O
trademark	O
of	O
ARM	O
Ltd	O
.	O
</s>
<s>
AMBA	B-Architecture
was	O
introduced	O
by	O
ARM	O
in	O
1996	O
.	O
</s>
<s>
The	O
first	O
AMBA	B-Architecture
buses	O
were	O
the	O
Advanced	O
System	O
Bus	O
(	O
ASB	O
)	O
and	O
the	O
Advanced	O
Peripheral	O
Bus	O
(	O
APB	O
)	O
.	O
</s>
<s>
In	O
its	O
second	O
version	O
,	O
AMBA	B-Architecture
2	O
in	O
1999	O
,	O
ARM	O
added	O
AMBA	B-Architecture
High-performance	I-Architecture
Bus	I-Architecture
(	O
AHB	O
)	O
that	O
is	O
a	O
single	O
clock-edge	O
protocol	O
.	O
</s>
<s>
In	O
2003	O
,	O
ARM	O
introduced	O
the	O
third	O
generation	O
,	O
AMBA	B-Architecture
3	O
,	O
including	O
Advanced	B-Protocol
eXtensible	I-Protocol
Interface	I-Protocol
(	O
AXI	O
)	O
to	O
reach	O
even	O
higher	O
performance	O
interconnect	B-General_Concept
and	O
the	O
Advanced	O
Trace	O
Bus	O
(	O
ATB	O
)	O
as	O
part	O
of	O
the	O
CoreSight	O
on-chip	O
debug	O
and	O
trace	O
solution	O
.	O
</s>
<s>
In	O
2010	O
the	O
AMBA	B-Architecture
4	O
specifications	O
were	O
introduced	O
starting	O
with	O
AMBA	B-Architecture
4	O
AXI4	O
,	O
then	O
in	O
2011	O
extending	O
system-wide	O
coherency	O
with	O
AMBA	B-Architecture
4	O
AXI	O
Coherency	O
Extensions	O
(	O
ACE	O
)	O
.	O
</s>
<s>
In	O
2013	O
the	O
AMBA	B-Architecture
5	O
Coherent	O
Hub	O
Interface	O
(	O
CHI	O
)	O
specification	O
was	O
introduced	O
,	O
with	O
a	O
re-designed	O
high-speed	O
transport	O
layer	O
and	O
features	O
designed	O
to	O
reduce	O
congestion	O
.	O
</s>
<s>
An	O
important	O
aspect	O
of	O
an	O
SoC	B-Architecture
is	O
not	O
only	O
which	O
components	O
or	O
blocks	O
it	O
houses	O
,	O
but	O
also	O
how	O
they	O
interconnect	B-General_Concept
.	O
</s>
<s>
AMBA	B-Architecture
is	O
a	O
solution	O
for	O
the	O
blocks	O
to	O
interface	O
with	O
each	O
other	O
.	O
</s>
<s>
The	O
objective	O
of	O
the	O
AMBA	B-Architecture
specification	I-Architecture
is	O
to	O
:	O
</s>
<s>
be	O
technology	O
independent	O
,	O
to	O
allow	O
reuse	O
of	O
IP	B-Architecture
cores	I-Architecture
,	O
peripheral	O
and	O
system	O
macrocells	O
across	O
diverse	O
IC	O
processes	O
,	O
</s>
<s>
The	O
AMBA	B-Architecture
specification	I-Architecture
defines	O
an	O
on-chip	O
communications	O
standard	O
for	O
designing	O
high-performance	O
embedded	O
microcontrollers	O
.	O
</s>
<s>
The	O
AMBA	B-Architecture
5	O
specification	O
defines	O
the	O
following	O
buses/interfaces	O
:	O
</s>
<s>
The	O
AMBA	B-Architecture
4	O
specification	O
defines	O
following	O
buses/interfaces	O
:	O
</s>
<s>
AMBA	B-Architecture
3	O
specification	O
defines	O
four	O
buses/interfaces	O
:	O
</s>
<s>
AMBA	B-Architecture
2	O
specification	O
defines	O
three	O
buses/interfaces	O
:	O
</s>
<s>
AMBA	B-Architecture
specification	I-Architecture
(	O
First	O
version	O
)	O
defines	O
two	O
buses/interfaces	O
:	O
</s>
<s>
ACE	O
,	O
defined	O
as	O
part	O
of	O
the	O
AMBA	B-Architecture
4	O
specification	O
,	O
extends	O
AXI	O
with	O
additional	O
signalling	O
introducing	O
system	O
wide	O
coherency	O
.	O
</s>
<s>
This	O
system	O
coherency	O
allows	O
multiple	O
processors	O
to	O
share	O
memory	O
and	O
enables	O
technology	O
like	O
ARM	O
's	O
big.LITTLE	B-Architecture
processing	O
.	O
</s>
<s>
AXI	O
,	O
the	O
third	O
generation	O
of	O
AMBA	B-Architecture
interface	O
defined	O
in	O
the	O
AMBA	B-Architecture
3	O
specification	O
,	O
is	O
targeted	O
at	O
high	O
performance	O
,	O
high	O
clock	O
frequency	O
system	O
designs	O
and	O
includes	O
features	O
that	O
make	O
it	O
suitable	O
for	O
high	O
speed	O
sub-micrometer	O
interconnect	B-General_Concept
:	O
</s>
<s>
AHB	O
is	O
a	O
bus	O
protocol	O
introduced	O
in	O
Advanced	B-Architecture
Microcontroller	I-Architecture
Bus	I-Architecture
Architecture	I-Architecture
version	O
2	O
published	O
by	O
ARM	O
Ltd	O
company	O
.	O
</s>
<s>
Access	O
to	O
the	O
target	O
device	O
is	O
controlled	O
through	O
a	O
MUX	B-Protocol
(	O
non-tristate	O
)	O
,	O
thereby	O
admitting	O
bus-access	O
to	O
one	O
bus-master	O
at	O
a	O
time	O
.	O
</s>
<s>
AHB-Lite	O
is	O
a	O
subset	O
of	O
AHB	O
formally	O
defined	O
in	O
the	O
AMBA	B-Architecture
3	O
standard	O
.	O
</s>
<s>
A	O
family	O
of	O
synthesizable	O
intellectual	O
property	O
(	O
IP	B-Architecture
)	O
cores	O
AMBA	B-Architecture
Products	O
is	O
licensable	O
from	O
ARM	O
Limited	O
that	O
implement	O
a	O
digital	B-General_Concept
bus	I-General_Concept
in	O
an	O
SoC	B-Architecture
for	O
the	O
efficient	O
moving	O
and	O
storing	O
of	O
data	O
using	O
the	O
AMBA	B-Architecture
protocol	O
specifications	O
.	O
</s>
<s>
The	O
AMBA	B-Architecture
family	O
includes	O
AMBA	B-Architecture
Network	O
Interconnect	B-General_Concept
(	O
CoreLink	O
NIC-400	O
)	O
,	O
Cache	B-Architecture
Coherent	I-Architecture
Interconnect	I-Architecture
(	O
CoreLink	O
CCI-500	O
)	O
,	O
SDRAM	O
memory	O
controllers	O
(	O
CoreLink	O
DMC-400	O
)	O
,	O
DMA	B-General_Concept
controllers	I-General_Concept
(	O
CoreLink	O
DMA-230	O
,	O
DMA-330	O
)	O
,	O
level	O
2	O
cache	O
controllers	O
(	O
L2C-310	O
)	O
,	O
etc	O
.	O
</s>
<s>
A	O
number	O
of	O
manufacturers	O
utilize	O
AMBA	B-Architecture
buses	O
for	O
non-ARM	O
designs	O
.	O
</s>
<s>
As	O
an	O
example	O
Infineon	O
uses	O
an	O
AMBA	B-Architecture
bus	O
for	O
the	O
ADM5120	O
SoC	B-Architecture
based	O
on	O
the	O
MIPS	B-Device
architecture	I-Device
.	O
</s>
