<s>
Addressing	B-Language
modes	I-Language
are	O
an	O
aspect	O
of	O
the	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
in	O
most	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
designs	O
.	O
</s>
<s>
The	O
various	O
addressing	B-Language
modes	I-Language
that	O
are	O
defined	O
in	O
a	O
given	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
define	O
how	O
the	O
machine	B-Language
language	I-Language
instructions	O
in	O
that	O
architecture	O
identify	O
the	O
operand(s )	O
of	O
each	O
instruction	B-General_Concept
.	O
</s>
<s>
An	O
addressing	B-Language
mode	I-Language
specifies	O
how	O
to	O
calculate	O
the	O
effective	O
memory	B-General_Concept
address	I-General_Concept
of	O
an	O
operand	O
by	O
using	O
information	O
held	O
in	O
registers	O
and/or	O
constants	O
contained	O
within	O
a	O
machine	B-Language
instruction	I-Language
or	O
elsewhere	O
.	O
</s>
<s>
In	O
computer	B-General_Concept
programming	I-General_Concept
,	O
addressing	B-Language
modes	I-Language
are	O
primarily	O
of	O
interest	O
to	O
those	O
who	O
write	O
in	O
assembly	B-Language
languages	I-Language
and	O
to	O
compiler	B-Language
writers	O
.	O
</s>
<s>
For	O
a	O
related	O
concept	O
see	O
orthogonal	B-General_Concept
instruction	I-General_Concept
set	I-General_Concept
which	O
deals	O
with	O
the	O
ability	O
of	O
any	O
instruction	B-General_Concept
to	O
use	O
any	O
addressing	B-Language
mode	I-Language
.	O
</s>
<s>
There	O
are	O
no	O
generally	O
accepted	O
names	O
for	O
addressing	B-Language
modes	I-Language
:	O
different	O
authors	O
and	O
computer	O
manufacturers	O
may	O
give	O
different	O
names	O
to	O
the	O
same	O
addressing	B-Language
mode	I-Language
,	O
or	O
the	O
same	O
names	O
to	O
different	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
Furthermore	O
,	O
an	O
addressing	B-Language
mode	I-Language
which	O
,	O
in	O
one	O
given	O
architecture	O
,	O
is	O
treated	O
as	O
a	O
single	O
addressing	B-Language
mode	I-Language
may	O
represent	O
functionality	O
that	O
,	O
in	O
another	O
architecture	O
,	O
is	O
covered	O
by	O
two	O
or	O
more	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
For	O
example	O
,	O
some	O
complex	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
CISC	O
)	O
architectures	O
,	O
such	O
as	O
the	O
Digital	O
Equipment	O
Corporation	O
(	O
DEC	O
)	O
VAX	B-Device
,	O
treat	O
registers	O
and	O
literal	O
or	O
immediate	O
constants	O
as	O
just	O
another	O
addressing	B-Language
mode	I-Language
.	O
</s>
<s>
Others	O
,	O
such	O
as	O
the	O
IBM	B-Application
System/360	I-Application
and	O
its	O
successors	O
,	O
and	O
most	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
designs	O
,	O
encode	O
this	O
information	O
within	O
the	O
instruction	B-General_Concept
.	O
</s>
<s>
Thus	O
,	O
the	O
latter	O
machines	O
have	O
three	O
distinct	O
instruction	B-General_Concept
codes	O
for	O
copying	O
one	O
register	B-General_Concept
to	O
another	O
,	O
copying	O
a	O
literal	O
constant	O
into	O
a	O
register	B-General_Concept
,	O
and	O
copying	O
the	O
contents	O
of	O
a	O
memory	B-General_Concept
location	I-General_Concept
into	O
a	O
register	B-General_Concept
,	O
while	O
the	O
VAX	B-Device
has	O
only	O
a	O
single	O
"	O
MOV	O
"	O
instruction	B-General_Concept
.	O
</s>
<s>
The	O
term	O
"	O
addressing	B-Language
mode	I-Language
"	O
is	O
itself	O
subject	O
to	O
different	O
interpretations	O
:	O
either	O
"	O
memory	B-General_Concept
address	I-General_Concept
calculation	O
mode	O
"	O
or	O
"	O
operand	O
accessing	O
mode	O
"	O
.	O
</s>
<s>
Under	O
the	O
first	O
interpretation	O
,	O
instructions	O
that	O
do	O
not	O
read	O
from	O
memory	O
or	O
write	O
to	O
memory	O
(	O
such	O
as	O
"	O
add	O
literal	O
to	O
register	B-General_Concept
"	O
)	O
are	O
considered	O
not	O
to	O
have	O
an	O
"	O
addressing	B-Language
mode	I-Language
"	O
.	O
</s>
<s>
The	O
second	O
interpretation	O
allows	O
for	O
machines	O
such	O
as	O
VAX	B-Device
which	O
use	O
operand	O
mode	O
bits	O
to	O
allow	O
for	O
a	O
register	B-General_Concept
or	O
for	O
a	O
literal	O
operand	O
.	O
</s>
<s>
Only	O
the	O
first	O
interpretation	O
applies	O
to	O
instructions	O
such	O
as	O
"	O
load	O
effective	B-Language
address	I-Language
,	O
"	O
which	O
loads	O
the	O
address	B-General_Concept
of	O
the	O
operand	O
,	O
not	O
the	O
operand	O
itself	O
.	O
</s>
<s>
The	O
addressing	B-Language
modes	I-Language
listed	O
below	O
are	O
divided	O
into	O
code	O
addressing	O
and	O
data	O
addressing	O
.	O
</s>
<s>
Most	O
computer	O
architectures	O
maintain	O
this	O
distinction	O
,	O
but	O
there	O
are	O
(	O
or	O
have	O
been	O
)	O
some	O
architectures	O
which	O
allow	O
(	O
almost	O
)	O
all	O
addressing	B-Language
modes	I-Language
to	O
be	O
used	O
in	O
any	O
context	O
.	O
</s>
<s>
The	O
instructions	O
shown	O
below	O
are	O
purely	O
representative	O
in	O
order	O
to	O
illustrate	O
the	O
addressing	B-Language
modes	I-Language
,	O
and	O
do	O
not	O
necessarily	O
reflect	O
the	O
mnemonics	O
used	O
by	O
any	O
particular	O
computer	O
.	O
</s>
<s>
Computer	O
architectures	O
vary	O
greatly	O
as	O
to	O
the	O
number	O
of	O
addressing	B-Language
modes	I-Language
they	O
provide	O
in	O
hardware	O
.	O
</s>
<s>
There	O
are	O
some	O
benefits	O
to	O
eliminating	O
complex	O
addressing	B-Language
modes	I-Language
and	O
using	O
only	O
one	O
or	O
a	O
few	O
simpler	O
addressing	B-Language
modes	I-Language
,	O
even	O
though	O
it	O
requires	O
a	O
few	O
extra	O
instructions	O
,	O
and	O
perhaps	O
an	O
extra	O
register	B-General_Concept
.	O
</s>
<s>
It	O
has	O
proven	O
much	O
easier	O
to	O
design	O
pipelined	B-General_Concept
CPUs	I-General_Concept
if	O
the	O
only	O
addressing	B-Language
modes	I-Language
available	O
are	O
simple	O
ones	O
.	O
</s>
<s>
Most	O
RISC	B-Architecture
architectures	I-Architecture
have	O
only	O
about	O
five	O
simple	O
addressing	B-Language
modes	I-Language
,	O
while	O
CISC	B-Architecture
architectures	I-Architecture
such	O
as	O
the	O
DEC	B-Device
VAX	I-Device
have	O
over	O
a	O
dozen	O
addressing	B-Language
modes	I-Language
,	O
some	O
of	O
which	O
are	O
quite	O
complicated	O
.	O
</s>
<s>
The	O
IBM	B-Application
System/360	I-Application
architecture	O
had	O
only	O
three	O
addressing	B-Language
modes	I-Language
;	O
a	O
few	O
more	O
have	O
been	O
added	O
for	O
the	O
System/390	B-Device
.	O
</s>
<s>
IBM	B-Application
System/360	I-Application
and	O
successors	O
,	O
most	O
RISC	B-Architecture
)	O
.	O
</s>
<s>
But	O
when	O
there	O
are	O
many	O
addressing	B-Language
modes	I-Language
,	O
a	O
specific	O
field	O
is	O
often	O
set	O
aside	O
in	O
the	O
instruction	B-General_Concept
to	O
specify	O
the	O
addressing	B-Language
mode	I-Language
.	O
</s>
<s>
The	O
DEC	B-Device
VAX	I-Device
allowed	O
multiple	O
memory	O
operands	O
for	O
almost	O
all	O
instructions	O
,	O
and	O
so	O
reserved	O
the	O
first	O
few	O
bits	O
of	O
each	O
operand	O
specifier	O
to	O
indicate	O
the	O
addressing	B-Language
mode	I-Language
for	O
that	O
particular	O
operand	O
.	O
</s>
<s>
Keeping	O
the	O
addressing	B-Language
mode	I-Language
specifier	O
bits	O
separate	O
from	O
the	O
opcode	O
operation	O
bits	O
produces	O
an	O
orthogonal	B-General_Concept
instruction	I-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Even	O
on	O
a	O
computer	O
with	O
many	O
addressing	B-Language
modes	I-Language
,	O
measurements	O
of	O
actual	O
programs	O
indicate	O
that	O
the	O
simple	O
addressing	B-Language
modes	I-Language
listed	O
below	O
account	O
for	O
some	O
90%	O
or	O
more	O
of	O
all	O
addressing	B-Language
modes	I-Language
used	O
.	O
</s>
<s>
Since	O
most	O
such	O
measurements	O
are	O
based	O
on	O
code	O
generated	O
from	O
high-level	O
languages	O
by	O
compilers	B-Language
,	O
this	O
reflects	O
to	O
some	O
extent	O
the	O
limitations	O
of	O
the	O
compilers	B-Language
being	O
used	O
.	O
</s>
<s>
Some	O
instruction	B-General_Concept
set	I-General_Concept
architectures	I-General_Concept
,	O
such	O
as	O
Intel	B-Operating_System
x86	I-Operating_System
and	O
IBM/360	B-Application
and	O
its	O
successors	O
,	O
have	O
a	O
load	O
effective	B-Language
address	I-Language
instruction	B-General_Concept
.	O
</s>
<s>
This	O
calculates	O
the	O
effective	O
operand	O
address	B-General_Concept
and	O
loads	O
it	O
into	O
a	O
register	B-General_Concept
,	O
without	O
accessing	O
the	O
memory	O
it	O
refers	O
to	O
.	O
</s>
<s>
This	O
can	O
be	O
useful	O
when	O
passing	O
the	O
address	B-General_Concept
of	O
an	O
array	B-Data_Structure
element	I-Data_Structure
to	O
a	O
subroutine	O
.	O
</s>
<s>
It	O
may	O
also	O
be	O
a	O
clever	O
way	O
of	O
doing	O
more	O
calculations	O
than	O
normal	O
in	O
one	O
instruction	B-General_Concept
;	O
for	O
example	O
,	O
using	O
such	O
an	O
instruction	B-General_Concept
with	O
the	O
addressing	B-Language
mode	I-Language
"	O
base+index+offset	O
"	O
(	O
detailed	O
below	O
)	O
allows	O
one	O
to	O
add	O
two	O
registers	O
and	O
a	O
constant	O
together	O
in	O
one	O
instruction	B-General_Concept
and	O
store	O
the	O
result	O
in	O
a	O
third	O
register	B-General_Concept
.	O
</s>
<s>
Some	O
simple	O
addressing	B-Language
modes	I-Language
for	O
code	O
are	O
shown	O
below	O
.	O
</s>
<s>
The	O
effective	B-Language
address	I-Language
for	O
an	O
absolute	O
instruction	B-General_Concept
address	B-General_Concept
is	O
the	O
address	B-General_Concept
parameter	O
itself	O
with	O
no	O
modifications	O
.	O
</s>
<s>
The	O
effective	B-Language
address	I-Language
for	O
a	O
PC-relative	O
instruction	B-General_Concept
address	B-General_Concept
is	O
the	O
offset	B-General_Concept
parameter	O
added	O
to	O
the	O
address	B-General_Concept
of	O
the	O
next	B-General_Concept
instruction	I-General_Concept
.	O
</s>
<s>
This	O
offset	B-General_Concept
is	O
usually	O
signed	O
to	O
allow	O
reference	O
to	O
code	O
both	O
before	O
and	O
after	O
the	O
instruction	B-General_Concept
.	O
</s>
<s>
Measurements	O
of	O
actual	O
programs	O
suggest	O
that	O
an	O
8	O
or	O
10	O
bit	O
offset	B-General_Concept
is	O
large	O
enough	O
for	O
some	O
90%	O
of	O
conditional	B-General_Concept
jumps	I-General_Concept
(	O
roughly	O
±128	O
or	O
±512	O
bytes	O
)	O
.	O
</s>
<s>
Another	O
advantage	O
of	O
PC-relative	O
addressing	O
is	O
that	O
the	O
code	O
may	O
be	O
position-independent	B-Operating_System
,	O
i.e.	O
</s>
<s>
Some	O
versions	O
of	O
this	O
addressing	B-Language
mode	I-Language
may	O
be	O
conditional	O
referring	O
to	O
two	O
registers	O
(	O
"	O
jump	O
if	O
reg1	O
=	O
reg2	O
"	O
)	O
,	O
one	O
register	B-General_Concept
(	O
"	O
jump	O
unless	O
reg1	O
=	O
0	O
"	O
)	O
or	O
no	O
registers	O
,	O
implicitly	O
referring	O
to	O
some	O
previously-set	O
bit	O
in	O
the	O
status	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
The	O
effective	B-Language
address	I-Language
for	O
a	O
Register	B-General_Concept
indirect	O
instruction	B-General_Concept
is	O
the	O
address	B-General_Concept
in	O
the	O
specified	O
register	B-General_Concept
.	O
</s>
<s>
For	O
example	O
,	O
(	O
A7	O
)	O
to	O
access	O
the	O
content	O
of	O
address	B-General_Concept
register	I-General_Concept
A7	O
.	O
</s>
<s>
The	O
effect	O
is	O
to	O
transfer	O
control	O
to	O
the	O
instruction	B-General_Concept
whose	O
address	B-General_Concept
is	O
in	O
the	O
specified	O
register	B-General_Concept
.	O
</s>
<s>
Many	O
RISC	B-Architecture
machines	O
,	O
as	O
well	O
as	O
the	O
CISC	O
IBM	B-Application
System/360	I-Application
and	O
successors	O
,	O
have	O
subroutine	O
call	O
instructions	O
that	O
place	O
the	O
return	B-Language
address	I-Language
in	O
an	O
address	B-General_Concept
register	I-General_Concept
—	O
the	O
register-indirect	O
addressing	O
mode	O
is	O
used	O
to	O
return	O
from	O
that	O
subroutine	O
call	O
.	O
</s>
<s>
The	O
CPU	O
,	O
after	O
executing	O
a	O
sequential	O
instruction	B-General_Concept
,	O
immediately	O
executes	O
the	O
following	O
instruction	B-General_Concept
.	O
</s>
<s>
Sequential	O
execution	O
is	O
not	O
considered	O
to	O
be	O
an	O
addressing	B-Language
mode	I-Language
on	O
some	O
computers	O
.	O
</s>
<s>
Because	O
most	O
instructions	O
are	O
sequential	O
instructions	O
,	O
CPU	O
designers	O
often	O
add	O
features	O
that	O
deliberately	O
sacrifice	O
performance	O
on	O
the	O
other	O
instructions	O
—	O
branch	B-General_Concept
instructions	I-General_Concept
—	O
in	O
order	O
to	O
make	O
these	O
sequential	O
instructions	O
run	O
faster	O
.	O
</s>
<s>
Conditional	B-General_Concept
branches	I-General_Concept
load	O
the	O
PC	B-General_Concept
with	O
one	O
of	O
2	O
possible	O
results	O
,	O
depending	O
on	O
the	O
condition	O
—	O
most	O
CPU	O
architectures	O
use	O
some	O
other	O
addressing	B-Language
mode	I-Language
for	O
the	O
"	O
taken	O
"	O
branch	O
,	O
and	O
sequential	O
execution	O
for	O
the	O
"	O
not	O
taken	O
"	O
branch	O
.	O
</s>
<s>
Many	O
features	O
in	O
modern	O
CPUs	O
—	O
instruction	B-General_Concept
prefetch	I-General_Concept
and	O
more	O
complex	O
pipelineing	O
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
etc.	O
—	O
maintain	O
the	O
illusion	O
that	O
each	O
instruction	B-General_Concept
finishes	O
before	O
the	O
next	O
one	O
begins	O
,	O
giving	O
the	O
same	O
final	O
results	O
,	O
even	O
though	O
that	O
's	O
not	O
exactly	O
what	O
happens	O
internally	O
.	O
</s>
<s>
Each	O
"	O
basic	B-Application
block	I-Application
"	O
of	O
such	O
sequential	O
instructions	O
exhibits	O
both	O
temporal	O
and	O
spatial	O
locality	B-General_Concept
of	I-General_Concept
reference	I-General_Concept
.	O
</s>
<s>
CPUs	O
that	O
do	O
not	O
use	O
sequential	O
execution	O
with	O
a	O
program	B-General_Concept
counter	I-General_Concept
are	O
extremely	O
rare	O
.	O
</s>
<s>
In	O
some	O
CPUs	O
,	O
each	O
instruction	B-General_Concept
always	O
specifies	O
the	O
address	B-General_Concept
of	O
next	B-General_Concept
instruction	I-General_Concept
.	O
</s>
<s>
Such	O
CPUs	O
have	O
an	O
instruction	B-General_Concept
pointer	I-General_Concept
that	O
holds	O
that	O
specified	O
address	B-General_Concept
;	O
it	O
is	O
not	O
a	O
program	B-General_Concept
counter	I-General_Concept
because	O
there	O
is	O
no	O
provision	O
for	O
incrementing	O
it	O
.	O
</s>
<s>
Such	O
CPUs	O
include	O
some	O
drum	B-General_Concept
memory	I-General_Concept
computers	O
such	O
as	O
the	O
IBM	B-Device
650	I-Device
,	O
the	O
SECD	B-Application
machine	I-Application
,	O
Librascope	B-Device
LGP-30	I-Device
,	O
and	O
the	O
RTX	O
32P	O
.	O
</s>
<s>
Other	O
computing	O
architectures	O
go	O
much	O
further	O
,	O
attempting	O
to	O
bypass	O
the	O
von	O
Neumann	O
bottleneck	O
using	O
a	O
variety	O
of	O
alternatives	O
to	O
the	O
program	B-General_Concept
counter	I-General_Concept
.	O
</s>
<s>
Some	O
computer	O
architectures	O
have	O
conditional	O
instructions	O
(	O
such	O
as	O
ARM	B-Architecture
,	O
but	O
no	O
longer	O
for	O
all	O
instructions	O
in	O
64-bit	O
mode	O
)	O
or	O
conditional	O
load	O
instructions	O
(	O
such	O
as	O
x86	B-Operating_System
)	O
which	O
can	O
in	O
some	O
cases	O
make	O
conditional	B-General_Concept
branches	I-General_Concept
unnecessary	O
and	O
avoid	O
flushing	O
the	O
instruction	B-General_Concept
pipeline	I-General_Concept
.	O
</s>
<s>
An	O
instruction	B-General_Concept
such	O
as	O
a	O
'	O
compare	O
 '	O
is	O
used	O
to	O
set	O
a	O
condition	B-General_Concept
code	I-General_Concept
,	O
and	O
subsequent	O
instructions	O
include	O
a	O
test	O
on	O
that	O
condition	B-General_Concept
code	I-General_Concept
to	O
see	O
whether	O
they	O
are	O
obeyed	O
or	O
ignored	O
.	O
</s>
<s>
Skip	O
addressing	O
may	O
be	O
considered	O
a	O
special	O
kind	O
of	O
PC-relative	O
addressing	O
mode	O
with	O
a	O
fixed	O
"	O
+1	O
"	O
offset	B-General_Concept
.	O
</s>
<s>
Like	O
PC-relative	O
addressing	O
,	O
some	O
CPUs	O
have	O
versions	O
of	O
this	O
addressing	B-Language
mode	I-Language
that	O
only	O
refer	O
to	O
one	O
register	B-General_Concept
(	O
"	O
skip	O
if	O
reg1	O
=	O
0	O
"	O
)	O
or	O
no	O
registers	O
,	O
implicitly	O
referring	O
to	O
some	O
previously-set	O
bit	O
in	O
the	O
status	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
Unlike	O
all	O
other	O
conditional	B-General_Concept
branches	I-General_Concept
,	O
a	O
"	O
skip	O
"	O
instruction	B-General_Concept
never	O
needs	O
to	O
flush	O
the	O
instruction	B-General_Concept
pipeline	I-General_Concept
,	O
though	O
it	O
may	O
need	O
to	O
cause	O
the	O
next	B-General_Concept
instruction	I-General_Concept
to	O
be	O
ignored	O
.	O
</s>
<s>
Some	O
simple	O
addressing	B-Language
modes	I-Language
for	O
data	O
are	O
shown	O
below	O
.	O
</s>
<s>
This	O
"	O
addressing	B-Language
mode	I-Language
"	O
does	O
not	O
have	O
an	O
effective	B-Language
address	I-Language
and	O
is	O
not	O
considered	O
to	O
be	O
an	O
addressing	B-Language
mode	I-Language
on	O
some	O
computers	O
.	O
</s>
<s>
In	O
this	O
example	O
,	O
all	O
the	O
operands	O
are	O
in	O
registers	O
,	O
and	O
the	O
result	O
is	O
placed	O
in	O
a	O
register	B-General_Concept
.	O
</s>
<s>
The	O
offset	B-General_Concept
is	O
usually	O
a	O
signed	O
16-bit	O
value	O
(	O
though	O
the	O
80386	B-General_Concept
expanded	O
it	O
to	O
32	O
bits	O
)	O
.	O
</s>
<s>
If	O
the	O
offset	B-General_Concept
is	O
zero	O
,	O
this	O
becomes	O
an	O
example	O
of	O
register	B-General_Concept
indirect	B-Language
addressing	I-Language
;	O
the	O
effective	B-Language
address	I-Language
is	O
just	O
the	O
value	O
in	O
the	O
base	O
register	B-General_Concept
.	O
</s>
<s>
On	O
many	O
RISC	B-Architecture
machines	O
,	O
register0	O
is	O
fixed	O
at	O
the	O
value	O
zero	O
.	O
</s>
<s>
If	O
register0	O
is	O
used	O
as	O
the	O
base	O
register	B-General_Concept
,	O
this	O
becomes	O
an	O
example	O
of	O
absolute	O
addressing	O
.	O
</s>
<s>
However	O
,	O
only	O
a	O
small	O
portion	O
of	O
memory	O
can	O
be	O
accessed	O
(	O
64	O
kilobytes	O
,	O
if	O
the	O
offset	B-General_Concept
is	O
16	O
bits	O
)	O
.	O
</s>
<s>
The	O
16-bit	O
offset	B-General_Concept
may	O
seem	O
very	O
small	O
in	O
relation	O
to	O
the	O
size	O
of	O
current	O
computer	O
memories	O
(	O
which	O
is	O
why	O
the	O
80386	B-General_Concept
expanded	O
it	O
to	O
32-bit	O
)	O
.	O
</s>
<s>
It	O
could	O
be	O
worse	O
:	O
IBM	B-Application
System/360	I-Application
mainframes	O
only	O
have	O
an	O
unsigned	O
12-bit	O
offset	B-General_Concept
.	O
</s>
<s>
However	O
,	O
the	O
principle	O
of	O
locality	B-General_Concept
of	I-General_Concept
reference	I-General_Concept
applies	O
:	O
over	O
a	O
short	O
time	O
span	O
,	O
most	O
of	O
the	O
data	O
items	O
a	O
program	O
wants	O
to	O
access	O
are	O
fairly	O
close	O
to	O
each	O
other	O
.	O
</s>
<s>
This	O
addressing	B-Language
mode	I-Language
is	O
closely	O
related	O
to	O
the	O
indexed	O
absolute	O
addressing	B-Language
mode	I-Language
.	O
</s>
<s>
Within	O
a	O
subroutine	O
a	O
programmer	O
will	O
mainly	O
be	O
interested	O
in	O
the	O
parameters	O
and	O
the	O
local	O
variables	O
,	O
which	O
will	O
rarely	O
exceed	O
64	O
KB	O
,	O
for	O
which	O
one	O
base	O
register	B-General_Concept
(	O
the	O
frame	O
pointer	O
)	O
suffices	O
.	O
</s>
<s>
If	O
this	O
routine	O
is	O
a	O
class	O
method	O
in	O
an	O
object-oriented	O
language	O
,	O
then	O
a	O
second	O
base	O
register	B-General_Concept
is	O
needed	O
which	O
points	O
at	O
the	O
attributes	O
for	O
the	O
current	O
object	O
(	O
this	O
or	O
self	O
in	O
some	O
high	O
level	O
languages	O
)	O
.	O
</s>
<s>
If	O
the	O
base	O
register	B-General_Concept
contains	O
the	O
address	B-General_Concept
of	O
a	O
composite	O
type	O
(	O
a	O
record	O
or	O
structure	O
)	O
,	O
the	O
offset	B-General_Concept
can	O
be	O
used	O
to	O
select	O
a	O
field	O
from	O
that	O
record	O
(	O
most	O
records/structures	O
are	O
less	O
than	O
32	O
kB	O
in	O
size	O
)	O
.	O
</s>
<s>
This	O
"	O
addressing	B-Language
mode	I-Language
"	O
does	O
not	O
have	O
an	O
effective	B-Language
address	I-Language
,	O
and	O
is	O
not	O
considered	O
to	O
be	O
an	O
addressing	B-Language
mode	I-Language
on	O
some	O
computers	O
.	O
</s>
<s>
For	O
example	O
,	O
move.l	O
#$FEEDABBA	O
,	O
D0	O
to	O
move	O
the	O
immediate	O
hex	O
value	O
of	O
"	O
FEEDABBA	O
"	O
into	O
register	B-General_Concept
D0	O
.	O
</s>
<s>
Instead	O
of	O
using	O
an	O
operand	O
from	O
memory	O
,	O
the	O
value	O
of	O
the	O
operand	O
is	O
held	O
within	O
the	O
instruction	B-General_Concept
itself	O
.	O
</s>
<s>
On	O
the	O
DEC	B-Device
VAX	I-Device
machine	O
,	O
the	O
literal	O
operand	O
sizes	O
could	O
be	O
6	O
,	O
8	O
,	O
16	O
,	O
or	O
32	O
bits	O
long	O
.	O
</s>
<s>
Andrew	O
Tanenbaum	O
showed	O
that	O
98%	O
of	O
all	O
the	O
constants	O
in	O
a	O
program	O
would	O
fit	O
in	O
13	O
bits	O
(	O
see	O
RISC	B-Architecture
design	O
philosophy	O
)	O
.	O
</s>
<s>
The	O
implied	O
addressing	B-Language
mode	I-Language
,	O
also	O
called	O
the	O
implicit	O
addressing	B-Language
mode	I-Language
(	O
x86	B-Language
assembly	I-Language
language	I-Language
)	O
,	O
does	O
not	O
explicitly	O
specify	O
an	O
effective	B-Language
address	I-Language
for	O
either	O
the	O
source	O
or	O
the	O
destination	O
(	O
or	O
sometimes	O
both	O
)	O
.	O
</s>
<s>
Either	O
the	O
source	O
(	O
if	O
any	O
)	O
or	O
destination	O
effective	B-Language
address	I-Language
(	O
or	O
sometimes	O
both	O
)	O
is	O
implied	O
by	O
the	O
opcode	O
.	O
</s>
<s>
Such	O
computers	O
typically	O
had	O
only	O
a	O
single	O
register	B-General_Concept
in	O
which	O
arithmetic	O
could	O
be	O
performed	O
—	O
the	O
accumulator	B-General_Concept
.	O
</s>
<s>
Such	O
accumulator	B-General_Concept
machines	I-General_Concept
implicitly	O
reference	O
that	O
accumulator	B-General_Concept
in	O
almost	O
every	O
instruction	B-General_Concept
.	O
</s>
<s>
For	O
example	O
,	O
the	O
operation	O
< a := b + c; > can be done using the sequence < load b; add c; store a; >	O
--	O
the	O
destination	O
(	O
the	O
accumulator	B-General_Concept
)	O
is	O
implied	O
in	O
every	O
"	O
load	O
"	O
and	O
"	O
add	O
"	O
instruction	B-General_Concept
;	O
the	O
source	O
(	O
the	O
accumulator	B-General_Concept
)	O
is	O
implied	O
in	O
every	O
"	O
store	O
"	O
instruction	B-General_Concept
.	O
</s>
<s>
Later	O
computers	O
generally	O
had	O
more	O
than	O
one	O
general-purpose	O
register	B-General_Concept
or	O
RAM	O
location	O
which	O
could	O
be	O
the	O
source	O
or	O
destination	O
or	O
both	O
for	O
arithmetic	O
—	O
and	O
so	O
later	O
computers	O
need	O
some	O
other	O
addressing	B-Language
mode	I-Language
to	O
specify	O
the	O
source	O
and	O
destination	O
of	O
arithmetic	O
.	O
</s>
<s>
Among	O
the	O
x86	B-Operating_System
instructions	O
,	O
some	O
use	O
implicit	O
registers	O
for	O
one	O
of	O
the	O
operands	O
or	O
results	O
(	O
multiplication	O
,	O
division	O
,	O
counting	O
conditional	B-General_Concept
jump	I-General_Concept
)	O
.	O
</s>
<s>
Many	O
computers	O
(	O
such	O
as	O
x86	B-Operating_System
and	O
AVR	O
)	O
have	O
one	O
special-purpose	O
register	B-General_Concept
called	O
the	O
stack	O
pointer	O
which	O
is	O
implicitly	O
incremented	O
or	O
decremented	O
when	O
pushing	O
or	O
popping	O
data	O
from	O
the	O
stack	O
,	O
and	O
the	O
source	O
or	O
destination	O
effective	B-Language
address	I-Language
is	O
(	O
implicitly	O
)	O
the	O
address	B-General_Concept
stored	O
in	O
that	O
stack	O
pointer	O
.	O
</s>
<s>
Many	O
32-bit	O
computers	O
(	O
such	O
as	O
68000	O
,	O
ARM	B-Architecture
,	O
or	O
PowerPC	O
)	O
have	O
more	O
than	O
one	O
register	B-General_Concept
which	O
could	O
be	O
used	O
as	O
a	O
stack	O
pointer	O
—	O
and	O
so	O
use	O
the	O
"	O
register	B-General_Concept
autoincrement	O
indirect	O
"	O
addressing	B-Language
mode	I-Language
to	O
specify	O
which	O
of	O
those	O
registers	O
should	O
be	O
used	O
when	O
pushing	O
or	O
popping	O
data	O
from	O
a	O
stack	O
.	O
</s>
<s>
IBM/390	B-Device
and	O
Intel	O
Pentium	O
)	O
contain	O
some	O
instructions	O
with	O
implicit	O
operands	O
in	O
order	O
to	O
maintain	O
backwards	O
compatibility	O
with	O
earlier	O
designs	O
.	O
</s>
<s>
implicitly	O
specify	O
the	O
special	O
register	B-General_Concept
that	O
holds	O
those	O
bits	O
.	O
</s>
<s>
This	O
simplifies	O
the	O
hardware	O
necessary	O
to	O
trap	O
those	O
instructions	O
in	O
order	O
to	O
meet	O
the	O
Popek	B-Architecture
and	I-Architecture
Goldberg	I-Architecture
virtualization	I-Architecture
requirements	I-Architecture
—	O
on	O
such	O
a	O
system	O
,	O
the	O
trap	O
logic	O
does	O
not	O
need	O
to	O
look	O
at	O
any	O
operand	O
(	O
or	O
at	O
the	O
final	O
effective	B-Language
address	I-Language
)	O
,	O
but	O
only	O
at	O
the	O
opcode	O
.	O
</s>
<s>
A	O
few	O
CPUs	O
have	O
been	O
designed	O
where	O
every	O
operand	O
is	O
always	O
implicitly	O
specified	O
in	O
every	O
instruction	B-General_Concept
--	O
zero-operand	O
CPUs	O
.	O
</s>
<s>
This	O
requires	O
space	O
in	O
an	O
instruction	B-General_Concept
for	O
quite	O
a	O
large	O
address	B-General_Concept
.	O
</s>
<s>
It	O
is	O
often	O
available	O
on	O
CISC	O
machines	O
which	O
have	O
variable-length	O
instructions	O
,	O
such	O
as	O
x86	B-Operating_System
.	O
</s>
<s>
Some	O
RISC	B-Architecture
machines	O
have	O
a	O
special	O
Load	O
Upper	O
Literal	O
instruction	B-General_Concept
which	O
places	O
a	O
16	O
-	O
or	O
20-bit	O
constant	O
in	O
the	O
top	O
half	O
of	O
a	O
register	B-General_Concept
.	O
</s>
<s>
That	O
can	O
then	O
be	O
used	O
as	O
the	O
base	O
register	B-General_Concept
in	O
a	O
base-plus-offset	O
addressing	B-Language
mode	I-Language
which	O
supplies	O
the	O
low-order	O
16	O
or	O
12	O
bits	O
.	O
</s>
<s>
The	O
combination	O
allows	O
a	O
full	O
32-bit	O
address	B-General_Concept
.	O
</s>
<s>
This	O
also	O
requires	O
space	O
in	O
an	O
instruction	B-General_Concept
for	O
quite	O
a	O
large	O
address	B-General_Concept
.	O
</s>
<s>
The	O
address	B-General_Concept
could	O
be	O
the	O
start	O
of	O
an	O
array	O
or	O
vector	O
,	O
and	O
the	O
index	O
could	O
select	O
the	O
particular	O
array	B-Data_Structure
element	I-Data_Structure
required	O
.	O
</s>
<s>
The	O
processor	O
may	O
scale	O
the	O
index	B-General_Concept
register	I-General_Concept
to	O
allow	O
for	O
the	O
size	B-Data_Structure
of	I-Data_Structure
each	I-Data_Structure
array	I-Data_Structure
element	I-Data_Structure
.	O
</s>
<s>
Note	O
that	O
this	O
is	O
more	O
or	O
less	O
the	O
same	O
as	O
base-plus-offset	O
addressing	B-Language
mode	I-Language
,	O
except	O
that	O
the	O
offset	B-General_Concept
in	O
this	O
case	O
is	O
large	O
enough	O
to	O
address	B-General_Concept
any	O
memory	B-General_Concept
location	I-General_Concept
.	O
</s>
<s>
Within	O
a	O
subroutine	O
,	O
a	O
programmer	O
may	O
define	O
a	O
string	O
as	O
a	O
local	O
constant	O
or	O
a	O
static	B-General_Concept
variable	I-General_Concept
.	O
</s>
<s>
The	O
address	B-General_Concept
of	O
the	O
string	O
is	O
stored	O
in	O
the	O
literal	O
address	B-General_Concept
in	O
the	O
instruction	B-General_Concept
.	O
</s>
<s>
The	O
offset	B-General_Concept
—	O
which	O
character	O
of	O
the	O
string	O
to	O
use	O
on	O
this	O
iteration	O
of	O
a	O
loop	O
—	O
is	O
stored	O
in	O
the	O
index	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
A	O
programmer	O
may	O
define	O
several	O
large	O
arrays	O
as	O
globals	O
or	O
as	O
class	B-Application
variables	I-Application
.	O
</s>
<s>
The	O
start	O
of	O
the	O
array	O
is	O
stored	O
in	O
the	O
literal	O
address	B-General_Concept
(	O
perhaps	O
modified	O
at	O
program-load	O
time	O
by	O
a	O
relocating	B-Library
loader	I-Library
)	O
of	O
the	O
instruction	B-General_Concept
that	O
references	O
it	O
.	O
</s>
<s>
The	O
offset	B-General_Concept
—	O
which	O
item	O
from	O
the	O
array	O
to	O
use	O
on	O
this	O
iteration	O
of	O
a	O
loop	O
—	O
is	O
stored	O
in	O
the	O
index	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
Often	O
the	O
instructions	O
in	O
a	O
loop	O
re-use	O
the	O
same	O
register	B-General_Concept
for	O
the	O
loop	O
counter	O
and	O
the	O
offsets	B-General_Concept
of	O
several	O
arrays	O
.	O
</s>
<s>
The	O
base	O
register	B-General_Concept
could	O
contain	O
the	O
start	O
address	B-General_Concept
of	O
an	O
array	O
or	O
vector	O
,	O
and	O
the	O
index	O
could	O
select	O
the	O
particular	O
array	B-Data_Structure
element	I-Data_Structure
required	O
.	O
</s>
<s>
The	O
processor	O
may	O
scale	O
the	O
index	B-General_Concept
register	I-General_Concept
to	O
allow	O
for	O
the	O
size	B-Data_Structure
of	I-Data_Structure
each	I-Data_Structure
array	I-Data_Structure
element	I-Data_Structure
.	O
</s>
<s>
The	O
base	O
register	B-General_Concept
could	O
contain	O
the	O
start	O
address	B-General_Concept
of	O
an	O
array	O
or	O
vector	O
of	O
records	O
,	O
the	O
index	O
could	O
select	O
the	O
particular	O
record	O
required	O
,	O
and	O
the	O
offset	B-General_Concept
could	O
select	O
a	O
field	O
within	O
that	O
record	O
.	O
</s>
<s>
The	O
processor	O
may	O
scale	O
the	O
index	B-General_Concept
register	I-General_Concept
to	O
allow	O
for	O
the	O
size	B-Data_Structure
of	I-Data_Structure
each	I-Data_Structure
array	I-Data_Structure
element	I-Data_Structure
.	O
</s>
<s>
The	O
base	O
register	B-General_Concept
could	O
contain	O
the	O
start	O
address	B-General_Concept
of	O
an	O
array	O
or	O
vector	B-Data_Structure
data	I-Data_Structure
structure	I-Data_Structure
,	O
and	O
the	O
index	O
could	O
contain	O
the	O
offset	B-General_Concept
of	O
the	O
one	O
particular	O
array	B-Data_Structure
element	I-Data_Structure
required	O
.	O
</s>
<s>
This	O
addressing	B-Language
mode	I-Language
dynamically	O
scales	O
the	O
value	O
in	O
the	O
index	B-General_Concept
register	I-General_Concept
to	O
allow	O
for	O
the	O
size	B-Data_Structure
of	I-Data_Structure
each	I-Data_Structure
array	I-Data_Structure
element	I-Data_Structure
,	O
e.g.	O
</s>
<s>
if	O
the	O
array	B-Data_Structure
elements	I-Data_Structure
are	O
double	O
precision	O
floating-point	O
numbers	O
occupying	O
8	O
bytes	O
each	O
then	O
the	O
value	O
in	O
the	O
index	B-General_Concept
register	I-General_Concept
is	O
multiplied	O
by	O
8	O
before	O
being	O
used	O
in	O
the	O
effective	B-Language
address	I-Language
calculation	O
.	O
</s>
<s>
A	O
few	O
computers	O
have	O
this	O
as	O
a	O
distinct	O
addressing	B-Language
mode	I-Language
.	O
</s>
<s>
Many	O
computers	O
just	O
use	O
base	O
plus	O
offset	B-General_Concept
with	O
an	O
offset	B-General_Concept
value	O
of	O
0	O
.	O
</s>
<s>
After	O
determining	O
the	O
effective	B-Language
address	I-Language
,	O
the	O
value	O
in	O
the	O
base	O
register	B-General_Concept
is	O
incremented	O
by	O
the	O
size	O
of	O
the	O
data	O
item	O
that	O
is	O
to	O
be	O
accessed	O
.	O
</s>
<s>
For	O
example	O
,	O
(	O
A7	O
)	O
+	O
would	O
access	O
the	O
content	O
of	O
the	O
address	B-General_Concept
register	I-General_Concept
A7	O
,	O
then	O
increase	O
the	O
address	B-General_Concept
pointer	O
of	O
A7	O
by	O
1	O
(	O
usually	O
1	O
word	O
)	O
.	O
</s>
<s>
Within	O
a	O
loop	O
,	O
this	O
addressing	B-Language
mode	I-Language
can	O
be	O
used	O
to	O
step	O
through	O
all	O
the	O
elements	O
of	O
an	O
array	O
or	O
vector	O
.	O
</s>
<s>
This	O
addressing	B-Language
mode	I-Language
has	O
a	O
side	O
effect	O
in	O
that	O
the	O
base	O
register	B-General_Concept
is	O
altered	O
.	O
</s>
<s>
page	B-General_Concept
fault	I-General_Concept
,	O
bus	B-General_Concept
error	I-General_Concept
,	O
address	B-General_Concept
error	O
)	O
leading	O
to	O
an	O
interrupt	O
,	O
then	O
restarting	O
the	O
instruction	B-General_Concept
becomes	O
much	O
more	O
problematic	O
since	O
one	O
or	O
more	O
registers	O
may	O
need	O
to	O
be	O
set	O
back	O
to	O
the	O
state	O
they	O
were	O
in	O
before	O
the	O
instruction	B-General_Concept
originally	O
started	O
.	O
</s>
<s>
There	O
have	O
been	O
at	O
least	O
two	O
computer	O
architectures	O
which	O
have	O
had	O
implementation	O
problems	O
with	O
regard	O
to	O
recovery	O
from	O
interrupts	O
when	O
this	O
addressing	B-Language
mode	I-Language
is	O
used	O
:	O
</s>
<s>
Motorola	O
68000	O
(	O
address	B-General_Concept
is	O
represented	O
in	O
24	O
bits	O
)	O
.	O
</s>
<s>
Could	O
have	O
one	O
or	O
two	O
autoincrement	O
register	B-General_Concept
operands	O
.	O
</s>
<s>
The	O
68010+	O
resolved	O
the	O
problem	O
by	O
saving	O
the	O
processor	O
's	O
internal	O
state	O
on	O
bus	B-General_Concept
or	O
address	B-General_Concept
errors	O
.	O
</s>
<s>
DEC	B-Device
VAX	I-Device
.	O
</s>
<s>
Could	O
have	O
up	O
to	O
6	O
autoincrement	O
register	B-General_Concept
operands	O
.	O
</s>
<s>
Each	O
operand	O
access	O
could	O
cause	O
two	O
page	B-General_Concept
faults	I-General_Concept
(	O
if	O
operands	O
happened	O
to	O
straddle	O
a	O
page	O
boundary	O
)	O
.	O
</s>
<s>
Of	O
course	O
the	O
instruction	B-General_Concept
itself	O
could	O
be	O
over	O
50	O
bytes	O
long	O
and	O
might	O
straddle	O
a	O
page	O
boundary	O
as	O
well	O
!	O
</s>
<s>
Before	O
determining	O
the	O
effective	B-Language
address	I-Language
,	O
the	O
value	O
in	O
the	O
base	O
register	B-General_Concept
is	O
decremented	O
by	O
the	O
size	O
of	O
the	O
data	O
item	O
which	O
is	O
to	O
be	O
accessed	O
.	O
</s>
<s>
Within	O
a	O
loop	O
,	O
this	O
addressing	B-Language
mode	I-Language
can	O
be	O
used	O
to	O
step	O
backwards	O
through	O
all	O
the	O
elements	O
of	O
an	O
array	O
or	O
vector	O
.	O
</s>
<s>
A	O
stack	O
can	O
be	O
implemented	O
by	O
using	O
this	O
mode	O
in	O
conjunction	O
with	O
the	O
previous	O
addressing	B-Language
mode	I-Language
(	O
autoincrement	O
)	O
.	O
</s>
<s>
See	O
the	O
discussion	O
of	O
side-effects	O
under	O
the	O
autoincrement	O
addressing	B-Language
mode	I-Language
.	O
</s>
<s>
Any	O
of	O
the	O
addressing	B-Language
modes	I-Language
mentioned	O
in	O
this	O
article	O
could	O
have	O
an	O
extra	O
bit	O
to	O
indicate	O
indirect	B-Language
addressing	I-Language
,	O
i.e.	O
</s>
<s>
the	O
address	B-General_Concept
calculated	O
using	O
some	O
mode	O
is	O
in	O
fact	O
the	O
address	B-General_Concept
of	O
a	O
location	O
(	O
typically	O
a	O
complete	O
word	O
)	O
which	O
contains	O
the	O
actual	O
effective	B-Language
address	I-Language
.	O
</s>
<s>
Indirect	B-Language
addressing	I-Language
may	O
be	O
used	O
for	O
code	O
or	O
data	O
.	O
</s>
<s>
Indirect	B-Language
addressing	I-Language
does	O
carry	O
a	O
performance	O
penalty	O
due	O
to	O
the	O
extra	O
memory	O
access	O
involved	O
.	O
</s>
<s>
DEC	B-Device
PDP-8	I-Device
,	O
Data	B-Device
General	I-Device
Nova	I-Device
)	O
had	O
only	O
a	O
few	O
registers	O
and	O
only	O
a	O
limited	O
direct	B-Language
addressing	I-Language
range	O
(	O
8	O
bits	O
)	O
.	O
</s>
<s>
Hence	O
the	O
use	O
of	O
memory	O
indirect	B-Language
addressing	I-Language
was	O
almost	O
the	O
only	O
way	O
of	O
referring	O
to	O
any	O
significant	O
amount	O
of	O
memory	O
.	O
</s>
<s>
Half	O
of	O
the	O
DEC	B-Device
PDP-11	I-Device
'	O
s	O
eight	O
addressing	B-Language
modes	I-Language
are	O
deferred	O
.	O
</s>
<s>
Register	B-General_Concept
deferred	O
@Rn	O
is	O
the	O
same	O
as	O
register	B-General_Concept
indirect	O
as	O
defined	O
above	O
.	O
</s>
<s>
Predecrement	O
deferred	O
@-(Rn )	O
,	O
postincrement	O
deferred	O
@(Rn )	O
+	O
,	O
and	O
indexed	O
deferred	O
@nn(Rn )	O
modes	O
point	O
to	O
addresses	O
in	O
memory	O
which	O
are	O
read	O
to	O
find	O
the	O
address	B-General_Concept
of	O
the	O
parameter	O
.	O
</s>
<s>
The	O
PDP-11	B-Device
'	O
s	O
deferred	O
modes	O
,	O
when	O
combined	O
with	O
the	O
program	B-General_Concept
counter	I-General_Concept
,	O
provide	O
its	O
absolute	O
and	O
PC-relative	O
addressing	O
modes	O
.	O
</s>
<s>
The	O
PC-relative	O
addressing	O
mode	O
can	O
be	O
used	O
to	O
load	O
a	O
register	B-General_Concept
with	O
a	O
value	O
stored	O
in	O
program	O
memory	O
a	O
short	O
distance	O
away	O
from	O
the	O
current	B-General_Concept
instruction	I-General_Concept
.	O
</s>
<s>
It	O
can	O
be	O
seen	O
as	O
a	O
special	O
case	O
of	O
the	O
"	O
base	O
plus	O
offset	B-General_Concept
"	O
addressing	B-Language
mode	I-Language
,	O
one	O
that	O
selects	O
the	O
program	B-General_Concept
counter	I-General_Concept
(	O
PC	B-General_Concept
)	O
as	O
the	O
"	O
base	O
register	B-General_Concept
"	O
.	O
</s>
<s>
There	O
are	O
a	O
few	O
CPUs	O
that	O
support	O
PC-relative	O
data	O
references	O
.	O
</s>
<s>
The	O
MOS	B-General_Concept
6502	I-General_Concept
and	O
its	O
derivatives	O
used	O
relative	B-General_Concept
addressing	I-General_Concept
for	O
all	O
branch	B-General_Concept
instructions	I-General_Concept
.	O
</s>
<s>
Only	O
these	O
instructions	O
used	O
this	O
mode	O
,	O
jumps	O
used	O
a	O
variety	O
of	O
other	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
The	O
x86-64	B-Device
architecture	O
and	O
the	O
64-bit	O
ARMv8-A	O
architecture	O
have	O
PC-relative	O
addressing	O
modes	O
,	O
called	O
"	O
RIP-relative	O
"	O
in	O
x86-64	B-Device
and	O
"	O
literal	O
"	O
in	O
ARMv8-A	O
.	O
</s>
<s>
The	O
Motorola	B-Device
6809	I-Device
also	O
supports	O
a	O
PC-relative	O
addressing	O
mode	O
.	O
</s>
<s>
The	O
PDP-11	B-Device
architecture	I-Device
,	O
the	O
VAX	B-Device
architecture	O
,	O
and	O
the	O
32-bit	O
ARM	B-Architecture
architectures	I-Architecture
support	O
PC-relative	O
addressing	O
by	O
having	O
the	O
PC	B-General_Concept
in	O
the	O
register	B-General_Concept
file	O
.	O
</s>
<s>
The	O
IBM	B-Device
z/Architecture	I-Device
includes	O
specific	O
instructions	O
,	O
e.g.	O
,	O
Load	O
Relative	O
Long	O
,	O
with	O
PC-relative	O
addressing	O
if	O
the	O
General-Instructions-Extension	O
Facility	O
is	O
active	O
.	O
</s>
<s>
When	O
this	O
addressing	B-Language
mode	I-Language
is	O
used	O
,	O
the	O
compiler	B-Language
typically	O
places	O
the	O
constants	O
in	O
a	O
literal	B-Application
pool	I-Application
immediately	O
before	O
or	O
immediately	O
after	O
the	O
subroutine	O
that	O
uses	O
them	O
,	O
to	O
prevent	O
accidentally	O
executing	O
those	O
constants	O
as	O
instructions	O
.	O
</s>
<s>
This	O
addressing	B-Language
mode	I-Language
,	O
which	O
always	O
fetches	O
data	O
from	O
memory	O
or	O
stores	O
data	O
to	O
memory	O
and	O
then	O
sequentially	O
falls	O
through	O
to	O
execute	O
the	O
next	B-General_Concept
instruction	I-General_Concept
(	O
the	O
effective	B-Language
address	I-Language
points	O
to	O
data	O
)	O
,	O
should	O
not	O
be	O
confused	O
with	O
"	O
PC-relative	O
branch	O
"	O
which	O
does	O
not	O
fetch	O
data	O
from	O
or	O
store	O
data	O
to	O
memory	O
,	O
but	O
instead	O
branches	O
to	O
some	O
other	O
instruction	B-General_Concept
at	O
the	O
given	O
offset	B-General_Concept
(	O
the	O
effective	B-Language
address	I-Language
points	O
to	O
an	O
executable	O
instruction	B-General_Concept
)	O
.	O
</s>
<s>
The	O
addressing	B-Language
modes	I-Language
listed	O
here	O
were	O
used	O
in	O
the	O
1950	O
–	O
1980	O
period	O
,	O
but	O
are	O
no	O
longer	O
available	O
on	O
most	O
current	O
computers	O
.	O
</s>
<s>
This	O
list	O
is	O
by	O
no	O
means	O
complete	O
;	O
there	O
have	O
been	O
many	O
other	O
interesting	O
and	O
peculiar	O
addressing	B-Language
modes	I-Language
used	O
from	O
time	O
to	O
time	O
,	O
e.g.	O
</s>
<s>
absolute-minus-logical-OR	O
of	O
two	O
or	O
three	O
index	B-General_Concept
registers	I-General_Concept
.	O
</s>
<s>
If	O
the	O
word	O
size	O
is	O
larger	O
than	O
the	O
address	B-General_Concept
,	O
then	O
the	O
word	O
referenced	O
for	O
memory-indirect	O
addressing	O
could	O
itself	O
have	O
an	O
indirect	O
flag	O
set	O
to	O
indicate	O
another	O
memory	O
indirect	O
cycle	O
.	O
</s>
<s>
Care	O
is	O
needed	O
to	O
ensure	O
that	O
a	O
chain	O
of	O
indirect	O
addresses	O
does	O
not	O
refer	O
to	O
itself	O
;	O
if	O
it	O
does	O
,	O
one	O
can	O
get	O
an	O
infinite	B-Algorithm
loop	I-Algorithm
while	O
trying	O
to	O
resolve	O
an	O
address	B-General_Concept
.	O
</s>
<s>
The	O
IBM	B-Device
1620	I-Device
,	O
the	O
Data	B-Device
General	I-Device
Nova	I-Device
,	O
the	O
HP	B-Device
2100	I-Device
series	O
,	O
and	O
the	O
NAR	B-Application
2	I-Application
each	O
have	O
such	O
a	O
multi-level	O
memory	O
indirect	O
,	O
and	O
could	O
enter	O
such	O
an	O
infinite	O
address	B-General_Concept
calculation	O
loop	O
.	O
</s>
<s>
The	O
memory	O
indirect	B-Language
addressing	I-Language
mode	O
on	O
the	O
Nova	O
influenced	O
the	O
invention	O
of	O
indirect	O
threaded	O
code	O
.	O
</s>
<s>
The	O
DEC	B-Device
PDP-10	I-Device
computer	O
with	O
18-bit	B-General_Concept
addresses	O
and	O
36-bit	O
words	O
allowed	O
multi-level	O
indirect	B-Language
addressing	I-Language
with	O
the	O
possibility	O
of	O
using	O
an	O
index	B-General_Concept
register	I-General_Concept
at	O
each	O
stage	O
as	O
well	O
.	O
</s>
<s>
The	O
priority	O
interrupt	O
system	O
was	O
queried	O
before	O
decoding	O
of	O
every	O
address	B-General_Concept
word	O
.	O
</s>
<s>
So	O
,	O
an	O
indirect	B-Language
address	I-Language
loop	O
would	O
not	O
prevent	O
execution	O
of	O
device	O
service	O
routines	O
,	O
including	O
any	O
preemptive	O
multitasking	O
scheduler	O
's	O
time-slice	O
expiration	O
handler	O
.	O
</s>
<s>
A	O
looping	O
instruction	B-General_Concept
would	O
be	O
treated	O
like	O
any	O
other	O
compute-bound	O
job	O
.	O
</s>
<s>
Although	O
on	O
some	O
early	O
computers	O
there	O
were	O
register	B-General_Concept
addresses	O
at	O
the	O
high	O
end	O
of	O
the	O
address	B-General_Concept
range	O
,	O
e.g.	O
,	O
IBM	B-Device
650	I-Device
,	O
IBM	B-Device
7070	I-Device
,	O
the	O
trend	O
has	O
been	O
to	O
use	O
only	O
register	B-General_Concept
address	B-General_Concept
at	O
the	O
low	O
end	O
and	O
to	O
use	O
only	O
the	O
first	O
8	O
or	O
16	O
words	O
of	O
memory	O
(	O
e.g.	O
</s>
<s>
ICL	B-Device
1900	I-Device
,	O
DEC	B-Device
PDP-10	I-Device
)	O
.	O
</s>
<s>
This	O
meant	O
that	O
there	O
was	O
no	O
need	O
for	O
a	O
separate	O
"	O
add	O
register	B-General_Concept
to	O
register	B-General_Concept
"	O
instruction	B-General_Concept
–	O
one	O
could	O
just	O
use	O
the	O
"	O
add	O
memory	O
to	O
register	B-General_Concept
"	O
instruction	B-General_Concept
.	O
</s>
<s>
In	O
the	O
case	O
of	O
early	O
models	O
of	O
the	O
PDP-10	B-Device
,	O
which	O
did	O
not	O
have	O
any	O
cache	O
memory	O
,	O
a	O
tight	O
inner	O
loop	O
loaded	O
into	O
the	O
first	O
few	O
words	O
of	O
memory	O
(	O
where	O
the	O
fast	O
registers	O
were	O
addressable	O
if	O
installed	O
)	O
ran	O
much	O
faster	O
than	O
it	O
would	O
have	O
in	O
magnetic	O
core	O
memory	O
.	O
</s>
<s>
Later	O
models	O
of	O
the	O
DEC	B-Device
PDP-11	I-Device
series	O
mapped	O
the	O
registers	O
onto	O
addresses	O
in	O
the	O
input/output	O
area	O
,	O
but	O
this	O
was	O
primarily	O
intended	O
to	O
allow	O
remote	O
diagnostics	O
.	O
</s>
<s>
The	O
DEC	B-Device
PDP-8	I-Device
minicomputer	O
had	O
eight	O
special	O
locations	O
(	O
at	O
addresses	O
8	O
through	O
15	O
)	O
.	O
</s>
<s>
When	O
accessed	O
via	O
memory	O
indirect	B-Language
addressing	I-Language
,	O
these	O
locations	O
would	O
automatically	O
increment	O
prior	O
to	O
use	O
.	O
</s>
<s>
This	O
made	O
it	O
easy	O
to	O
step	O
through	O
memory	O
in	O
a	O
loop	O
without	O
needing	O
to	O
use	O
the	O
accumulator	B-General_Concept
to	O
increment	O
the	O
address	B-General_Concept
.	O
</s>
<s>
The	O
Data	B-Device
General	I-Device
Nova	I-Device
minicomputer	O
had	O
16	O
special	O
memory	B-General_Concept
locations	I-General_Concept
at	O
addresses	O
16	O
through	O
31	O
.	O
</s>
<s>
When	O
accessed	O
via	O
memory	O
indirect	B-Language
addressing	I-Language
,	O
16	O
through	O
23	O
would	O
automatically	O
increment	O
before	O
use	O
,	O
and	O
24	O
through	O
31	O
would	O
automatically	O
decrement	O
before	O
use	O
.	O
</s>
<s>
The	O
Data	B-Device
General	I-Device
Nova	I-Device
,	O
Motorola	B-Device
6800	I-Device
family	O
,	O
and	O
MOS	B-General_Concept
Technology	I-General_Concept
6502	I-General_Concept
family	O
of	O
processors	O
had	O
very	O
few	O
internal	O
registers	O
.	O
</s>
<s>
The	O
initial	O
256	O
bytes	O
of	O
memory	O
( $0000	O
–	O
$00FF	O
;	O
a.k.a.	O
,	O
page	O
"	O
0	O
"	O
)	O
could	O
be	O
accessed	O
using	O
a	O
one-byte	O
absolute	O
or	O
indexed	O
memory	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
This	O
reduced	O
instruction	B-General_Concept
execution	O
time	O
by	O
one	O
clock	O
cycle	O
and	O
instruction	B-General_Concept
length	O
by	O
one	O
byte	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
the	O
zero	O
page	O
was	O
used	O
similarly	O
to	O
a	O
register	B-General_Concept
file	O
.	O
</s>
<s>
The	O
zero	O
page	O
address	B-Language
mode	I-Language
was	O
enhanced	O
in	O
several	O
late	O
model	O
8-bit	O
processors	O
,	O
including	O
the	O
WDC	B-General_Concept
65816	I-General_Concept
,	O
the	O
CSG	B-General_Concept
65CE02	I-General_Concept
,	O
and	O
the	O
Motorola	B-Device
6809	I-Device
.	O
</s>
<s>
The	O
new	O
mode	O
,	O
known	O
as	O
"	O
direct	O
page	O
"	O
addressing	O
,	O
added	O
the	O
ability	O
to	O
move	O
the	O
256-byte	O
zero	O
page	O
memory	O
window	O
from	O
the	O
start	O
of	O
memory	O
(	O
offset	B-General_Concept
address	B-General_Concept
$0000	O
)	O
to	O
a	O
new	O
location	O
within	O
the	O
first	O
64KB	O
of	O
memory	O
.	O
</s>
<s>
The	O
CSG	B-General_Concept
65CE02	I-General_Concept
allowed	O
the	O
direct	O
page	O
to	O
be	O
moved	O
to	O
any	O
256-byte	O
boundary	O
within	O
the	O
first	O
64KB	O
of	O
memory	O
by	O
storing	O
an	O
8-bit	O
offset	B-General_Concept
value	O
in	O
the	O
new	O
base	O
page	O
(	O
B	O
)	O
register	B-General_Concept
.	O
</s>
<s>
The	O
Motorola	B-Device
6809	I-Device
could	O
do	O
the	O
same	O
with	O
its	O
direct	O
page	O
(	O
DP	O
)	O
register	B-General_Concept
.	O
</s>
<s>
The	O
WDC	B-General_Concept
65816	I-General_Concept
went	O
a	O
step	O
further	O
and	O
allowed	O
the	O
direct	O
page	O
to	O
be	O
moved	O
to	O
any	O
location	O
within	O
the	O
first	O
64KB	O
of	O
memory	O
by	O
storing	O
a	O
16-bit	O
offset	B-General_Concept
value	O
in	O
the	O
new	O
direct	O
(	O
D	O
)	O
register	B-General_Concept
.	O
</s>
<s>
As	O
a	O
result	O
,	O
a	O
greater	O
number	O
of	O
programs	O
were	O
able	O
to	O
utilize	O
the	O
enhanced	O
direct	O
page	O
addressing	B-Language
mode	I-Language
versus	O
legacy	O
processors	O
that	O
only	O
included	O
the	O
zero	O
page	O
addressing	B-Language
mode	I-Language
.	O
</s>
<s>
This	O
is	O
similar	O
to	O
scaled	O
index	O
addressing	O
,	O
except	O
that	O
the	O
instruction	B-General_Concept
has	O
two	O
extra	O
operands	O
(	O
typically	O
constants	O
)	O
,	O
and	O
the	O
hardware	O
checks	O
that	O
the	O
index	O
value	O
is	O
between	O
these	O
bounds	O
.	O
</s>
<s>
Some	O
computers	O
had	O
special	O
indirect	B-Language
addressing	I-Language
modes	O
for	O
subfields	O
within	O
words	O
.	O
</s>
<s>
The	O
GE/Honeywell	B-Device
600	I-Device
series	I-Device
character	O
addressing	O
indirect	B-Language
word	I-Language
specified	O
either	O
6-bit	O
or	O
9-bit	O
character	O
fields	O
within	O
its	O
36-bit	O
word	O
.	O
</s>
<s>
The	O
DEC	B-Device
PDP-10	I-Device
,	O
also	O
36-bit	O
,	O
had	O
special	O
instructions	O
which	O
allowed	O
memory	O
to	O
be	O
treated	O
as	O
a	O
sequence	O
of	O
fixed-size	O
bit	O
fields	O
or	O
bytes	O
of	O
any	O
size	O
from	O
1	O
bit	O
to	O
36	O
bits	O
.	O
</s>
<s>
A	O
one-word	O
sequence	O
descriptor	O
in	O
memory	O
,	O
called	O
a	O
"	O
byte	O
pointer	O
"	O
,	O
held	O
the	O
current	O
word	O
address	B-General_Concept
within	O
the	O
sequence	O
,	O
a	O
bit	O
position	O
within	O
a	O
word	O
,	O
and	O
the	O
size	O
of	O
each	O
byte	O
.	O
</s>
<s>
Implementations	O
of	O
C	B-Language
had	O
to	O
use	O
four	O
9-bit	O
bytes	O
per	O
word	O
,	O
since	O
the	O
'	O
malloc	O
 '	O
function	O
in	O
C	B-Language
assumes	O
that	O
the	O
size	O
of	O
an	O
int	O
is	O
some	O
multiple	O
of	O
the	O
size	O
of	O
a	O
char	O
;	O
the	O
actual	O
multiple	O
is	O
determined	O
by	O
the	O
system-dependent	O
compile-time	O
operator	O
sizeof	B-Language
.	O
</s>
<s>
The	O
Elliott	B-Device
503	I-Device
,	O
the	O
Elliott	B-Device
803	I-Device
,	O
and	O
the	O
Apollo	B-Application
Guidance	I-Application
Computer	I-Application
only	O
used	O
absolute	O
addressing	O
,	O
and	O
did	O
not	O
have	O
any	O
index	B-General_Concept
registers	I-General_Concept
.	O
</s>
<s>
Thus	O
,	O
indirect	O
jumps	O
,	O
or	O
jumps	O
through	O
registers	O
,	O
were	O
not	O
supported	O
in	O
the	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Instead	O
,	O
it	O
could	O
be	O
instructed	O
to	O
add	O
the	O
contents	O
of	O
the	O
current	O
memory	O
word	O
to	O
the	O
next	B-General_Concept
instruction	I-General_Concept
.	O
</s>
<s>
Adding	O
a	O
small	O
value	O
to	O
the	O
next	B-General_Concept
instruction	I-General_Concept
to	O
be	O
executed	O
could	O
,	O
for	O
example	O
,	O
change	O
a	O
JUMP	O
0	O
into	O
a	O
JUMP	O
20	O
,	O
thus	O
creating	O
the	O
effect	O
of	O
an	O
indexed	O
jump	O
.	O
</s>
<s>
Note	O
that	O
the	O
instruction	B-General_Concept
is	O
modified	O
on-the-fly	O
and	O
remains	O
unchanged	O
in	O
memory	O
,	O
i.e.	O
</s>
<s>
it	O
is	O
not	O
self-modifying	B-Application
code	I-Application
.	O
</s>
<s>
If	O
the	O
value	O
being	O
added	O
to	O
the	O
next	B-General_Concept
instruction	I-General_Concept
was	O
large	O
enough	O
,	O
it	O
could	O
modify	O
the	O
opcode	O
of	O
that	O
instruction	B-General_Concept
as	O
well	O
as	O
or	O
instead	O
of	O
the	O
address	B-General_Concept
.	O
</s>
