<s>
The	O
address	B-General_Concept
generation	I-General_Concept
unit	I-General_Concept
(	O
AGU	B-General_Concept
)	O
,	O
sometimes	O
also	O
called	O
address	B-General_Concept
computation	I-General_Concept
unit	I-General_Concept
(	O
ACU	O
)	O
,	O
is	O
an	O
execution	B-General_Concept
unit	I-General_Concept
inside	O
central	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
(	O
CPUs	O
)	O
that	O
calculates	O
addresses	B-General_Concept
used	O
by	O
the	O
CPU	O
to	O
access	O
main	O
memory	O
.	O
</s>
<s>
By	O
having	O
address	O
calculations	O
handled	O
by	O
separate	O
circuitry	O
that	O
operates	O
in	O
parallel	O
with	O
the	O
rest	O
of	O
the	O
CPU	O
,	O
the	O
number	O
of	O
CPU	B-General_Concept
cycles	I-General_Concept
required	O
for	O
executing	O
various	O
machine	B-Language
instructions	I-Language
can	O
be	O
reduced	O
,	O
bringing	O
performance	O
improvements	O
.	O
</s>
<s>
While	O
performing	O
various	O
operations	O
,	O
CPUs	O
need	O
to	O
calculate	O
memory	O
addresses	B-General_Concept
required	O
for	O
fetching	O
data	O
from	O
the	O
memory	O
;	O
for	O
example	O
,	O
in-memory	O
positions	O
of	O
array	B-Data_Structure
elements	I-Data_Structure
must	O
be	O
calculated	O
before	O
the	O
CPU	O
can	O
fetch	O
the	O
data	O
from	O
actual	O
memory	B-General_Concept
locations	I-General_Concept
.	O
</s>
<s>
Often	O
,	O
calculating	O
a	O
memory	B-General_Concept
address	I-General_Concept
involves	O
more	O
than	O
one	O
general-purpose	O
machine	B-Language
instruction	I-Language
,	O
which	O
do	O
not	O
necessarily	O
decode	B-General_Concept
and	I-General_Concept
execute	I-General_Concept
quickly	O
.	O
</s>
<s>
By	O
incorporating	O
an	O
AGU	B-General_Concept
into	O
a	O
CPU	O
design	O
,	O
together	O
with	O
introducing	O
specialized	O
instructions	O
that	O
use	O
the	O
AGU	B-General_Concept
,	O
various	O
address-generation	O
calculations	O
can	O
be	O
offloaded	O
from	O
the	O
rest	O
of	O
the	O
CPU	O
,	O
and	O
can	O
often	O
be	O
executed	O
quickly	O
in	O
a	O
single	O
CPU	B-General_Concept
cycle	I-General_Concept
.	O
</s>
<s>
Capabilities	O
of	O
an	O
AGU	B-General_Concept
depend	O
on	O
a	O
particular	O
CPU	O
and	O
its	O
architecture	B-General_Concept
.	O
</s>
<s>
Thus	O
,	O
some	O
AGUs	B-General_Concept
implement	O
and	O
expose	O
more	O
address-calculation	O
operations	O
,	O
while	O
some	O
also	O
include	O
more	O
advanced	O
specialized	O
instructions	O
that	O
can	O
operate	O
on	O
multiple	O
operands	O
at	O
a	O
time	O
.	O
</s>
<s>
Furthermore	O
,	O
some	O
CPU	O
architectures	O
include	O
multiple	O
AGUs	B-General_Concept
so	O
more	O
than	O
one	O
address-calculation	O
operation	O
can	O
be	O
executed	O
simultaneously	O
,	O
bringing	O
further	O
performance	O
improvements	O
by	O
capitalizing	O
on	O
the	O
superscalar	B-General_Concept
nature	O
of	O
advanced	O
CPU	O
designs	O
.	O
</s>
<s>
For	O
example	O
,	O
Intel	O
incorporates	O
multiple	O
AGUs	B-General_Concept
into	O
its	O
Sandy	B-Device
Bridge	I-Device
and	O
Haswell	B-Device
microarchitectures	I-Device
,	O
which	O
increase	O
bandwidth	O
of	O
the	O
CPU	O
memory	O
subsystem	O
by	O
allowing	O
multiple	O
memory-access	O
instructions	O
to	O
be	O
executed	O
in	O
parallel	O
.	O
</s>
