<s>
In	O
digital	O
electronics	O
,	O
an	O
address	B-Device
decoder	I-Device
is	O
a	O
binary	O
decoder	O
that	O
has	O
two	O
or	O
more	O
inputs	O
for	O
address	B-Architecture
bits	O
and	O
one	O
or	O
more	O
outputs	O
for	O
device	O
selection	O
signals	O
.	O
</s>
<s>
When	O
the	O
address	B-Architecture
for	O
a	O
particular	O
device	O
appears	O
on	O
the	O
address	B-Architecture
inputs	O
,	O
the	O
decoder	O
asserts	O
the	O
selection	O
output	O
for	O
that	O
device	O
.	O
</s>
<s>
A	O
dedicated	O
,	O
single-output	O
address	B-Device
decoder	I-Device
may	O
be	O
incorporated	O
into	O
each	O
device	O
on	O
an	O
address	B-Architecture
bus	I-Architecture
,	O
or	O
a	O
single	O
address	B-Device
decoder	I-Device
may	O
serve	O
multiple	O
devices	O
.	O
</s>
<s>
A	O
single	O
address	B-Device
decoder	I-Device
with	O
n	O
address	B-Architecture
input	O
bits	O
can	O
serve	O
up	O
to	O
2n	O
devices	O
.	O
</s>
<s>
Several	O
members	O
of	O
the	O
7400	O
series	O
of	O
integrated	O
circuits	O
can	O
be	O
used	O
as	O
address	B-Device
decoders	I-Device
.	O
</s>
<s>
For	O
example	O
,	O
when	O
used	O
as	O
an	O
address	B-Device
decoder	I-Device
,	O
the	O
74154	O
provides	O
four	O
address	B-Architecture
inputs	O
and	O
sixteen	O
(	O
i.e.	O
,	O
24	O
)	O
device	O
selector	O
outputs	O
.	O
</s>
<s>
An	O
address	B-Device
decoder	I-Device
is	O
a	O
particular	O
use	O
of	O
a	O
binary	O
decoder	O
circuit	O
known	O
as	O
a	O
"	O
demultiplexer	O
"	O
or	O
"	O
demux	O
"	O
(	O
the	O
74154	O
is	O
commonly	O
called	O
a	O
"	O
4-to-16	O
demultiplexer	O
"	O
)	O
,	O
which	O
has	O
many	O
other	O
uses	O
besides	O
address	B-Architecture
decoding	O
.	O
</s>
<s>
Address	B-Device
decoders	I-Device
are	O
fundamental	O
building	O
blocks	O
for	O
systems	O
that	O
use	O
buses	B-General_Concept
.	O
</s>
<s>
They	O
are	O
represented	O
in	O
all	O
integrated	O
circuit	O
families	O
and	O
processes	O
and	O
in	O
all	O
standard	O
FPGA	B-Architecture
and	O
ASIC	O
libraries	O
.	O
</s>
<s>
An	O
address	B-Device
decoder	I-Device
is	O
a	O
commonly	O
used	O
component	O
in	O
microelectronics	O
that	O
is	O
used	O
to	O
select	O
memory	O
cells	O
in	O
randomly	O
addressable	O
memory	O
devices	O
.	O
</s>
<s>
The	O
address	B-Device
decoder	I-Device
is	O
connected	O
to	O
an	O
address	B-Architecture
bus	I-Architecture
and	O
reads	O
the	O
address	B-Architecture
created	O
there	O
.	O
</s>
<s>
Using	O
a	O
special	O
switching	O
logic	O
,	O
it	O
uses	O
this	O
address	B-Architecture
to	O
calculate	O
which	O
memory	O
cell	O
is	O
to	O
be	O
accessed	O
.	O
</s>
<s>
In	O
dynamic	O
memories	O
(	O
DRAM	O
)	O
,	O
there	O
are	O
row	O
and	O
column	O
select	O
lines	O
on	O
the	O
memory	O
matrix	O
,	O
which	O
are	O
controlled	O
by	O
address	B-Device
decoders	I-Device
integrated	O
in	O
the	O
chip	O
.	O
</s>
<s>
An	O
address	B-Device
decoder	I-Device
is	O
also	O
used	O
to	O
select	O
the	O
appropriate	O
one	O
of	O
multiple	O
memory	O
modules	O
or	O
memory	O
chips	O
when	O
a	O
particular	O
address	B-Architecture
is	O
provided	O
by	O
the	O
processor	O
system	O
's	O
address	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
The	O
address	B-Device
decoder	I-Device
uses	O
the	O
different	O
combinatorial	O
logic	O
to	O
place	O
the	O
memory	O
modules	O
or	O
chips	O
in	O
the	O
address	B-Architecture
space	O
of	O
a	O
processor	O
.	O
</s>
<s>
The	O
memory	O
modules	O
often	O
have	O
a	O
smaller	O
capacity	O
than	O
the	O
address	B-Architecture
space	O
.	O
</s>
<s>
It	O
must	O
be	O
ensured	O
that	O
they	O
differ	O
in	O
the	O
address	B-Architecture
range	O
.	O
</s>
