<s>
Ada	B-General_Concept
Lovelace	I-General_Concept
,	O
also	O
referred	O
to	O
simply	O
as	O
Lovelace	O
,	O
is	O
the	O
codename	O
for	O
a	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
(	O
GPU	B-Architecture
)	O
microarchitecture	O
developed	O
by	O
Nvidia	O
as	O
the	O
successor	O
to	O
the	O
Ampere	B-General_Concept
architecture	O
,	O
officially	O
announced	O
on	O
September	O
20	O
,	O
2022	O
.	O
</s>
<s>
It	O
is	O
named	O
after	O
English	O
mathematician	O
Ada	B-General_Concept
Lovelace	I-General_Concept
who	O
is	O
often	O
regarded	O
as	O
the	O
first	O
computer	B-Application
programmer	I-Application
and	O
is	O
the	O
first	O
architecture	O
to	O
include	O
both	O
a	O
first	O
and	O
last	O
name	O
.	O
</s>
<s>
Nvidia	O
announced	O
the	O
architecture	O
along	O
with	O
the	O
new	O
GeForce	B-Device
40	I-Device
series	I-Device
consumer	O
GPUs	B-Architecture
and	O
the	O
RTX	B-Algorithm
6000	O
Ada	O
Generation	O
pro	O
workstation	O
graphics	O
card	O
.	O
</s>
<s>
The	O
new	O
GPUs	B-Architecture
were	O
revealed	O
to	O
use	O
TSMC	O
's	O
new	O
5	B-Algorithm
nm	I-Algorithm
"	O
4N	B-Algorithm
"	O
process	O
which	O
offers	O
increased	O
efficiency	O
over	O
the	O
previous	O
Samsung	B-Application
8	B-Algorithm
nm	I-Algorithm
and	O
TSMC	O
N7	B-Algorithm
processes	O
used	O
by	O
Nvidia	O
for	O
its	O
last	O
generation	O
Ampere	B-General_Concept
architecture	O
.	O
</s>
<s>
The	O
Ada	B-General_Concept
Lovelace	I-General_Concept
architecture	O
follows	O
on	O
from	O
the	O
Ampere	B-General_Concept
architecture	O
that	O
was	O
released	O
in	O
2020	O
.	O
</s>
<s>
The	O
Ada	B-General_Concept
Lovelace	I-General_Concept
architecture	O
was	O
announced	O
by	O
Nvidia	O
CEO	O
Jensen	O
Huang	O
during	O
a	O
GTC	O
2022	O
keynote	O
on	O
September	O
20	O
,	O
2022	O
with	O
the	O
architecture	O
powering	O
Nvidia	O
's	O
GPUs	B-Architecture
for	O
gaming	O
,	O
workstations	O
and	O
datacenters	O
.	O
</s>
<s>
Architectural	O
improvements	O
of	O
the	O
Ada	B-General_Concept
Lovelace	I-General_Concept
architecture	O
include	O
the	O
following	O
:	O
</s>
<s>
128	O
CUDA	B-Architecture
cores	O
are	O
included	O
in	O
each	O
SM	O
.	O
</s>
<s>
The	O
RTX	B-Device
4090	I-Device
features	O
128	O
RT	B-Algorithm
cores	I-Algorithm
compared	O
to	O
the	O
84	O
in	O
the	O
previous	O
generation	O
RTX	B-Algorithm
3090	O
Ti	O
.	O
</s>
<s>
These	O
128	O
RT	B-Algorithm
cores	I-Algorithm
can	O
provide	O
up	O
to	O
191	O
TFLOPS	O
of	O
compute	O
with	O
1.49	O
TFLOPS	O
per	O
RT	O
core	O
.	O
</s>
<s>
Lovelace	O
's	O
new	O
fourth-generation	O
Tensor	B-Device
cores	O
enable	O
the	O
AI	O
technology	O
used	O
in	O
DLSS	O
3	O
's	O
frame	O
generation	O
techniques	O
.	O
</s>
<s>
Much	O
like	O
Ampere	B-General_Concept
,	O
each	O
SM	O
contains	O
4	O
Tensor	B-Device
cores	O
but	O
Lovelace	O
contains	O
a	O
greater	O
number	O
of	O
Tensor	B-Device
cores	O
overall	O
given	O
its	O
increased	O
number	O
of	O
SMs	O
.	O
</s>
<s>
There	O
is	O
a	O
significant	O
increase	O
in	O
clock	O
speeds	O
with	O
the	O
Lovelace	O
architecture	O
with	O
the	O
RTX	B-Device
4090	I-Device
's	O
base	O
clock	O
speed	O
being	O
higher	O
than	O
the	O
boost	O
clock	O
speed	O
of	O
the	O
RTX	B-Algorithm
3090	O
Ti	O
.	O
</s>
<s>
The	O
fully	O
enabled	O
AD102	O
Lovelace	O
die	O
features	O
96MB	O
of	O
L2	O
cache	O
,	O
a	O
16x	O
increase	O
from	O
the	O
6MB	O
in	O
the	O
Ampere-based	O
GA102	O
die	O
.	O
</s>
<s>
The	O
GPU	B-Architecture
having	O
quick	O
access	O
to	O
a	O
high	O
amount	O
of	O
L2	O
cache	O
benefits	O
complex	O
operations	O
like	O
ray	O
tracing	O
compared	O
to	O
the	O
GPU	B-Architecture
seeking	O
data	O
from	O
the	O
GDDR	O
video	O
memory	O
which	O
is	O
slower	O
.	O
</s>
<s>
GDDR6X	O
memory	O
features	O
on	O
the	O
desktop	O
GeForce	B-Device
RTX	I-Device
40	I-Device
series	I-Device
while	O
the	O
more	O
energy-efficient	O
GDDR6	O
memory	O
is	O
used	O
on	O
its	O
corresponding	O
mobile	O
versions	O
and	O
on	O
RTX	B-Algorithm
A6000	O
workstation	O
GPUs	B-Architecture
.	O
</s>
<s>
The	O
Ada	B-General_Concept
Lovelace	I-General_Concept
architecture	O
is	O
able	O
to	O
use	O
lower	O
voltages	O
compared	O
to	O
its	O
predecessor	O
.	O
</s>
<s>
Nvidia	O
claims	O
a	O
2x	O
performance	O
increase	O
for	O
the	O
RTX	B-Device
4090	I-Device
at	O
the	O
same	O
450W	O
used	O
by	O
the	O
previous	O
generation	O
flagship	O
RTX	B-Algorithm
3090	O
Ti	O
.	O
</s>
<s>
Increased	O
power	O
effiency	O
can	O
be	O
attributed	O
in	O
part	O
to	O
the	O
smaller	O
fabrication	B-Architecture
node	I-Architecture
used	O
by	O
the	O
Lovelace	O
architecture	O
.	O
</s>
<s>
The	O
Ada	B-General_Concept
Lovelace	I-General_Concept
architecture	O
is	O
fabricated	O
on	O
TSMC	O
's	O
cutting-edge	O
4N	B-Algorithm
process	O
,	O
a	O
custom	O
designed	O
process	O
node	O
for	O
Nvidia	O
.	O
</s>
<s>
The	O
previous	O
generation	O
Ampere	B-General_Concept
architecture	O
used	O
Samsung	B-Application
's	O
8nm-based	O
8N	B-Algorithm
process	O
node	O
from	O
2018	O
,	O
which	O
was	O
two	O
years	O
old	O
by	O
the	O
time	O
of	O
Ampere	B-General_Concept
's	O
launch	O
.	O
</s>
<s>
The	O
Lovelace	O
architecture	O
utilizes	O
the	O
new	O
8th	O
generation	O
Nvidia	B-General_Concept
NVENC	I-General_Concept
video	O
encoder	O
and	O
the	O
7th	O
generation	O
NVDEC	O
video	O
decoder	O
introduced	O
by	O
Ampere	B-General_Concept
returns	O
.	O
</s>
<s>
NVENC	B-General_Concept
AV1	B-Application
hardware	O
encoding	O
with	O
support	O
for	O
up	O
to	O
8K	O
resolution	O
at	O
60FPS	O
in	O
10-bit	O
color	O
is	O
added	O
,	O
enabling	O
higher	O
video	O
fidelity	O
at	O
lower	O
bit	O
rates	O
compared	O
to	O
the	O
H.264	B-Application
and	O
H.265	B-Algorithm
codecs	O
.	O
</s>
<s>
Nvidia	O
claims	O
that	O
its	O
NVENC	B-General_Concept
AV1	B-Application
encoder	O
featured	O
in	O
the	O
Lovelace	O
architecture	O
is	O
40%	O
more	O
efficient	O
than	O
the	O
H.264	B-Application
encoder	O
in	O
the	O
Ampere	B-General_Concept
architecture	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
Lovelace	O
GPUs	B-Architecture
would	O
be	O
limited	O
by	O
DisplayPort	O
1.4a	O
'	O
s	O
supported	O
refresh	O
rates	O
despite	O
the	O
GPU	B-Architecture
's	O
performace	O
being	O
able	O
to	O
reach	O
higher	O
frame	O
rates	O
.	O
</s>
<s>
Intel	O
's	O
Arc	B-Device
GPUs	B-Architecture
that	O
also	O
released	O
in	O
October	O
2022	O
included	O
DisplayPort	O
2.0	O
.	O
</s>
<s>
Model	O
Launch	O
Launch	O
MSRP	O
(	O
USD	O
)	O
Code	O
name(s )	O
rowspan	O
=	O
"	O
2	O
"	O
Die	O
size	O
Core	O
config	O
SM	O
count	O
Cache	O
Clock	O
speeds	O
Fillrate	B-General_Concept
Memory	O
Processing	O
power	O
(	O
TFLOPS	O
)	O
TBP	B-General_Concept
L1	O
L2	O
Core	O
clock	O
(	O
MHz	O
)	O
Memory	O
(	O
MHz	O
)	O
Pixel	B-Algorithm
(	O
Gpx/s	O
)	O
Texture	O
(	O
Gtex/s	O
)	O
Type	O
Size	O
Bandwidth	O
(	O
GB/s	O
)	O
Bus	O
width	O
Half	O
precision(boost )	O
Single	O
precision(boost )	O
Double	O
precision(boost )	O
Tensorcompute[sparse]	O
Unknown	O
$	O
AD104-	O
??	O
</s>
