<s>
Accelerated	B-Architecture
Graphics	I-Architecture
Port	I-Architecture
(	O
AGP	O
)	O
is	O
a	B-General_Concept
parallel	O
expansion	B-Device
card	I-Device
standard	O
,	O
designed	O
for	O
attaching	O
a	B-General_Concept
video	B-Device
card	I-Device
to	O
a	B-General_Concept
computer	O
system	O
to	O
assist	O
in	O
the	O
acceleration	O
of	O
3D	O
computer	O
graphics	O
.	O
</s>
<s>
It	O
was	O
originally	O
designed	O
as	O
a	B-General_Concept
successor	O
to	O
PCI-type	O
connections	O
for	O
video	B-Device
cards	I-Device
.	O
</s>
<s>
Since	O
2004	O
,	O
AGP	O
was	O
progressively	O
phased	O
out	O
in	O
favor	O
of	O
PCI	B-Protocol
Express	O
(	O
PCIe	O
)	O
,	O
which	O
is	O
serial	B-Protocol
,	O
as	O
opposed	O
to	O
parallel	O
;	O
by	O
mid-2008	O
,	O
PCI	B-Protocol
Express	O
cards	O
dominated	O
the	O
market	O
and	O
only	O
a	B-General_Concept
few	O
AGP	O
models	O
were	O
available	O
,	O
with	O
GPU	O
manufacturers	O
and	O
add-in	O
board	O
partners	O
eventually	O
dropping	O
support	O
for	O
the	O
interface	O
in	O
favor	O
of	O
PCI	B-Protocol
Express	O
.	O
</s>
<s>
AGP	O
is	O
a	B-General_Concept
superset	O
of	O
the	O
PCI	B-Protocol
standard	O
,	O
designed	O
to	O
overcome	O
PCI	B-Protocol
's	O
limitations	O
in	O
serving	O
the	O
requirements	O
of	O
the	O
era	O
's	O
high-performance	O
graphics	B-Device
cards	I-Device
.	O
</s>
<s>
The	O
primary	O
advantage	O
of	O
AGP	O
is	O
that	O
it	O
does	O
n't	O
share	O
the	O
PCI	B-Protocol
bus	I-Protocol
,	O
providing	O
a	B-General_Concept
dedicated	O
,	O
point-to-point	B-Architecture
pathway	O
between	O
the	O
expansion	O
slot(s )	O
and	O
the	O
motherboard	O
chipset	O
.	O
</s>
<s>
The	O
second	O
major	O
change	O
is	O
the	O
use	O
of	O
split	O
transactions	O
,	O
wherein	O
the	O
address	B-Architecture
and	O
data	O
phases	O
are	O
separated	O
.	O
</s>
<s>
The	O
card	O
may	O
send	O
many	O
address	B-Architecture
phases	O
so	O
the	O
host	O
can	O
process	O
them	O
in	O
order	O
,	O
avoiding	O
any	O
long	O
delays	O
caused	O
by	O
the	O
bus	B-General_Concept
being	O
idle	O
during	O
read	O
operations	O
.	O
</s>
<s>
Third	O
,	O
PCI	B-Protocol
bus	I-Protocol
handshaking	O
is	O
simplified	O
.	O
</s>
<s>
Unlike	O
PCI	B-Protocol
bus	I-Protocol
transactions	O
whose	O
length	O
is	O
negotiated	O
on	O
a	B-General_Concept
cycle-by-cycle	O
basis	O
using	O
the	O
FRAME#	O
and	O
STOP#	O
signals	O
,	O
AGP	O
transfers	O
are	O
always	O
a	B-General_Concept
multiple	O
of	O
8	O
bytes	O
long	O
,	O
with	O
the	O
total	O
length	O
included	O
in	O
the	O
request	O
.	O
</s>
<s>
Finally	O
,	O
AGP	O
allows	O
(	O
mandatory	O
only	O
in	O
AGP	O
3.0	O
)	O
sideband	B-Architecture
addressing	I-Architecture
,	O
meaning	O
that	O
the	O
address	B-Architecture
and	O
data	B-General_Concept
buses	I-General_Concept
are	O
separated	O
so	O
the	O
address	B-Architecture
phase	O
does	O
not	O
use	O
the	O
main	O
address/data	O
(	O
AD	O
)	O
lines	O
at	O
all	O
.	O
</s>
<s>
This	O
is	O
done	O
by	O
adding	O
an	O
extra	O
8-bit	O
"	O
SideBand	O
Address	B-Architecture
"	O
bus	B-General_Concept
over	O
which	O
the	O
graphics	B-Device
controller	I-Device
can	O
issue	O
new	O
AGP	O
requests	O
while	O
other	O
AGP	O
data	O
is	O
flowing	O
over	O
the	O
main	O
32	O
address/data	O
(	O
AD	O
)	O
lines	O
.	O
</s>
<s>
This	O
great	O
improvement	O
in	O
memory	O
read	O
performance	O
makes	O
it	O
practical	O
for	O
an	O
AGP	O
card	O
to	O
read	O
textures	O
directly	O
from	O
system	O
RAM	O
,	O
while	O
a	B-General_Concept
PCI	B-Protocol
graphics	B-Device
card	I-Device
must	O
copy	O
it	O
from	O
system	O
RAM	O
to	O
the	O
card	O
's	O
video	O
memory	O
.	O
</s>
<s>
System	O
memory	O
is	O
made	O
available	O
using	O
the	O
graphics	B-General_Concept
address	I-General_Concept
remapping	I-General_Concept
table	I-General_Concept
(	O
GART	O
)	O
,	O
which	O
apportions	O
main	O
memory	O
as	O
needed	O
for	O
texture	O
storage	O
.	O
</s>
<s>
The	O
maximum	O
amount	O
of	O
system	O
memory	O
available	O
to	O
AGP	O
is	O
defined	O
as	O
the	O
AGP	O
aperture	B-General_Concept
.	O
</s>
<s>
The	O
AGP	B-Architecture
slot	I-Architecture
first	O
appeared	O
on	O
x86-compatible	O
system	O
boards	O
based	O
on	O
Socket	B-General_Concept
7	I-General_Concept
Intel	B-General_Concept
P5	I-General_Concept
Pentium	B-General_Concept
and	O
Slot	B-Device
1	I-Device
P6	B-Device
Pentium	B-General_Concept
II	I-General_Concept
processors	O
.	O
</s>
<s>
Intel	O
introduced	O
AGP	O
support	O
with	O
the	O
i440LX	O
Slot	B-Device
1	I-Device
chipset	O
on	O
August	O
26	O
,	O
1997	O
,	O
and	O
a	B-General_Concept
flood	O
of	O
products	O
followed	O
from	O
all	O
the	O
major	O
system	O
board	O
vendors	O
.	O
</s>
<s>
The	O
first	O
Socket	B-General_Concept
7	I-General_Concept
chipsets	O
to	O
support	O
AGP	O
were	O
the	O
VIA	B-Device
Apollo	I-Device
VP3	I-Device
,	O
SiS	O
5591/5592	O
,	O
and	O
the	O
ALI	O
Aladdin	O
V	O
.	O
Intel	O
never	O
released	O
an	O
AGP-equipped	O
Socket	B-General_Concept
7	I-General_Concept
chipset	O
.	O
</s>
<s>
FIC	O
demonstrated	O
the	O
first	O
Socket	B-General_Concept
7	I-General_Concept
AGP	O
system	O
board	O
in	O
November	O
1997	O
as	O
the	O
FIC	O
PA-2012	O
based	O
on	O
the	O
VIA	B-Device
Apollo	I-Device
VP3	I-Device
chipset	O
,	O
followed	O
very	O
quickly	O
by	O
the	O
EPoX	O
P55-VP3	O
also	O
based	O
on	O
the	O
VIA	O
VP3	O
chipset	O
which	O
was	O
first	O
to	O
market	O
.	O
</s>
<s>
Early	O
video	O
chipsets	O
featuring	O
AGP	O
support	O
included	O
the	O
Rendition	O
Vérité	O
V2200	O
,	O
3dfx	O
Voodoo	O
Banshee	O
,	O
Nvidia	B-Device
RIVA	I-Device
128	I-Device
,	O
3Dlabs	O
PERMEDIA	O
2	O
,	O
Intel	B-General_Concept
i740	I-General_Concept
,	O
ATI	B-Device
Rage	I-Device
series	I-Device
,	O
Matrox	B-Application
Millennium	O
II	O
,	O
and	O
S3	B-Device
ViRGE	I-Device
GX/2	I-Device
.	O
</s>
<s>
Some	O
early	O
AGP	O
boards	O
used	O
graphics	O
processors	O
built	O
around	O
PCI	B-Protocol
and	O
were	O
simply	O
bridged	O
to	O
AGP	O
.	O
</s>
<s>
This	O
resulted	O
in	O
the	O
cards	O
benefiting	O
little	O
from	O
the	O
new	O
bus	B-General_Concept
,	O
with	O
the	O
only	O
improvement	O
used	O
being	O
the	O
66MHz	O
bus	B-General_Concept
clock	O
,	O
with	O
its	O
resulting	O
doubled	O
bandwidth	O
over	O
PCI	B-Protocol
,	O
and	O
bus	B-General_Concept
exclusivity	O
.	O
</s>
<s>
Examples	O
of	O
such	O
cards	O
were	O
the	O
Voodoo	O
Banshee	O
,	O
Vérité	O
V2200	O
,	O
Millennium	O
II	O
,	O
and	O
S3	B-Device
ViRGE	I-Device
GX/2	I-Device
.	O
</s>
<s>
Intel	O
's	O
i740	B-General_Concept
was	O
explicitly	O
designed	O
to	O
exploit	O
the	O
new	O
AGP	O
feature	O
set	O
;	O
in	O
fact	O
it	O
was	O
designed	O
to	O
texture	O
only	O
from	O
AGP	O
memory	O
,	O
making	O
PCI	B-Protocol
versions	O
of	O
the	O
board	O
difficult	O
to	O
implement	O
(	O
local	O
board	O
RAM	O
had	O
to	O
emulate	O
AGP	O
memory	O
.	O
)	O
</s>
<s>
Microsoft	O
first	O
introduced	O
AGP	O
support	O
into	O
Windows	B-Application
95	I-Application
OEM	O
Service	O
Release	O
2	O
(	O
OSR2	O
version	O
1111	O
or	O
950B	O
)	O
via	O
the	O
USB	O
SUPPLEMENT	O
to	O
OSR2	O
patch	O
.	O
</s>
<s>
After	O
applying	O
the	O
patch	O
the	O
Windows	B-Application
95	I-Application
system	O
became	O
Windows	B-Application
95	I-Application
version	O
4.00.950	O
B	O
.	O
</s>
<s>
The	O
first	O
Windows	O
NT-based	O
operating	O
system	O
to	O
receive	O
AGP	O
support	O
was	O
Windows	B-Device
NT	I-Device
4.0	I-Device
with	O
Service	O
Pack	O
3	O
,	O
introduced	O
in	O
1997	O
.	O
</s>
<s>
Linux	B-Application
support	O
for	O
AGP	O
enhanced	O
fast	O
data	O
transfers	O
was	O
first	O
added	O
in	O
1999	O
with	O
the	O
implementation	O
of	O
the	O
AGPgart	B-General_Concept
kernel	O
module	O
.	O
</s>
<s>
With	O
the	O
increasing	O
adoption	O
of	O
PCIe	O
,	O
graphics	B-Device
cards	I-Device
manufacturers	O
continued	O
to	O
produce	O
AGP	O
cards	O
as	O
the	O
standard	O
became	O
obsolete	O
.	O
</s>
<s>
As	O
GPUs	O
began	O
to	O
be	O
designed	O
to	O
connect	O
to	O
PCIe	O
,	O
an	O
additional	O
PCIe-to-AGP	O
bridge-chip	O
was	O
required	O
to	O
create	O
an	O
AGP-compatible	O
graphics	B-Device
card	I-Device
.	O
</s>
<s>
The	O
inclusion	O
of	O
a	B-General_Concept
bridge	O
,	O
and	O
the	O
need	O
for	O
a	B-General_Concept
separate	O
AGP	O
card	O
design	O
,	O
incurred	O
additional	O
board	O
costs	O
.	O
</s>
<s>
In	O
2009	O
AGP	O
cards	O
from	O
Nvidia	O
had	O
a	B-General_Concept
ceiling	O
of	O
the	O
GeForce	O
7	O
Series	O
.	O
</s>
<s>
included	O
the	O
Radeon	O
HD	O
2400	O
,	O
3450	O
,	O
3650	O
,	O
3850	O
,	O
4350	B-Device
,	I-Device
4650	I-Device
,	I-Device
and	I-Device
4670	I-Device
.	O
</s>
<s>
There	O
were	O
many	O
problems	O
with	O
the	O
AMD	O
Catalyst	O
11.2	O
-	O
11.6	O
AGP	O
hotfix	O
drivers	O
under	O
Windows	O
7	O
with	O
the	O
HD	O
4000	O
series	O
AGP	O
video	B-Device
cards	I-Device
;	O
use	O
of	O
10.12	O
or	O
11.1	O
AGP	O
hotfix	O
drivers	O
is	O
the	O
recommended	O
workaround	O
.	O
</s>
<s>
By	O
2010	O
,	O
no	O
new	O
motherboard	O
chipsets	O
supported	O
AGP	O
and	O
few	O
new	O
motherboards	O
had	O
AGP	B-Architecture
slots	I-Architecture
,	O
however	O
some	O
continued	O
to	O
be	O
produced	O
with	O
older	O
AGP-supporting	O
chipsets	O
.	O
</s>
<s>
Possible	O
future	O
removal	O
of	O
support	O
for	O
AGP	O
from	O
open	O
source	O
Linux	B-Application
kernel	O
drivers	O
was	O
considered	O
in	O
2020	O
.	O
</s>
<s>
AGP	O
version	O
3.5	O
is	O
only	O
publicly	O
mentioned	O
by	O
Microsoft	O
under	O
Universal	O
Accelerated	B-Architecture
Graphics	I-Architecture
Port	I-Architecture
(	O
UAGP	O
)	O
,	O
which	O
specifies	O
mandatory	O
supports	O
of	O
extra	O
registers	O
once	O
marked	O
optional	O
under	O
AGP	O
3.0	O
.	O
</s>
<s>
An	O
official	O
extension	O
for	O
cards	O
that	O
required	O
more	O
electrical	O
power	O
,	O
with	O
a	B-General_Concept
longer	O
slot	O
with	O
additional	O
pins	O
for	O
that	O
purpose	O
.	O
</s>
<s>
AGP	O
Pro	O
cards	O
were	O
usually	O
workstation-class	O
cards	O
used	O
to	O
accelerate	O
professional	O
computer-aided	B-Application
design	I-Application
applications	O
employed	O
in	O
the	O
fields	O
of	O
architecture	O
,	O
machining	O
,	O
engineering	O
,	O
simulations	O
,	O
and	O
similar	O
fields	O
.	O
</s>
<s>
A	B-General_Concept
64-bit	B-Device
channel	O
was	O
once	O
proposed	O
as	O
an	O
optional	O
standard	O
for	O
AGP	O
3.0	O
in	O
draft	O
documents	O
,	O
but	O
it	O
was	O
dropped	O
in	O
the	O
final	O
version	O
of	O
the	O
standard	O
.	O
</s>
<s>
The	O
standard	O
allows	O
64-bit	B-Device
transfer	O
for	O
AGP8×	O
reads	O
,	O
writes	O
,	O
and	O
fast	O
writes	O
;	O
32-bit	O
transfer	O
for	O
PCI	B-Protocol
operations	O
.	O
</s>
<s>
A	B-General_Concept
number	O
of	O
non-standard	O
variations	O
of	O
the	O
AGP	O
interface	O
have	O
been	O
produced	O
by	O
manufacturers	O
.	O
</s>
<s>
AGP	O
Express	O
Not	O
a	B-General_Concept
true	O
AGP	O
interface	O
,	O
but	O
allows	O
an	O
AGP	O
card	O
to	O
be	O
connected	O
over	O
the	O
legacy	O
PCI	B-Protocol
bus	I-Protocol
on	O
a	B-General_Concept
PCI	B-Protocol
Express	O
motherboard	O
.	O
</s>
<s>
It	O
is	O
a	B-General_Concept
technology	O
used	O
on	O
motherboards	O
made	O
by	O
ECS	O
,	O
intended	O
to	O
allow	O
an	O
existing	O
AGP	O
card	O
to	O
be	O
used	O
in	O
a	B-General_Concept
new	O
motherboard	O
instead	O
of	O
requiring	O
a	B-General_Concept
PCIe	O
card	O
to	O
be	O
obtained	O
(	O
since	O
the	O
introduction	O
of	O
PCIe	O
graphics	B-Device
cards	I-Device
few	O
motherboards	O
provide	O
AGP	B-Architecture
slots	I-Architecture
)	O
.	O
</s>
<s>
An	O
"	O
AGP	O
Express	O
"	O
slot	O
is	O
basically	O
a	B-General_Concept
PCI	B-Protocol
slot	I-Protocol
(	O
with	O
twice	O
the	O
electrical	O
power	O
)	O
with	O
an	O
AGP	O
connector	O
.	O
</s>
<s>
It	O
offers	O
backward	B-General_Concept
compatibility	I-General_Concept
with	O
AGP	O
cards	O
,	O
but	O
provides	O
incomplete	O
support	O
(	O
some	O
AGP	O
cards	O
do	O
not	O
work	O
with	O
AGP	O
Express	O
)	O
and	O
reduced	O
performance	O
—	O
the	O
card	O
is	O
forced	O
to	O
use	O
the	O
shared	O
PCI	B-Protocol
bus	I-Protocol
at	O
its	O
lower	O
bandwidth	O
,	O
rather	O
than	O
having	O
exclusive	O
use	O
of	O
the	O
faster	O
AGP	O
.	O
</s>
<s>
AGI	O
The	O
ASRock	O
Graphics	O
Interface	O
(	O
AGI	O
)	O
is	O
a	B-General_Concept
proprietary	O
variant	O
of	O
the	O
Accelerated	B-Architecture
Graphics	I-Architecture
Port	I-Architecture
(	O
AGP	O
)	O
standard	O
.	O
</s>
<s>
However	O
,	O
it	O
is	O
not	O
fully	O
compatible	O
with	O
AGP	O
,	O
and	O
several	O
video	B-Device
card	I-Device
chipsets	O
are	O
known	O
not	O
to	O
be	O
supported	O
.	O
</s>
<s>
AGR	O
The	O
Advanced	B-Device
Graphics	I-Device
Riser	I-Device
is	O
a	B-General_Concept
variation	O
of	O
the	O
AGP	B-Architecture
port	I-Architecture
used	O
in	O
some	O
PCIe	O
motherboards	O
made	O
by	O
MSI	O
to	O
offer	O
limited	O
backwards	B-General_Concept
compatibility	I-General_Concept
with	O
AGP	O
.	O
</s>
<s>
It	O
is	O
,	O
effectively	O
,	O
a	B-General_Concept
modified	O
PCIe	O
slot	O
allowing	O
for	O
performance	O
comparable	O
to	O
an	O
AGP	O
4×	O
/8	O
×	O
slot	O
,	O
but	O
does	O
not	O
support	O
all	O
AGP	O
cards	O
;	O
the	O
manufacturer	O
published	O
a	B-General_Concept
list	O
of	O
some	O
cards	O
and	O
chipsets	O
that	O
work	O
with	O
the	O
modified	O
slot	O
.	O
</s>
<s>
AGP	O
cards	O
are	O
backward	B-General_Concept
and	O
forward	B-General_Concept
compatible	I-General_Concept
within	O
limits	O
.	O
</s>
<s>
Some	O
of	O
the	O
last	O
modern	O
cards	O
with	O
3.3	O
V	O
support	O
were	O
the	O
Nvidia	O
GeForce	O
FX	O
series	O
(	O
FX	O
5200	O
,	O
FX	O
5500	O
,	O
FX	O
5700	O
,	O
some	O
FX	O
5800	O
,	O
FX	O
5900	O
and	O
some	O
FX	O
5950	O
)	O
,	O
certain	O
Geforce	O
6	O
Series	O
and	O
7	O
series	O
(	O
few	O
cards	O
were	O
made	O
with	O
3.3v	O
support	O
except	O
for	O
6200	O
where	O
3.3v	O
support	O
was	O
common	O
)	O
and	O
the	O
ATI	O
Radeon	O
9500/9700/9800	O
(	O
R300/R350	O
)	O
(	O
but	O
not	O
9600/9800	O
(	O
R360/RV360	O
)	O
)	O
.	O
</s>
<s>
AGP	O
Pro	O
cards	O
will	O
not	O
fit	O
into	O
standard	O
slots	O
,	O
but	O
standard	O
AGP	O
cards	O
will	O
work	O
in	O
a	B-General_Concept
Pro	O
slot	O
.	O
</s>
<s>
Motherboards	O
equipped	O
with	O
a	B-General_Concept
Universal	O
AGP	O
Pro	O
slot	O
will	O
accept	O
a	B-General_Concept
1.5	O
V	O
or	O
3.3	O
V	O
card	O
in	O
either	O
the	O
AGP	O
Pro	O
or	O
standard	O
AGP	O
configuration	O
,	O
a	B-General_Concept
Universal	O
AGP	O
card	O
,	O
or	O
a	B-General_Concept
Universal	O
AGP	O
Pro	O
card	O
.	O
</s>
<s>
Some	O
cards	O
incorrectly	O
have	O
dual	O
notches	O
,	O
and	O
some	O
motherboards	O
incorrectly	O
have	O
fully	O
open	O
slots	O
,	O
allowing	O
a	B-General_Concept
card	O
to	O
be	O
plugged	O
into	O
a	B-General_Concept
slot	O
that	O
does	O
not	O
support	O
the	O
correct	O
signaling	O
voltage	O
,	O
which	O
may	O
damage	O
card	O
or	O
motherboard	O
.	O
</s>
<s>
There	O
are	O
some	O
proprietary	O
systems	O
incompatible	O
with	O
standard	O
AGP	O
;	O
for	O
example	O
,	O
Apple	B-Device
Power	I-Device
Macintosh	I-Device
computers	O
with	O
the	O
Apple	B-Protocol
Display	I-Protocol
Connector	I-Protocol
(	O
ADC	O
)	O
have	O
an	O
extra	O
connector	O
which	O
delivers	O
power	O
to	O
the	O
attached	O
display	O
.	O
</s>
<s>
Some	O
cards	O
designed	O
to	O
work	O
with	O
a	B-General_Concept
specific	O
CPU	B-General_Concept
architecture	I-General_Concept
(	O
e.g.	O
,	O
PC	O
,	O
Apple	O
)	O
may	O
not	O
work	O
with	O
others	O
due	O
to	O
firmware	B-Application
issues	O
.	O
</s>
<s>
Actual	O
power	O
supplied	O
by	O
an	O
AGP	B-Architecture
slot	I-Architecture
depends	O
upon	O
the	O
card	O
used	O
.	O
</s>
<s>
For	O
example	O
,	O
if	O
maximum	O
current	O
is	O
drawn	O
from	O
all	O
supplies	O
and	O
all	O
voltages	O
are	O
at	O
their	O
specified	O
upper	O
limits	O
,	O
an	O
AGP3.0	O
slot	O
can	O
supply	O
up	O
to	O
48.25watts	O
;	O
this	O
figure	O
can	O
be	O
used	O
to	O
specify	O
a	B-General_Concept
power	O
supply	O
conservatively	O
,	O
but	O
in	O
practice	O
a	B-General_Concept
card	O
is	O
unlikely	O
ever	O
to	O
draw	O
more	O
than	O
40W	O
from	O
the	O
slot	O
,	O
with	O
many	O
using	O
less	O
.	O
</s>
<s>
An	O
AGP	O
bus	B-General_Concept
is	O
a	B-General_Concept
superset	O
of	O
a	B-General_Concept
66MHz	O
conventional	B-Protocol
PCI	I-Protocol
bus	B-General_Concept
and	O
,	O
immediately	O
after	O
reset	O
,	O
follows	O
the	O
same	O
protocol	O
.	O
</s>
<s>
The	O
card	O
must	O
act	O
as	O
a	B-General_Concept
PCI	B-Protocol
target	O
,	O
and	O
optionally	O
may	O
act	O
as	O
a	B-General_Concept
PCI	B-Protocol
master	O
.	O
</s>
<s>
(	O
AGP	O
2.0	O
added	O
a	B-General_Concept
"	O
fast	O
writes	O
"	O
extension	O
which	O
allows	O
PCI	B-Protocol
writes	O
from	O
the	O
motherboard	O
to	O
the	O
card	O
to	O
transfer	O
data	O
at	O
higher	O
speed	O
.	O
)	O
</s>
<s>
After	O
the	O
card	O
is	O
initialized	O
using	O
PCI	B-Protocol
transactions	O
,	O
AGP	O
transactions	O
are	O
permitted	O
.	O
</s>
<s>
The	O
card	O
queues	O
multiple	O
requests	O
which	O
correspond	O
to	O
the	O
PCI	B-Protocol
address	B-Architecture
phase	O
,	O
and	O
the	O
motherboard	O
schedules	O
the	O
corresponding	O
data	O
phases	O
later	O
.	O
</s>
<s>
An	O
important	O
part	O
of	O
initialization	O
is	O
telling	O
the	O
card	O
the	O
maximum	O
number	O
of	O
outstanding	O
AGP	O
requests	O
which	O
may	O
be	O
queued	O
at	O
a	B-General_Concept
given	O
time	O
.	O
</s>
<s>
AGP	O
requests	O
are	O
similar	O
to	O
PCI	B-Protocol
memory	O
read	O
and	O
write	O
requests	O
,	O
but	O
use	O
a	B-General_Concept
different	O
encoding	O
on	O
command	O
lines	O
C/BE[3:0]	O
and	O
are	O
always	O
8-byte	O
aligned	B-Application
;	O
their	O
starting	O
address	B-Architecture
and	O
length	O
are	O
always	O
multiples	O
of	O
8	O
bytes	O
(	O
64	B-Device
bits	I-Device
)	O
.	O
</s>
<s>
The	O
three	O
low-order	O
bits	O
of	O
the	O
address	B-Architecture
are	O
used	O
instead	O
to	O
communicate	O
the	O
length	O
of	O
the	O
request	O
.	O
</s>
<s>
Whenever	O
the	O
PCI	B-Protocol
GNT#	O
signal	O
is	O
asserted	O
,	O
granting	O
the	O
bus	B-General_Concept
to	O
the	O
card	O
,	O
three	O
additional	O
status	O
bits	O
ST[2:0]	O
indicate	O
the	O
type	O
of	O
transfer	O
to	O
be	O
performed	O
next	O
.	O
</s>
<s>
If	O
the	O
bits	O
are	O
0xx	O
,	O
a	B-General_Concept
previously	O
queued	O
AGP	O
transaction	O
's	O
data	O
is	O
to	O
be	O
transferred	O
;	O
if	O
the	O
three	O
bits	O
are	O
111	O
,	O
the	O
card	O
may	O
begin	O
a	B-General_Concept
PCI	B-Protocol
transaction	O
or	O
(	O
if	O
sideband	B-Architecture
addressing	I-Architecture
is	O
not	O
in	O
use	O
)	O
queue	O
a	B-General_Concept
request	O
in-band	O
using	O
PIPE#	O
.	O
</s>
<s>
Like	O
PCI	B-Protocol
,	O
each	O
AGP	O
transaction	O
begins	O
with	O
an	O
address	B-Architecture
phase	O
,	O
communicating	O
an	O
address	B-Architecture
and	O
4-bit	O
command	O
code	O
.	O
</s>
<s>
The	O
possible	O
commands	O
are	O
different	O
from	O
PCI	B-Protocol
,	O
however	O
:	O
</s>
<s>
This	O
is	O
the	O
same	O
as	O
a	B-General_Concept
read	O
request	O
,	O
but	O
the	O
length	O
is	O
multiplied	O
by	O
four	O
.	O
</s>
<s>
This	O
acts	O
as	O
a	B-General_Concept
low-priority	O
read	O
,	O
taking	O
a	B-General_Concept
queue	O
slot	O
and	O
returning	O
8	O
bytes	O
of	O
random	O
data	O
to	O
indicate	O
completion	O
.	O
</s>
<s>
The	O
address	B-Architecture
and	O
length	O
supplied	O
with	O
this	O
command	O
are	O
ignored	O
.	O
</s>
<s>
This	O
acts	O
as	O
a	B-General_Concept
memory	B-General_Concept
fence	I-General_Concept
,	O
requiring	O
that	O
all	O
earlier	O
AGP	O
requests	O
complete	O
before	O
any	O
following	O
requests	O
.	O
</s>
<s>
Ordinarily	O
,	O
for	O
increased	O
performance	O
,	O
AGP	O
uses	O
a	B-General_Concept
very	O
weak	O
consistency	B-General_Concept
model	I-General_Concept
,	O
and	O
allows	O
a	B-General_Concept
later	O
write	O
to	O
pass	O
an	O
earlier	O
read	O
.	O
</s>
<s>
after	O
sending	O
"	O
write	O
1	O
,	O
write	O
2	O
,	O
read	O
,	O
write	O
3	O
,	O
write	O
4	O
"	O
requests	O
,	O
all	O
to	O
the	O
same	O
address	B-Architecture
,	O
the	O
read	O
may	O
return	O
any	O
value	O
from	O
2	O
to	O
4	O
.	O
</s>
<s>
When	O
making	O
a	B-General_Concept
request	O
to	O
an	O
address	B-Architecture
above	O
232	O
,	O
this	O
is	O
used	O
to	O
indicate	O
that	O
a	B-General_Concept
second	O
address	B-Architecture
cycle	O
will	O
follow	O
with	O
additional	O
address	B-Architecture
bits	O
.	O
</s>
<s>
This	O
operates	O
like	O
a	B-General_Concept
regular	O
PCI	B-Protocol
dual	O
address	B-Architecture
cycle	O
;	O
it	O
is	O
accompanied	O
by	O
the	O
low-order	O
32	O
bits	O
of	O
the	O
address	B-Architecture
(	O
and	O
the	O
length	O
)	O
,	O
and	O
the	O
following	O
cycle	O
includes	O
the	O
high	O
32	O
address	B-Architecture
bits	O
and	O
the	O
desired	O
command	O
.	O
</s>
<s>
It	O
also	O
mandated	O
side-band	O
addressing	O
,	O
thus	O
dropping	O
the	O
dual	O
address	B-Architecture
cycle	O
,	O
leaving	O
only	O
four	O
request	O
types	O
:	O
low-priority	O
read	O
(	O
0000	O
)	O
,	O
low-priority	O
write	O
(	O
0100	O
)	O
,	O
flush	O
(	O
1010	O
)	O
and	O
fence	O
(	O
1100	O
)	O
.	O
</s>
<s>
To	O
queue	O
a	B-General_Concept
request	O
in-band	O
,	O
the	O
card	O
must	O
request	O
the	O
bus	B-General_Concept
using	O
the	O
standard	O
PCI	B-Protocol
REQ#	O
signal	O
,	O
and	O
receive	O
GNT#	O
plus	O
bus	B-General_Concept
status	O
ST[2:0]	O
equal	O
to	O
111	O
.	O
</s>
<s>
Then	O
,	O
instead	O
of	O
asserting	O
FRAME#	O
to	O
begin	O
a	B-General_Concept
PCI	B-Protocol
transaction	O
,	O
the	O
card	O
asserts	O
the	O
PIPE#	O
signal	O
while	O
driving	O
the	O
AGP	O
command	O
,	O
address	B-Architecture
,	O
and	O
length	O
on	O
the	O
C/BE[3:0],	O
AD[31:3]	O
and	O
AD[2:0]	O
lines	O
,	O
respectively	O
.	O
</s>
<s>
(	O
If	O
the	O
address	B-Architecture
is	O
64	B-Device
bits	I-Device
,	O
a	B-General_Concept
dual	O
address	B-Architecture
cycle	O
similar	O
to	O
PCI	B-Protocol
is	O
used	O
.	O
)	O
</s>
<s>
Instead	O
,	O
requests	O
are	O
broken	O
into	O
16-bit	O
pieces	O
which	O
are	O
sent	O
as	O
two	O
bytes	O
across	O
the	O
SBA	O
bus	B-General_Concept
.	O
</s>
<s>
There	O
is	O
no	O
need	O
for	O
the	O
card	O
to	O
ask	O
permission	O
from	O
the	O
motherboard	O
;	O
a	B-General_Concept
new	O
request	O
may	O
be	O
sent	O
at	O
any	O
time	O
as	O
long	O
as	O
the	O
number	O
of	O
outstanding	O
requests	O
is	O
within	O
the	O
configured	O
maximum	O
queue	O
depth	O
.	O
</s>
<s>
Queue	O
a	B-General_Concept
request	O
with	O
the	O
given	O
low-order	O
address	B-Architecture
bits	O
A[14:3]	O
and	O
length	O
8×( L[	O
2:0	O
 ]+1	O
)	O
.	O
</s>
<s>
Any	O
number	O
of	O
requests	O
may	O
be	O
queued	O
by	O
sending	O
only	O
this	O
pattern	O
,	O
as	O
long	O
as	O
the	O
command	O
and	O
higher	O
address	B-Architecture
bits	O
remain	O
the	O
same	O
.	O
</s>
<s>
Use	O
command	O
C[3:0]	O
and	O
address	B-Architecture
bits	O
A[23:15]	O
for	O
future	O
requests	O
.	O
</s>
<s>
This	O
does	O
not	O
queue	O
a	B-General_Concept
request	O
,	O
but	O
sets	O
values	O
that	O
will	O
be	O
used	O
in	O
all	O
future	O
queued	O
requests	O
.	O
</s>
<s>
Use	O
address	B-Architecture
bits	O
A[35:24]	O
for	O
future	O
requests	O
.	O
</s>
<s>
Use	O
address	B-Architecture
bits	O
A[47:36]	O
for	O
future	O
requests	O
.	O
</s>
<s>
Synchronization	O
pattern	O
used	O
when	O
starting	O
the	O
SBA	O
bus	B-General_Concept
after	O
an	O
idle	O
period	O
.	O
</s>
<s>
No	B-Language
operation	I-Language
;	O
no	O
request	O
.	O
</s>
<s>
At	O
AGP	O
1×	O
speed	O
,	O
this	O
may	O
be	O
sent	O
as	O
a	B-General_Concept
single	O
byte	O
and	O
a	B-General_Concept
following	O
16-bit	O
side-band	O
request	O
started	O
one	O
cycle	O
later	O
.	O
</s>
<s>
At	O
AGP	O
2×	O
and	O
higher	O
speeds	O
,	O
all	O
side-band	O
requests	O
,	O
including	O
this	O
NOP	B-Language
,	O
are	O
16	O
bits	O
long	O
.	O
</s>
<s>
Sideband	O
address	B-Architecture
bytes	O
are	O
sent	O
at	O
the	O
same	O
rate	O
as	O
data	O
transfers	O
,	O
up	O
to	O
8×	O
the	O
66MHz	O
basic	O
bus	B-General_Concept
clock	O
.	O
</s>
<s>
Sideband	B-Architecture
addressing	I-Architecture
has	O
the	O
advantage	O
that	O
it	O
mostly	O
eliminates	O
the	O
need	O
for	O
turnaround	O
cycles	O
on	O
the	O
AD	O
bus	B-General_Concept
between	O
transfers	O
,	O
in	O
the	O
usual	O
case	O
when	O
read	O
operations	O
greatly	O
outnumber	O
writes	O
.	O
</s>
<s>
While	O
asserting	O
GNT#	O
,	O
the	O
motherboard	O
may	O
instead	O
indicate	O
via	O
the	O
ST	O
bits	O
that	O
a	B-General_Concept
data	O
phase	O
for	O
a	B-General_Concept
queued	O
request	O
will	O
be	O
performed	O
next	O
.	O
</s>
<s>
For	O
each	O
cycle	O
when	O
the	O
GNT#	O
is	O
asserted	O
and	O
the	O
status	O
bits	O
have	O
the	O
value	O
00p	O
,	O
a	B-General_Concept
read	O
response	O
of	O
the	O
indicated	O
priority	O
is	O
scheduled	O
to	O
be	O
returned	O
.	O
</s>
<s>
(	O
Other	O
PCI	B-Protocol
bus	I-Protocol
signals	O
like	O
FRAME#	O
,	O
DEVSEL#	O
and	O
IRDY#	O
remain	O
deasserted	O
.	O
)	O
</s>
<s>
If	O
either	O
one	O
does	O
not	O
,	O
wait	B-Device
states	I-Device
will	O
be	O
inserted	O
until	O
two	O
cycles	O
after	O
they	O
both	O
do	O
.	O
</s>
<s>
For	O
each	O
cycle	O
when	O
GNT#	O
is	O
asserted	O
and	O
the	O
status	O
bits	O
have	O
the	O
value	O
01p	O
,	O
write	O
data	O
is	O
scheduled	O
to	O
be	O
sent	O
across	O
the	O
bus	B-General_Concept
.	O
</s>
<s>
The	O
multiplier	O
in	O
AGP	O
2×	O
,	O
4×	O
and	O
8×	O
indicates	O
the	O
number	O
of	O
data	O
transfers	O
across	O
the	O
bus	B-General_Concept
during	O
each	O
66MHz	O
clock	O
cycle	O
.	O
</s>
<s>
Such	O
transfers	O
use	O
source	O
synchronous	O
clocking	O
with	O
a	B-General_Concept
"	O
strobe	O
"	O
signal	O
(	O
AD_STB[0]	O
,	O
AD_STB[1],	O
and	O
SB_STB	O
)	O
generated	O
by	O
the	O
data	O
source	O
.	O
</s>
<s>
Because	O
AGP	O
transactions	O
may	O
be	O
as	O
short	O
as	O
two	O
transfers	O
,	O
at	O
AGP	O
4×	O
and	O
8×	O
speeds	O
it	O
is	O
possible	O
for	O
a	B-General_Concept
request	O
to	O
complete	O
in	O
the	O
middle	O
of	O
a	B-General_Concept
clock	O
cycle	O
.	O
</s>
<s>
In	O
such	O
a	B-General_Concept
case	O
,	O
the	O
cycle	O
is	O
padded	O
with	O
dummy	O
data	O
transfers	O
(	O
with	O
the	O
C/BE	O
#	O
byte	O
enable	O
lines	O
held	O
deasserted	O
)	O
.	O
</s>
<s>
The	O
AGP	O
connector	O
contains	O
almost	O
all	O
PCI	B-Protocol
signals	O
,	O
plus	O
several	O
additions	O
.	O
</s>
<s>
Pin1	O
is	O
closest	O
to	O
the	O
I/O	O
bracket	O
,	O
and	O
the	O
B	O
and	O
A	B-General_Concept
sides	O
are	O
as	O
in	O
the	O
table	O
,	O
looking	O
down	O
at	O
the	O
motherboard	O
connector	O
.	O
</s>
<s>
Odd-numbered	O
A-side	O
contacts	O
,	O
and	O
even-numbered	O
B-side	O
contacts	O
are	O
in	O
the	O
lower	O
row	O
(	O
1.0	O
to	O
3.5mm	O
from	O
the	O
card	O
edge	O
)	O
.	O
</s>
<s>
PCI	B-Protocol
signals	O
omitted	O
are	O
:	O
</s>
