<s>
AVR	O
is	O
a	O
family	O
of	O
microcontrollers	B-Architecture
developed	O
since	O
1996	O
by	O
Atmel	O
,	O
acquired	O
by	O
Microchip	O
Technology	O
in	O
2016	O
.	O
</s>
<s>
These	O
are	O
modified	B-Device
Harvard	I-Device
architecture	I-Device
8-bit	O
RISC	B-Architecture
single-chip	O
microcontrollers	B-Architecture
.	O
</s>
<s>
AVR	O
was	O
one	O
of	O
the	O
first	O
microcontroller	B-Architecture
families	O
to	O
use	O
on-chip	O
flash	B-Device
memory	I-Device
for	O
program	O
storage	O
,	O
as	O
opposed	O
to	O
one-time	B-General_Concept
programmable	I-General_Concept
ROM	I-General_Concept
,	O
EPROM	B-General_Concept
,	O
or	O
EEPROM	B-General_Concept
used	O
by	O
other	O
microcontrollers	B-Architecture
at	O
the	O
time	O
.	O
</s>
<s>
AVR	B-Architecture
microcontrollers	I-Architecture
find	O
many	O
applications	O
as	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
However	O
,	O
it	O
is	O
commonly	O
accepted	O
that	O
AVR	O
stands	O
for	O
Alf	O
and	O
Vegard	O
's	O
RISC	B-Architecture
processor	I-Architecture
.	O
</s>
<s>
Note	O
that	O
the	O
use	O
of	O
"	O
AVR	O
"	O
in	O
this	O
article	O
generally	O
refers	O
to	O
the	O
8-bit	O
RISC	B-Architecture
line	O
of	O
Atmel	B-Architecture
AVR	I-Architecture
microcontrollers	B-Architecture
.	O
</s>
<s>
It	O
was	O
known	O
as	O
a	O
μRISC	O
(	O
Micro	O
RISC	B-Architecture
)	O
and	O
was	O
available	O
as	O
silicon	O
IP/building	O
block	O
from	O
Nordic	O
VLSI	O
.	O
</s>
<s>
When	O
the	O
technology	O
was	O
sold	O
to	O
Atmel	O
from	O
Nordic	O
VLSI	O
,	O
the	O
internal	O
architecture	O
was	O
further	O
developed	O
by	O
Bogen	O
and	O
Wollan	O
at	O
Atmel	B-Architecture
Norway	I-Architecture
,	O
a	O
subsidiary	O
of	O
Atmel	O
.	O
</s>
<s>
The	O
designers	O
worked	O
closely	O
with	O
compiler	B-Language
writers	O
at	O
IAR	O
Systems	O
to	O
ensure	O
that	O
the	O
AVR	B-Device
instruction	I-Device
set	I-Device
provided	O
efficient	O
compilation	B-Language
of	O
high-level	B-Language
languages	I-Language
.	O
</s>
<s>
Among	O
the	O
first	O
of	O
the	O
AVR	O
line	O
was	O
the	O
AT90S8515	B-Architecture
,	O
which	O
in	O
a	O
40-pin	O
DIP	B-Algorithm
package	B-Algorithm
has	O
the	O
same	O
pinout	O
as	O
an	O
8051	B-Architecture
microcontroller	B-Architecture
,	O
including	O
the	O
external	O
multiplexed	O
address	O
and	O
data	O
bus	O
.	O
</s>
<s>
The	O
polarity	O
of	O
the	O
RESET	O
line	O
was	O
opposite	O
(	O
8051	B-Architecture
's	O
having	O
an	O
active-high	O
RESET	O
,	O
while	O
the	O
AVR	O
has	O
an	O
active-low	O
RESET	O
)	O
,	O
but	O
other	O
than	O
that	O
the	O
pinout	O
was	O
identical	O
.	O
</s>
<s>
The	O
AVR	O
8-bit	O
microcontroller	B-Architecture
architecture	O
was	O
introduced	O
in	O
1997	O
.	O
</s>
<s>
By	O
2003	O
,	O
Atmel	O
had	O
shipped	O
500	O
million	O
AVR	O
flash	B-Device
microcontrollers	B-Architecture
.	O
</s>
<s>
The	O
Arduino	O
platform	O
,	O
developed	O
for	O
simple	O
electronics	O
projects	O
,	O
was	O
released	O
in	O
2005	O
and	O
featured	O
ATmega8	B-Architecture
AVR	B-Architecture
microcontrollers	I-Architecture
.	O
</s>
<s>
The	O
AVR	O
is	O
a	O
modified	B-Device
Harvard	I-Device
architecture	I-Device
machine	O
,	O
where	O
program	O
and	O
data	O
are	O
stored	O
in	O
separate	O
physical	O
memory	O
systems	O
that	O
appear	O
in	O
different	O
address	B-General_Concept
spaces	I-General_Concept
,	O
but	O
having	O
the	O
ability	O
to	O
read	O
data	O
items	O
from	O
program	O
memory	O
using	O
special	O
instructions	O
.	O
</s>
<s>
The	O
ATtiny	O
series	O
feature	O
small	O
package	B-Algorithm
microcontrollers	B-Architecture
with	O
a	O
limited	O
peripheral	O
set	O
available	O
.	O
</s>
<s>
The	O
ATmega	O
series	O
feature	O
microcontrollers	B-Architecture
that	O
provide	O
an	O
extended	O
instruction	O
set	O
(	O
multiply	O
instructions	O
and	O
instructions	O
for	O
handling	O
larger	O
program	O
memories	O
)	O
,	O
an	O
extensive	O
peripheral	O
set	O
,	O
a	O
solid	O
amount	O
of	O
program	O
memory	O
,	O
as	O
well	O
as	O
a	O
wide	O
range	O
of	O
pins	O
available	O
.	O
</s>
<s>
AVR	O
Dx	O
–	O
The	O
AVR	O
Dx	O
family	O
is	O
featuring	O
multiple	O
microcontroller	B-Architecture
series	O
,	O
focused	O
on	O
HCI	O
,	O
analog	O
signal	O
conditioning	O
and	O
functional	O
safety	O
.	O
</s>
<s>
The	O
parts	O
numbers	O
is	O
formatted	O
as	O
AVRffDxpp	O
,	O
where	O
ff	O
is	O
flash	B-Device
size	I-Device
,	O
x	O
is	O
family	O
,	O
and	O
pp	O
is	O
number	O
of	O
pins	O
.	O
</s>
<s>
Example	O
:	O
AVR128DA64	O
–	O
64-pin	O
DA-series	O
with	O
128k	O
flash	B-Device
.	O
</s>
<s>
AVR	O
DA-series	O
(	O
early	O
2020	O
)	O
–	O
The	O
high	O
memory	O
density	O
makes	O
these	O
MCUs	B-Architecture
well	O
suited	O
for	O
both	O
wired	O
and	O
wireless	O
communication-stack-intensive	O
functions	O
.	O
</s>
<s>
AVR	O
DD-series	O
(	O
not	O
yet	O
released	O
)	O
–	O
small	O
package	B-Algorithm
microcontrollers	B-Architecture
designed	O
to	O
bring	O
real-time	O
control	O
and	O
multi-voltage	O
operation	O
to	O
applications	O
industrial	O
control	O
,	O
home	O
appliance	O
products	O
,	O
automotive	O
,	O
and	O
Internet	O
of	O
Things	O
(	O
IoT	O
)	O
.	O
</s>
<s>
megaAVRs	O
with	O
special	O
features	O
not	O
found	O
on	O
the	O
other	O
members	O
of	O
the	O
AVR	O
family	O
,	O
such	O
as	O
LCD	B-Device
controller	O
,	O
USB	B-Protocol
controller	O
,	O
advanced	O
PWM	B-Algorithm
,	O
CAN	B-Protocol
,	O
etc	O
.	O
</s>
<s>
In	O
2006	O
,	O
Atmel	O
released	O
microcontrollers	B-Architecture
based	O
on	O
the	O
32-bit	O
AVR32	B-Device
architecture	I-Device
.	O
</s>
<s>
This	O
was	O
a	O
completely	O
different	O
architecture	O
unrelated	O
to	O
the	O
8-bit	O
AVR	O
,	O
intended	O
to	O
compete	O
with	O
the	O
ARM-based	O
processors	O
.	O
</s>
<s>
It	O
had	O
a	O
32-bit	O
data	O
path	O
,	O
SIMD	B-Device
and	O
DSP	B-Architecture
instructions	O
,	O
along	O
with	O
other	O
audio	O
-	O
and	O
video-processing	O
features	O
.	O
</s>
<s>
The	O
instruction	O
set	O
was	O
similar	O
to	O
other	O
RISC	B-Architecture
cores	O
,	O
but	O
it	O
was	O
not	O
compatible	O
with	O
the	O
original	O
AVR	O
(	O
nor	O
any	O
of	O
the	O
various	O
ARM	B-Architecture
cores	O
)	O
.	O
</s>
<s>
Since	O
then	O
support	O
for	O
AVR32	B-Device
has	O
been	O
dropped	O
from	O
Linux	B-Application
as	O
of	O
kernel	O
4.12	O
;	O
compiler	B-Language
support	O
for	O
the	O
architecture	O
in	O
GCC	B-Application
was	O
never	O
mainlined	O
into	O
the	O
compiler	B-Language
's	O
central	O
source-code	O
repository	O
and	O
was	O
available	O
primarily	O
in	O
a	O
vendor-supported	O
fork	O
.	O
</s>
<s>
At	O
the	O
time	O
that	O
AVR32	B-Device
was	O
introduced	O
,	O
Atmel	O
had	O
already	O
been	O
a	O
licensee	O
of	O
the	O
ARM	B-Architecture
architecture	I-Architecture
,	O
with	O
both	O
ARM7	O
and	O
ARM9	O
microcontrollers	B-Architecture
having	O
been	O
released	O
prior	O
to	O
and	O
concurrently	O
with	O
the	O
AVR32	B-Device
;	O
later	O
Atmel	O
focused	O
most	O
development	O
effort	O
on	O
32-bit	O
chips	O
with	O
ARM	B-Architecture
Cortex-M	O
and	O
Cortex-A	O
cores	O
.	O
</s>
<s>
Flash	B-Device
,	O
EEPROM	B-General_Concept
,	O
and	O
SRAM	B-Architecture
are	O
all	O
integrated	O
onto	O
a	O
single	O
chip	O
,	O
removing	O
the	O
need	O
for	O
external	O
memory	O
in	O
most	O
applications	O
.	O
</s>
<s>
Almost	O
all	O
devices	O
(	O
except	O
the	O
smallest	O
TinyAVR	O
chips	O
)	O
have	O
serial	O
interfaces	O
,	O
which	O
can	B-Protocol
be	O
used	O
to	O
connect	O
larger	O
serial	O
EEPROMs	B-General_Concept
or	O
flash	B-Device
chips	I-Device
.	O
</s>
<s>
Program	O
instructions	O
are	O
stored	O
in	O
non-volatile	B-General_Concept
flash	B-Device
memory	I-Device
.	O
</s>
<s>
Although	O
the	O
MCUs	B-Architecture
are	O
8-bit	O
,	O
each	O
instruction	O
takes	O
one	O
or	O
two	O
16-bit	O
words	O
.	O
</s>
<s>
The	O
size	O
of	O
the	O
program	O
memory	O
is	O
usually	O
indicated	O
in	O
the	O
naming	O
of	O
the	O
device	O
itself	O
(	O
e.g.	O
,	O
the	O
ATmega64x	O
line	O
has	O
64KB	O
of	O
flash	B-Device
,	O
while	O
the	O
ATmega32x	O
line	O
has	O
32KB	O
)	O
.	O
</s>
<s>
There	O
is	O
no	O
provision	O
for	O
off-chip	O
program	O
memory	O
;	O
all	O
code	O
executed	O
by	O
the	O
AVR	O
core	O
must	O
reside	O
in	O
the	O
on-chip	O
flash	B-Device
.	O
</s>
<s>
However	O
,	O
this	O
limitation	O
does	O
not	O
apply	O
to	O
the	O
AT94	O
FPSLIC	O
AVR/FPGA	O
chips	O
.	O
</s>
<s>
The	O
data	O
address	B-General_Concept
space	I-General_Concept
consists	O
of	O
the	O
register	B-General_Concept
file	I-General_Concept
,	O
I/O	O
registers	B-General_Concept
,	O
and	O
SRAM	B-Architecture
.	O
</s>
<s>
Some	O
small	O
models	O
also	O
map	O
the	O
program	O
ROM	O
into	O
the	O
data	O
address	B-General_Concept
space	I-General_Concept
,	O
but	O
larger	O
models	O
do	O
not	O
.	O
</s>
<s>
The	O
AVRs	O
have	O
32	O
single-byte	B-Application
registers	B-General_Concept
and	O
are	O
classified	O
as	O
8-bit	O
RISC	B-Architecture
devices	O
.	O
</s>
<s>
In	O
the	O
tinyAVR	O
and	O
megaAVR	O
variants	O
of	O
the	O
AVR	O
architecture	O
,	O
the	O
working	B-General_Concept
registers	I-General_Concept
are	O
mapped	O
in	O
as	O
the	O
first	O
32	O
data	O
memory	O
addresses	O
(	O
000016	O
–	O
001F16	O
)	O
,	O
followed	O
by	O
64	O
I/O	O
registers	B-General_Concept
(	O
002016	O
–	O
005F16	O
)	O
.	O
</s>
<s>
In	O
devices	O
with	O
many	O
peripherals	O
,	O
these	O
registers	B-General_Concept
are	O
followed	O
by	O
160	O
“	O
extended	O
I/O	O
”	O
registers	B-General_Concept
,	O
only	O
accessible	O
as	O
memory-mapped	B-Architecture
I/O	I-Architecture
(	O
006016	O
–	O
00FF16	O
)	O
.	O
</s>
<s>
Actual	O
SRAM	B-Architecture
starts	O
after	O
these	O
register	B-General_Concept
sections	O
,	O
at	O
address	O
006016	O
or	O
,	O
in	O
devices	O
with	O
"	O
extended	O
I/O	O
"	O
,	O
at	O
010016	O
.	O
</s>
<s>
Even	O
though	O
there	O
are	O
separate	O
addressing	O
schemes	O
and	O
optimized	O
opcodes	O
for	O
accessing	O
the	O
register	B-General_Concept
file	I-General_Concept
and	O
the	O
first	O
64	O
I/O	O
registers	B-General_Concept
,	O
all	O
can	B-Protocol
also	O
be	O
addressed	O
and	O
manipulated	O
as	O
if	O
they	O
were	O
in	O
SRAM	B-Architecture
.	O
</s>
<s>
The	O
very	O
smallest	O
of	O
the	O
tinyAVR	O
variants	O
use	O
a	O
reduced	O
architecture	O
with	O
only	O
16	O
registers	B-General_Concept
(	O
r0	O
through	O
r15	O
are	O
omitted	O
)	O
which	O
are	O
not	O
addressable	O
as	O
memory	O
locations	O
.	O
</s>
<s>
I/O	O
memory	O
begins	O
at	O
address	O
000016	O
,	O
followed	O
by	O
SRAM	B-Architecture
.	O
</s>
<s>
In	O
addition	O
,	O
these	O
devices	O
have	O
slight	O
deviations	O
from	O
the	O
standard	O
AVR	B-Device
instruction	I-Device
set	I-Device
.	O
</s>
<s>
Most	O
notably	O
,	O
the	O
direct	O
load/store	O
instructions	O
(	O
LDS/STS	O
)	O
have	O
been	O
reduced	O
from	O
2	O
words	O
(	O
32	O
bits	O
)	O
to	O
1	O
word	O
(	O
16	O
bits	O
)	O
,	O
limiting	O
the	O
total	O
direct	O
addressable	O
memory	O
(	O
the	O
sum	O
of	O
both	O
I/O	O
and	O
SRAM	B-Architecture
)	O
to	O
128	O
bytes	B-Application
.	O
</s>
<s>
Conversely	O
,	O
the	O
indirect	O
load	O
instruction	O
's	O
(	O
LD	O
)	O
16-bit	O
address	B-General_Concept
space	I-General_Concept
is	O
expanded	O
to	O
also	O
include	O
non-volatile	B-General_Concept
memory	I-General_Concept
such	O
as	O
Flash	B-Device
and	O
configuration	O
bits	O
;	O
therefore	O
,	O
the	O
Load	O
Program	O
Memory	O
(	O
LPM	O
)	O
instruction	O
is	O
unnecessary	O
and	O
omitted	O
.	O
</s>
<s>
(	O
For	O
detailed	O
info	O
,	O
see	O
Atmel	B-Device
AVR	I-Device
instruction	I-Device
set	I-Device
.	O
)	O
</s>
<s>
In	O
the	O
XMEGA	B-Architecture
variant	O
,	O
the	O
working	B-General_Concept
register	I-General_Concept
file	O
is	O
not	O
mapped	O
into	O
the	O
data	O
address	B-General_Concept
space	I-General_Concept
;	O
as	O
such	O
,	O
it	O
is	O
not	O
possible	O
to	O
treat	O
any	O
of	O
the	O
XMEGA	B-Architecture
's	O
working	B-General_Concept
registers	I-General_Concept
as	O
though	O
they	O
were	O
SRAM	B-Architecture
.	O
</s>
<s>
Instead	O
,	O
the	O
I/O	O
registers	B-General_Concept
are	O
mapped	O
into	O
the	O
data	O
address	B-General_Concept
space	I-General_Concept
starting	O
at	O
the	O
very	O
beginning	O
of	O
the	O
address	B-General_Concept
space	I-General_Concept
.	O
</s>
<s>
Additionally	O
,	O
the	O
amount	O
of	O
data	O
address	B-General_Concept
space	I-General_Concept
dedicated	O
to	O
I/O	O
registers	B-General_Concept
has	O
grown	O
substantially	O
to	O
4096	O
bytes	B-Application
(	O
000016	O
–	O
0FFF16	O
)	O
.	O
</s>
<s>
As	O
with	O
previous	O
generations	O
,	O
however	O
,	O
the	O
fast	O
I/O	O
manipulation	O
instructions	O
can	B-Protocol
only	O
reach	O
the	O
first	O
64	O
I/O	O
register	B-General_Concept
locations	O
(	O
the	O
first	O
32	O
locations	O
for	O
bitwise	O
instructions	O
)	O
.	O
</s>
<s>
Following	O
the	O
I/O	O
registers	B-General_Concept
,	O
the	O
XMEGA	B-Architecture
series	O
sets	O
aside	O
a	O
4096	O
byte	B-Application
range	O
of	O
the	O
data	O
address	B-General_Concept
space	I-General_Concept
,	O
which	O
can	B-Protocol
be	O
used	O
optionally	O
for	O
mapping	O
the	O
internal	O
EEPROM	B-General_Concept
to	O
the	O
data	O
address	B-General_Concept
space	I-General_Concept
(	O
100016	O
–	O
1FFF16	O
)	O
.	O
</s>
<s>
The	O
actual	O
SRAM	B-Architecture
is	O
located	O
after	O
these	O
ranges	O
,	O
starting	O
at	O
200016	O
.	O
</s>
<s>
Each	O
GPIO	B-Architecture
port	O
on	O
a	O
tiny	O
or	O
mega	O
AVR	O
drives	O
up	O
to	O
eight	O
pins	O
and	O
is	O
controlled	O
by	O
three	O
8-bit	O
registers	B-General_Concept
:	O
DDRx	O
,	O
PORTx	O
and	O
PINx	O
,	O
where	O
x	O
is	O
the	O
port	O
identifier	O
.	O
</s>
<s>
DDRx	O
:	O
Data	O
Direction	O
Register	B-General_Concept
,	O
configures	O
the	O
pins	O
as	O
either	O
inputs	O
or	O
outputs	O
.	O
</s>
<s>
PORTx	O
:	O
Output	O
port	O
register	B-General_Concept
.	O
</s>
<s>
PINx	O
:	O
Input	O
register	B-General_Concept
,	O
used	O
to	O
read	O
an	O
input	O
signal	O
.	O
</s>
<s>
On	O
some	O
devices	O
,	O
this	O
register	B-General_Concept
can	B-Protocol
be	O
used	O
for	O
pin	O
toggling	O
:	O
writing	O
a	O
logic	O
one	O
to	O
a	O
PINx	O
bit	O
toggles	O
the	O
corresponding	O
bit	O
in	O
PORTx	O
,	O
irrespective	O
of	O
the	O
setting	O
of	O
the	O
DDRx	O
bit	O
.	O
</s>
<s>
Newer	O
ATtiny	O
AVR	O
's	O
,	O
like	O
ATtiny817	O
and	O
its	O
siblings	O
,	O
have	O
their	O
port	O
control	O
registers	B-General_Concept
somewhat	O
differently	O
defined	O
.	O
</s>
<s>
xmegaAVR	O
have	O
additional	O
registers	B-General_Concept
for	O
push/pull	O
,	O
totem-pole	O
and	O
pullup	O
configurations	O
.	O
</s>
<s>
Almost	O
all	O
AVR	B-Architecture
microcontrollers	I-Architecture
have	O
internal	O
EEPROM	B-General_Concept
for	O
semi-permanent	O
data	O
storage	O
.	O
</s>
<s>
Like	O
flash	B-Device
memory	I-Device
,	O
EEPROM	B-General_Concept
can	B-Protocol
maintain	O
its	O
contents	O
when	O
electrical	O
power	O
is	O
removed	O
.	O
</s>
<s>
In	O
most	O
variants	O
of	O
the	O
AVR	O
architecture	O
,	O
this	O
internal	O
EEPROM	B-General_Concept
memory	O
is	O
not	O
mapped	O
into	O
the	O
MCU	O
's	O
addressable	O
memory	O
space	O
.	O
</s>
<s>
It	O
can	B-Protocol
only	O
be	O
accessed	O
the	O
same	O
way	O
an	O
external	O
peripheral	O
device	O
is	O
,	O
using	O
special	O
pointer	B-General_Concept
registers	I-General_Concept
and	O
read/write	O
instructions	O
,	O
which	O
makes	O
EEPROM	B-General_Concept
access	O
much	O
slower	O
than	O
other	O
internal	O
RAM	O
.	O
</s>
<s>
However	O
,	O
some	O
devices	O
in	O
the	O
SecureAVR	O
(	O
AT90SC	O
)	O
family	O
use	O
a	O
special	O
EEPROM	B-General_Concept
mapping	O
to	O
the	O
data	O
or	O
program	O
memory	O
,	O
depending	O
on	O
the	O
configuration	O
.	O
</s>
<s>
The	O
XMEGA	B-Architecture
family	O
also	O
allows	O
the	O
EEPROM	B-General_Concept
to	O
be	O
mapped	O
into	O
the	O
data	O
address	B-General_Concept
space	I-General_Concept
.	O
</s>
<s>
Since	O
the	O
number	O
of	O
writes	O
to	O
EEPROM	B-General_Concept
is	O
limited	O
Atmel	O
specifies	O
100,000	O
write	O
cycles	O
in	O
their	O
datasheets	O
a	O
well	O
designed	O
EEPROM	B-General_Concept
write	O
routine	O
should	O
compare	O
the	O
contents	O
of	O
an	O
EEPROM	B-General_Concept
address	O
with	O
desired	O
contents	O
and	O
only	O
perform	O
an	O
actual	O
write	O
if	O
the	O
contents	O
need	O
to	O
be	O
changed	O
.	O
</s>
<s>
Atmel	O
's	O
AVRs	O
have	O
a	O
two-stage	O
,	O
single-level	O
pipeline	B-General_Concept
design	O
.	O
</s>
<s>
Most	O
instructions	O
take	O
just	O
one	O
or	O
two	O
clock	O
cycles	O
,	O
making	O
AVRs	O
relatively	O
fast	O
among	O
eight-bit	O
microcontrollers	B-Architecture
.	O
</s>
<s>
The	O
AVR	O
processors	O
were	O
designed	O
with	O
the	O
efficient	O
execution	O
of	O
compiled	B-Language
C	B-Language
code	O
in	O
mind	O
and	O
have	O
several	O
built-in	O
pointers	O
for	O
the	O
task	O
.	O
</s>
<s>
The	O
AVR	B-Device
instruction	I-Device
set	I-Device
is	O
more	O
orthogonal	B-General_Concept
than	O
those	O
of	O
most	O
eight-bit	O
microcontrollers	B-Architecture
,	O
in	O
particular	O
the	O
8051	B-Architecture
clones	I-Architecture
and	O
PIC	B-Architecture
microcontrollers	I-Architecture
with	O
which	O
AVR	O
competes	O
today	O
.	O
</s>
<s>
Pointer	B-General_Concept
registers	I-General_Concept
X	O
,	O
Y	O
,	O
and	O
Z	O
have	O
addressing	O
capabilities	O
that	O
are	O
different	O
from	O
each	O
other	O
.	O
</s>
<s>
Register	B-General_Concept
locations	O
R0	O
to	O
R15	O
have	O
more	O
limited	O
addressing	O
capabilities	O
than	O
register	B-General_Concept
locations	O
R16	O
to	O
R31	O
.	O
</s>
<s>
I/O	B-Architecture
ports	I-Architecture
0	O
to	O
31	O
can	B-Protocol
be	O
bit	O
addressed	O
,	O
unlike	O
I/O	B-Architecture
ports	I-Architecture
32	O
to	O
63	O
.	O
</s>
<s>
Accessing	O
read-only	O
data	O
stored	O
in	O
the	O
program	O
memory	O
(	O
flash	B-Device
)	O
requires	O
special	O
LPM	O
instructions	O
;	O
the	O
flash	B-Device
bus	O
is	O
otherwise	O
reserved	O
for	O
instruction	O
memory	O
.	O
</s>
<s>
Code	O
pointers	O
(	O
including	O
return	O
addresses	O
on	O
the	O
stack	O
)	O
are	O
two	O
bytes	B-Application
long	O
on	O
chips	O
with	O
up	O
to	O
128KB	O
of	O
flash	B-Device
memory	I-Device
,	O
but	O
three	O
bytes	B-Application
long	O
on	O
larger	O
chips	O
;	O
not	O
all	O
chips	O
have	O
hardware	O
multipliers	O
;	O
chips	O
with	O
over	O
8KB	O
of	O
flash	B-Device
have	O
branch	O
and	O
call	O
instructions	O
with	O
longer	O
ranges	O
;	O
and	O
so	B-Algorithm
forth	O
.	O
</s>
<s>
The	O
mostly	O
regular	O
instruction	O
set	O
makes	O
C	B-Language
(	O
and	O
even	O
Ada	O
)	O
compilers	B-Language
fairly	O
straightforward	O
and	O
efficient	O
.	O
</s>
<s>
GCC	B-Application
has	O
included	O
AVR	O
support	O
for	O
quite	O
some	O
time	O
,	O
and	O
that	O
support	O
is	O
widely	O
used	O
.	O
</s>
<s>
LLVM	B-Application
also	O
has	O
rudimentary	O
AVR	O
support	O
.	O
</s>
<s>
In	O
fact	O
,	O
Atmel	O
solicited	O
input	O
from	O
major	O
developers	O
of	O
compilers	B-Language
for	O
small	O
microcontrollers	B-Architecture
,	O
to	O
determine	O
the	O
instruction	O
set	O
features	O
that	O
were	O
most	O
useful	O
in	O
a	O
compiler	B-Language
for	O
high-level	B-Language
languages	I-Language
.	O
</s>
<s>
The	O
AVR	O
line	O
can	B-Protocol
normally	O
support	O
clock	O
speeds	O
from	O
0	O
to	O
20MHz	O
,	O
with	O
some	O
devices	O
reaching	O
32MHz	O
.	O
</s>
<s>
All	O
recent	O
(	O
Tiny	O
,	O
Mega	O
,	O
and	O
Xmega	B-Architecture
,	O
but	O
not	O
90S	O
)	O
AVRs	O
feature	O
an	O
on-chip	O
oscillator	O
,	O
removing	O
the	O
need	O
for	O
external	O
clocks	O
or	O
resonator	O
circuitry	O
.	O
</s>
<s>
Some	O
AVRs	O
also	O
have	O
a	O
system	O
clock	O
prescaler	O
that	O
can	B-Protocol
divide	O
down	O
the	O
system	O
clock	O
by	O
up	O
to	O
1024	O
.	O
</s>
<s>
This	O
prescaler	O
can	B-Protocol
be	O
reconfigured	O
by	O
software	O
during	O
run-time	O
,	O
allowing	O
the	O
clock	O
speed	O
to	O
be	O
optimized	O
.	O
</s>
<s>
Since	O
all	O
operations	O
(	O
excluding	O
multiplication	O
and	O
16-bit	O
add/subtract	O
)	O
on	O
registers	B-General_Concept
R0	O
–	O
R31	O
are	O
single-cycle	O
,	O
the	O
AVR	O
can	B-Protocol
achieve	O
up	O
to	O
1	O
MIPS	O
per	O
MHz	O
,	O
i.e.	O
</s>
<s>
an	O
8MHz	O
processor	O
can	B-Protocol
achieve	O
up	O
to	O
8MIPS	O
.	O
</s>
<s>
Branches	O
in	O
the	O
latest	O
"	O
3-byte	O
PC	O
"	O
parts	O
such	O
as	O
ATmega2560	B-Architecture
are	O
one	O
cycle	O
slower	O
than	O
on	O
previous	O
devices	O
.	O
</s>
<s>
The	O
JTAG	O
signals	O
(	O
TMS	O
,	O
TDI	O
,	O
TDO	O
,	O
and	O
TCK	O
)	O
are	O
multiplexed	O
on	O
GPIOs	B-Architecture
.	O
</s>
<s>
These	O
pins	O
can	B-Protocol
be	O
configured	O
to	O
function	O
as	O
JTAG	O
or	O
GPIO	B-Architecture
depending	O
on	O
the	O
setting	O
of	O
a	O
fuse	O
bit	O
,	O
which	O
can	B-Protocol
be	O
programmed	O
via	O
ISP	O
or	O
HVSP	O
.	O
</s>
<s>
The	O
external	O
data	O
space	O
is	O
overlaid	O
with	O
the	O
internal	O
data	O
space	O
,	O
such	O
that	O
the	O
full	O
64KB	O
address	B-General_Concept
space	I-General_Concept
does	O
not	O
appear	O
on	O
the	O
external	O
bus	O
and	O
accesses	O
to	O
e.g.	O
</s>
<s>
In	O
certain	O
members	O
of	O
the	O
XMega	B-Architecture
series	O
,	O
the	O
external	O
data	O
space	O
has	O
been	O
enhanced	O
to	O
support	O
both	O
SRAM	B-Architecture
and	O
SDRAM	O
.	O
</s>
<s>
Universal	O
Serial	O
Interface	O
(	O
USI	O
)	O
:	O
a	O
multi-purpose	O
hardware	O
communication	O
module	O
that	O
can	B-Protocol
be	O
used	O
to	O
implement	O
an	O
SPI	B-Architecture
,	O
I2C	O
or	O
UART	O
interface	O
.	O
</s>
<s>
DMA	B-General_Concept
controllers	I-General_Concept
and	O
"	O
event	O
system	O
"	O
peripheral	O
communication	O
.	O
</s>
<s>
The	O
in-system	B-Device
programming	I-Device
(	O
ISP	O
)	O
programming	O
method	O
is	O
functionally	O
performed	O
through	O
SPI	B-Architecture
,	O
plus	O
some	O
twiddling	O
of	O
the	O
Reset	O
line	O
.	O
</s>
<s>
As	O
long	O
as	O
the	O
SPI	B-Architecture
pins	O
of	O
the	O
AVR	O
are	O
not	O
connected	O
to	O
anything	O
disruptive	O
,	O
the	O
AVR	O
chip	O
can	B-Protocol
stay	O
soldered	O
on	O
a	O
PCB	O
while	O
reprogramming	O
.	O
</s>
<s>
The	O
Atmel-ICE	O
device	O
or	O
AVRISP	O
mkII	O
(	O
Legacy	O
device	O
)	O
connects	O
to	O
a	O
computer	O
's	O
USB	B-Protocol
port	I-Protocol
and	O
performs	O
in-system	B-Device
programming	I-Device
using	O
Atmel	O
's	O
software	O
.	O
</s>
<s>
AVRDUDE	O
(	O
AVR	O
Downloader/UploaDEr	O
)	O
runs	O
on	O
Linux	B-Application
,	O
FreeBSD	B-Operating_System
,	O
Windows	O
,	O
and	O
,	O
and	O
supports	O
a	O
variety	O
of	O
in-system	B-Device
programming	I-Device
hardware	O
,	O
including	O
Atmel	O
AVRISP	O
mkII	O
,	O
Atmel	O
JTAG	O
ICE	O
,	O
older	O
Atmel	O
serial-port	O
based	O
programmers	O
,	O
and	O
various	O
third-party	O
and	O
"	O
do-it-yourself	O
"	O
programmers	O
.	O
</s>
<s>
The	O
Program	O
and	O
Debug	O
Interface	O
(	O
PDI	B-Application
)	O
is	O
an	O
Atmel	O
proprietary	O
interface	O
for	O
external	O
programming	O
and	O
on-chip	O
debugging	O
of	O
XMEGA	B-Architecture
devices	O
.	O
</s>
<s>
The	O
PDI	B-Application
supports	O
high-speed	O
programming	O
of	O
all	O
non-volatile	B-General_Concept
memory	I-General_Concept
(	O
NVM	O
)	O
spaces	O
;	O
flash	B-Device
,	O
EEPROM	B-General_Concept
,	O
fuses	O
,	O
lock-bits	O
and	O
the	O
User	O
Signature	O
Row	O
.	O
</s>
<s>
This	O
is	O
done	O
by	O
accessing	O
the	O
XMEGA	B-Architecture
NVM	O
controller	O
through	O
the	O
PDI	B-Application
interface	O
,	O
and	O
executing	O
NVM	O
controller	O
commands	O
.	O
</s>
<s>
The	O
PDI	B-Application
is	O
a	O
2-pin	O
interface	O
using	O
the	O
Reset	O
pin	O
for	O
clock	O
input	O
(	O
PDI_CLK	O
)	O
and	O
a	O
dedicated	O
data	O
pin	O
(	O
PDI_DATA	O
)	O
for	O
input	O
and	O
output	O
.	O
</s>
<s>
It	O
is	O
also	O
possible	O
to	O
use	O
an	O
Arduino	O
thanks	O
to	O
jtag2updi	O
,	O
or	O
a	O
standard	O
USB-UART	O
adapter	O
with	O
the	O
TX	O
and	O
RX	O
pin	O
shorted	O
by	O
a	O
1	O
kΩ	O
resistor	O
and	O
the	O
pymcuprog	O
utility	O
provided	O
by	O
Microchip	O
.	O
</s>
<s>
An	O
8-pin	O
AVR	O
package	B-Algorithm
does	O
not	O
leave	O
many	O
unique	O
signal	O
combinations	O
to	O
place	O
the	O
AVR	O
into	O
a	O
programming	O
mode	O
.	O
</s>
<s>
The	O
high	O
voltage	O
mode	O
can	B-Protocol
also	O
be	O
used	O
in	O
some	O
devices	O
where	O
the	O
reset	O
pin	O
has	O
been	O
disabled	O
by	O
fuses	O
.	O
</s>
<s>
Most	O
AVR	O
models	O
can	B-Protocol
reserve	O
a	O
bootloader	B-Application
region	O
,	O
256bytes	O
to	O
4KB	O
,	O
where	O
re-programming	O
code	O
can	B-Protocol
reside	O
.	O
</s>
<s>
At	O
reset	O
,	O
the	O
bootloader	B-Application
runs	O
first	O
and	O
does	O
some	O
user-programmed	O
determination	O
whether	O
to	O
re-program	O
or	O
to	O
jump	O
to	O
the	O
main	O
application	O
.	O
</s>
<s>
The	O
code	O
can	B-Protocol
re-program	O
through	O
any	O
interface	O
available	O
,	O
or	O
it	O
could	O
read	O
an	O
encrypted	O
binary	O
through	O
an	O
Ethernet	O
adapter	O
like	O
PXE	B-Device
.	O
</s>
<s>
The	O
AT90SC	O
series	O
of	O
AVRs	O
are	O
available	O
with	O
a	O
factory	O
mask-ROM	O
rather	O
than	O
flash	B-Device
for	O
program	O
memory	O
.	O
</s>
<s>
aWire	O
is	O
a	O
new	O
one-wire	O
debug	O
interface	O
available	O
on	O
the	O
new	O
UC3L	O
AVR32	B-Device
devices	O
.	O
</s>
<s>
debugWIRE	O
is	O
Atmel	O
's	O
solution	O
for	O
providing	O
on-chip	O
debug	O
capabilities	O
via	O
a	O
single	O
microcontroller	B-Architecture
pin	O
.	O
</s>
<s>
JTAG	O
allows	O
accessing	O
internal	O
memory	O
and	O
registers	B-General_Concept
,	O
setting	O
breakpoints	O
on	O
code	O
,	O
and	O
single-stepping	O
execution	O
to	O
observe	O
system	O
behaviour	O
.	O
</s>
<s>
It	O
supports	O
JTAG	O
,	O
debugWire	O
,	O
aWire	O
,	O
SPI	B-Architecture
,	O
TPI	O
,	O
and	O
PDI	B-Application
interfaces	O
.	O
</s>
<s>
It	O
supports	O
JTAG	O
,	O
aWire	O
,	O
SPI	B-Architecture
,	O
and	O
PDI	B-Application
interfaces	O
.	O
</s>
<s>
The	O
JTAGICE	O
mkII	O
interfaces	O
to	O
the	O
PC	O
via	O
USB	B-Protocol
,	O
and	O
supports	O
both	O
JTAG	O
and	O
the	O
newer	O
debugWIRE	O
interface	O
.	O
</s>
<s>
JTAG	O
can	B-Protocol
also	O
be	O
used	O
to	O
perform	O
a	O
boundary	O
scan	O
test	O
,	O
which	O
tests	O
the	O
electrical	O
connections	O
between	O
AVRs	O
and	O
other	O
boundary	O
scan	O
capable	O
chips	O
in	O
a	O
system	O
.	O
</s>
<s>
Official	O
Atmel	B-Architecture
AVR	I-Architecture
development	O
tools	O
and	O
evaluation	O
kits	O
contain	O
a	O
number	O
of	O
starter	O
kits	O
and	O
debugging	O
tools	O
with	O
support	O
for	O
most	O
AVR	O
devices	O
:	O
</s>
<s>
The	O
base	O
board	O
is	O
similar	O
to	O
the	O
STK500	O
,	O
in	O
that	O
it	O
provides	O
a	O
power	O
supply	O
,	O
clock	O
,	O
in-system	B-Device
programming	I-Device
,	O
an	O
RS-232	O
port	O
and	O
a	O
CAN	B-Protocol
(	O
Controller	B-Protocol
Area	I-Protocol
Network	I-Protocol
,	O
an	O
automotive	O
standard	O
)	O
port	O
via	O
DE9	O
connectors	O
,	O
and	O
stake	O
pins	O
for	O
all	O
of	O
the	O
GPIO	B-Architecture
signals	O
from	O
the	O
target	O
device	O
.	O
</s>
<s>
The	O
target	O
boards	O
have	O
ZIF	B-General_Concept
sockets	I-General_Concept
for	O
DIP	B-Algorithm
,	O
SOIC	B-Algorithm
,	O
QFN	B-Algorithm
,	O
or	O
QFP	B-Algorithm
packages	O
,	O
depending	O
on	O
the	O
board	O
.	O
</s>
<s>
There	O
are	O
many	O
different	O
signal	O
routing	O
boards	O
that	O
could	O
be	O
used	O
with	O
a	O
single	O
target	O
board	O
,	O
depending	O
on	O
what	O
device	O
is	O
in	O
the	O
ZIF	B-General_Concept
socket	I-General_Concept
.	O
</s>
<s>
The	O
STK600	O
allows	O
in-system	B-Device
programming	I-Device
from	O
the	O
PC	O
via	O
USB	B-Protocol
,	O
leaving	O
the	O
RS-232	O
port	O
available	O
for	O
the	O
target	O
microcontroller	B-Architecture
.	O
</s>
<s>
A	O
4	O
pin	B-Protocol
header	I-Protocol
on	O
the	O
STK600	O
labeled	O
'	O
RS-232	O
spare	O
 '	O
can	B-Protocol
connect	O
any	O
TTL	O
level	O
USART	O
port	O
on	O
the	O
chip	O
to	O
an	O
onboard	O
MAX232	O
chip	O
to	O
translate	O
the	O
signals	O
to	O
RS-232	O
levels	O
.	O
</s>
<s>
The	O
board	O
is	O
fitted	O
with	O
DIP	B-Algorithm
sockets	O
for	O
all	O
AVRs	O
available	O
in	O
DIP	B-Algorithm
packages	O
.	O
</s>
<s>
STK501	O
–	O
Adds	O
support	O
for	O
microcontrollers	B-Architecture
in	O
64-pin	O
TQFP	O
packages	O
.	O
</s>
<s>
STK502	O
–	O
Adds	O
support	O
for	O
LCD	B-Device
AVRs	O
in	O
64-pin	O
TQFP	O
packages	O
.	O
</s>
<s>
STK503	O
–	O
Adds	O
support	O
for	O
microcontrollers	B-Architecture
in	O
100-pin	O
TQFP	O
packages	O
.	O
</s>
<s>
STK504	O
–	O
Adds	O
support	O
for	O
LCD	B-Device
AVRs	O
in	O
100-pin	O
TQFP	O
packages	O
.	O
</s>
<s>
STK520	O
–	O
Adds	O
support	O
for	O
14	O
and	O
20	O
,	O
and	O
32-pin	O
microcontrollers	B-Architecture
from	O
the	O
AT90PWM	O
and	O
ATmega	O
family	O
.	O
</s>
<s>
STK524	O
–	O
Adds	O
support	O
for	O
the	O
ATmega32M1/C1	O
32-pin	O
CAN/LIN/Motor	O
Control	O
family	O
.	O
</s>
<s>
STK525	O
–	O
Adds	O
support	O
for	O
the	O
AT90USB	O
microcontrollers	B-Architecture
in	O
64-pin	O
TQFP	O
packages	O
.	O
</s>
<s>
STK526	O
–	O
Adds	O
support	O
for	O
the	O
AT90USB	O
microcontrollers	B-Architecture
in	O
32-pin	O
TQFP	O
packages	O
.	O
</s>
<s>
The	O
STK200	O
starter	O
kit	O
and	O
development	O
system	O
has	O
a	O
DIP	B-Algorithm
socket	O
that	O
can	B-Protocol
host	O
an	O
AVR	O
chip	O
in	O
a	O
40	O
,	O
20	O
,	O
or	O
8-pin	O
package	B-Algorithm
.	O
</s>
<s>
The	O
board	O
has	O
a	O
4MHz	O
clock	O
source	O
,	O
8	O
light-emitting	O
diode	O
(	O
LED	O
)	O
s	O
,	O
8	O
input	O
buttons	O
,	O
an	O
RS-232	O
port	O
,	O
a	O
socket	O
for	O
a	O
32	O
KB	O
SRAM	B-Architecture
and	O
numerous	O
general	O
I/O	O
.	O
</s>
<s>
The	O
chip	O
can	B-Protocol
be	O
programmed	O
with	O
a	O
dongle	O
connected	O
to	O
the	O
parallel	O
port	O
.	O
</s>
<s>
It	O
connects	O
to	O
and	O
receives	O
power	O
from	O
a	O
PC	O
via	O
USB	B-Protocol
,	O
and	O
supports	O
JTAG	O
,	O
PDI	B-Application
,	O
aWire	O
,	O
debugWIRE	O
,	O
SPI	B-Architecture
,	O
SWD	O
,	O
TPI	O
,	O
and	O
UPDI	O
(	O
the	O
Microchip	O
Unified	O
Program	O
and	O
Debug	O
Interface	O
)	O
interfaces	O
.	O
</s>
<s>
The	O
ICE	O
can	B-Protocol
program	O
and	O
debug	O
all	O
AVRs	O
via	O
the	O
JTAG	O
interface	O
,	O
and	O
program	O
with	O
additional	O
interfaces	O
as	O
supported	O
on	O
each	O
device	O
:	O
</s>
<s>
The	O
ICE	O
is	O
supported	O
by	O
the	O
Microchip	O
Studio	O
IDE	B-Application
,	O
as	O
well	O
as	O
a	O
command	O
line	O
interface	O
(	O
atprogram	O
)	O
.	O
</s>
<s>
The	O
AVRISP	O
and	O
AVRISP	O
mkII	O
are	O
inexpensive	O
tools	O
allowing	O
all	O
AVRs	O
to	O
be	O
programmed	O
via	O
ICSP	B-Device
.	O
</s>
<s>
The	O
AVRISP	O
allows	O
using	O
either	O
of	O
the	O
"	O
standard	O
"	O
ICSP	B-Device
pinouts	O
,	O
either	O
the	O
10-pin	O
or	O
6-pin	O
connector	O
.	O
</s>
<s>
The	O
AVRISP	O
mkII	O
connects	O
to	O
a	O
PC	O
via	O
USB	B-Protocol
and	O
draws	O
power	O
from	O
USB	B-Protocol
.	O
</s>
<s>
As	O
the	O
AVRISP	O
mkII	O
lacks	O
driver/buffer	O
ICs	O
,	O
it	O
can	B-Protocol
have	O
trouble	O
programming	O
target	O
boards	O
with	O
multiple	O
loads	O
on	O
its	O
SPI	B-Architecture
lines	O
.	O
</s>
<s>
Alternatively	O
,	O
the	O
AVRISP	O
mkII	O
can	B-Protocol
still	O
be	O
used	O
if	O
low-value	O
(	O
~	O
150	O
ohm	O
)	O
load-limiting	O
resistors	O
can	B-Protocol
be	O
placed	O
on	O
the	O
SPI	B-Architecture
lines	O
before	O
each	O
peripheral	O
device	O
.	O
</s>
<s>
The	O
Atmel	O
Dragon	O
is	O
an	O
inexpensive	O
tool	O
which	O
connects	O
to	O
a	O
PC	O
via	O
USB	B-Protocol
.	O
</s>
<s>
The	O
Dragon	O
can	B-Protocol
program	O
all	O
AVRs	O
via	O
JTAG	O
,	O
HVP	O
,	O
PDI	B-Application
,	O
or	O
ICSP	B-Device
.	O
</s>
<s>
The	O
Dragon	O
also	O
allows	O
debugging	O
of	O
all	O
AVRs	O
via	O
JTAG	O
,	O
PDI	B-Application
,	O
or	O
debugWire	O
;	O
a	O
previous	O
limitation	O
to	O
devices	O
with	O
32KB	O
or	O
less	O
program	O
memory	O
has	O
been	O
removed	O
in	O
AVR	O
Studio	O
4.18	O
.	O
</s>
<s>
The	O
Dragon	O
has	O
a	O
small	O
prototype	O
area	O
which	O
can	B-Protocol
accommodate	O
an	O
8	O
,	O
28	O
,	O
or	O
40-pin	O
AVR	O
,	O
including	O
connections	O
to	O
power	O
and	O
programming	O
pins	O
.	O
</s>
<s>
There	O
is	O
no	O
area	O
for	O
any	O
additional	O
circuitry	O
,	O
although	O
this	O
can	B-Protocol
be	O
provided	O
by	O
a	O
third-party	O
product	O
called	O
the	O
"	O
Dragon	O
Rider	O
"	O
.	O
</s>
<s>
The	O
original	O
JTAGICE	O
(	O
sometimes	O
retroactively	O
referred	O
to	O
as	O
JTAGICE	O
mkI	O
)	O
uses	O
an	O
RS-232	O
interface	O
to	O
a	O
PC	O
and	O
can	B-Protocol
only	O
program	O
AVR	O
's	O
with	O
a	O
JTAG	O
interface	O
.	O
</s>
<s>
The	O
JTAGICE	O
mkII	O
debugging	O
tool	O
supports	O
on-chip	O
debugging	O
(	O
OCD	O
)	O
of	O
AVRs	O
with	O
SPI	B-Architecture
,	O
JTAG	O
,	O
PDI	B-Application
,	O
and	O
debugWIRE	O
interfaces	O
.	O
</s>
<s>
The	O
debugWire	O
interface	O
enables	O
debugging	O
using	O
only	O
one	O
pin	O
(	O
the	O
Reset	O
pin	O
)	O
,	O
allowing	O
debugging	O
of	O
applications	O
running	O
on	O
low	O
pin-count	O
microcontrollers	B-Architecture
.	O
</s>
<s>
The	O
JTAGICE	O
mkII	O
connects	O
using	O
USB	B-Protocol
,	O
but	O
there	O
is	O
an	O
alternate	O
connection	O
via	O
a	O
serial	O
port	O
,	O
which	O
requires	O
using	O
a	O
separate	O
power	O
supply	O
.	O
</s>
<s>
Both	O
the	O
USB	B-Protocol
and	O
serial	O
links	O
use	O
a	O
variant	O
of	O
the	O
STK500	O
protocol	O
.	O
</s>
<s>
It	O
connects	O
via	O
USB	B-Protocol
and	O
supports	O
the	O
JTAG	O
,	O
aWire	O
,	O
SPI	B-Architecture
,	O
and	O
PDI	B-Application
interfaces	O
.	O
</s>
<s>
It	O
supports	O
SPI	B-Architecture
,	O
JTAG	O
,	O
PDI	B-Application
,	O
and	O
aWire	O
programming	O
modes	O
and	O
debugging	O
using	O
debugWIRE	O
,	O
JTAG	O
,	O
PDI	B-Application
,	O
and	O
aWire	O
interfaces	O
.	O
</s>
<s>
The	O
very	O
popular	O
AVR	O
Butterfly	O
demonstration	O
board	O
is	O
a	O
self-contained	O
,	O
battery-powered	O
computer	O
running	O
the	O
Atmel	B-Architecture
AVR	I-Architecture
ATmega169V	O
microcontroller	B-Architecture
.	O
</s>
<s>
It	O
was	O
built	O
to	O
show	O
off	O
the	O
AVR	O
family	O
,	O
especially	O
a	O
then	O
new	O
built-in	O
LCD	B-Device
interface	O
.	O
</s>
<s>
The	O
board	O
includes	O
the	O
LCD	B-Device
screen	I-Device
,	O
joystick	O
,	O
speaker	O
,	O
serial	O
port	O
,	O
real	O
time	O
clock	O
(	O
RTC	O
)	O
,	O
flash	B-Device
memory	I-Device
chip	O
,	O
and	O
both	O
temperature	O
and	O
voltage	O
sensors	O
.	O
</s>
<s>
The	O
small	O
board	O
has	O
a	O
shirt	O
pin	O
on	O
its	O
back	O
so	B-Algorithm
it	O
can	B-Protocol
be	O
worn	O
as	O
a	O
name	O
badge	O
.	O
</s>
<s>
The	O
AVR	O
Butterfly	O
comes	O
preloaded	O
with	O
software	O
to	O
demonstrate	O
the	O
capabilities	O
of	O
the	O
microcontroller	B-Architecture
.	O
</s>
<s>
Factory	O
firmware	O
can	B-Protocol
scroll	O
your	O
name	O
,	O
display	O
the	O
sensor	O
readings	O
,	O
and	O
show	O
the	O
time	O
.	O
</s>
<s>
The	O
AVR	O
Butterfly	O
also	O
has	O
a	O
piezoelectric	O
transducer	O
that	O
can	B-Protocol
be	O
used	O
to	O
reproduce	O
sounds	O
and	O
music	O
.	O
</s>
<s>
The	O
AVR	O
Butterfly	O
demonstrates	O
LCD	B-Device
driving	O
by	O
running	O
a	O
14-segment	O
,	O
six	O
alpha-numeric	O
character	O
display	O
.	O
</s>
<s>
However	O
,	O
the	O
LCD	B-Device
interface	O
consumes	O
many	O
of	O
the	O
I/O	O
pins	O
.	O
</s>
<s>
The	O
Butterfly	O
's	O
ATmega169	B-Architecture
CPU	O
is	O
capable	O
of	O
speeds	O
up	O
to	O
8MHz	O
,	O
but	O
it	O
is	O
factory	O
set	O
by	O
software	O
to	O
2MHz	O
to	O
preserve	O
the	O
button	O
battery	O
life	O
.	O
</s>
<s>
A	O
pre-installed	O
bootloader	B-Application
program	O
allows	O
the	O
board	O
to	O
be	O
re-programmed	O
via	O
a	O
standard	O
RS-232	O
serial	O
plug	O
with	O
new	O
programs	O
that	O
users	O
can	B-Protocol
write	O
with	O
the	O
free	O
Atmel	O
IDE	B-Application
tools	O
.	O
</s>
<s>
It	O
includes	O
an	O
AT90USB1287	O
with	O
USB	B-Protocol
On-The-Go	O
(	O
OTG	O
)	O
support	O
,	O
16MB	O
of	O
DataFlash	B-General_Concept
,	O
LEDs	O
,	O
a	O
small	O
joystick	O
,	O
and	O
a	O
temperature	O
sensor	O
.	O
</s>
<s>
The	O
board	O
includes	O
software	O
,	O
which	O
lets	O
it	O
act	O
as	O
a	O
USB	B-Architecture
mass	I-Architecture
storage	I-Architecture
device	I-Architecture
(	O
its	O
documentation	O
is	O
shipped	O
on	O
the	O
DataFlash	B-General_Concept
)	O
,	O
a	O
USB	B-Protocol
joystick	O
,	O
and	O
more	O
.	O
</s>
<s>
To	O
support	O
the	O
USB	B-Protocol
host	O
capability	O
,	O
it	O
must	O
be	O
operated	O
from	O
a	O
battery	O
,	O
but	O
when	O
running	O
as	O
a	O
USB	B-Protocol
peripheral	O
,	O
it	O
only	O
needs	O
the	O
power	O
provided	O
over	O
USB	B-Protocol
.	O
</s>
<s>
All	O
the	O
other	O
AVR	O
I/O	B-Architecture
ports	I-Architecture
require	O
more	O
compact	O
1.27mm	O
headers	O
.	O
</s>
<s>
The	O
AVR	O
Dragon	O
can	B-Protocol
both	O
program	O
and	O
debug	O
since	O
the	O
32KB	O
limitation	O
was	O
removed	O
in	O
AVR	O
Studio	O
4.18	O
,	O
and	O
the	O
JTAGICE	O
mkII	O
is	O
capable	O
of	O
both	O
programming	O
and	O
debugging	O
the	O
processor	O
.	O
</s>
<s>
The	O
processor	O
can	B-Protocol
also	O
be	O
programmed	O
through	O
USB	B-Protocol
from	O
a	O
Windows	O
or	O
Linux	B-Application
host	O
,	O
using	O
the	O
USB	B-Protocol
"	O
Device	O
Firmware	O
Update	O
"	O
protocols	O
.	O
</s>
<s>
Atmel	O
ships	O
proprietary	O
(	O
source	O
code	O
included	O
but	O
distribution	O
restricted	O
)	O
example	O
programs	O
and	O
a	O
USB	B-Protocol
protocol	O
stack	O
with	O
the	O
device	O
.	O
</s>
<s>
LUFA	O
is	O
a	O
third-party	O
free	B-Application
software	I-Application
(	O
MIT	B-License
license	I-License
)	O
USB	B-Protocol
protocol	O
stack	O
for	O
the	O
USBKey	O
and	O
other	O
8-bit	O
USB	B-Protocol
AVRs	O
.	O
</s>
<s>
The	O
RAVEN	O
kit	O
supports	O
wireless	O
development	O
using	O
Atmel	O
's	O
IEEE	O
802.15.4	O
chipsets	O
,	O
for	O
Zigbee	B-Protocol
and	O
other	O
wireless	O
stacks	O
.	O
</s>
<s>
The	O
kit	O
includes	O
two	O
AVR	O
Raven	O
boards	O
,	O
each	O
with	O
a	O
2.4GHz	O
transceiver	O
supporting	O
IEEE	O
802.15.4	O
(	O
and	O
a	O
freely	O
licensed	O
Zigbee	B-Protocol
stack	O
)	O
.	O
</s>
<s>
The	O
radios	O
are	O
driven	O
with	O
ATmega1284p	O
processors	O
,	O
which	O
are	O
supported	O
by	O
a	O
custom	O
segmented	O
LCD	B-Device
display	I-Device
driven	O
by	O
an	O
ATmega3290p	O
processor	O
.	O
</s>
<s>
Raven	O
peripherals	O
resemble	O
the	O
Butterfly	O
:	O
piezo	O
speaker	O
,	O
DataFlash	B-General_Concept
(	O
bigger	O
)	O
,	O
external	O
EEPROM	B-General_Concept
,	O
sensors	O
,	O
32kHz	O
crystal	O
for	O
RTC	O
,	O
and	O
so	B-Algorithm
on	O
.	O
</s>
<s>
The	O
USB	B-Protocol
stick	O
uses	O
an	O
AT90USB1287	O
for	O
connections	O
to	O
a	O
USB	B-Protocol
host	O
and	O
to	O
the	O
2.4GHz	O
wireless	O
links	O
.	O
</s>
<s>
These	O
devices	O
use	O
various	O
interfaces	O
,	O
including	O
RS-232	O
,	O
PC	O
parallel	O
port	O
,	O
and	O
USB	B-Protocol
.	O
</s>
<s>
Atmel	O
has	O
recently	O
launched	O
a	O
new	O
publication	O
"	O
Atmel	O
Automotive	O
Compilation	B-Language
"	O
to	O
help	O
developers	O
with	O
automotive	O
applications	O
.	O
</s>
<s>
The	O
Arduino	O
physical	B-General_Concept
computing	I-General_Concept
platform	O
is	O
based	O
on	O
an	O
ATmega328	B-Device
microcontroller	B-Architecture
(	O
ATmega168	B-Architecture
or	O
ATmega8	B-Architecture
in	O
board	O
versions	O
older	O
than	O
the	O
Diecimila	O
)	O
.	O
</s>
<s>
The	O
ATmega1280	B-Architecture
and	O
ATmega2560	B-Architecture
,	O
with	O
more	O
pinout	O
and	O
memory	O
capabilities	O
,	O
have	O
also	O
been	O
employed	O
to	O
develop	O
the	O
Arduino	O
Mega	O
platform	O
.	O
</s>
<s>
Arduino	O
boards	O
can	B-Protocol
be	O
used	O
with	O
its	O
language	O
and	O
IDE	B-Application
,	O
or	O
with	O
more	O
conventional	O
programming	B-Application
environments	I-Application
(	O
C	B-Language
,	O
assembler	B-Language
,	O
etc	O
.	O
)	O
</s>
<s>
USB-based	O
AVRs	O
have	O
been	O
used	O
in	O
the	O
Microsoft	O
Xbox	O
hand	O
controllers	O
.	O
</s>
<s>
The	O
link	O
between	O
the	O
controllers	O
and	O
Xbox	O
is	O
USB	B-Protocol
.	O
</s>
<s>
Numerous	O
companies	O
produce	O
AVR-based	O
microcontroller	B-Architecture
boards	O
intended	O
for	O
use	O
by	O
hobbyists	O
,	O
robot	O
builders	O
,	O
experimenters	O
and	O
small	O
system	O
developers	O
including	O
:	O
Cubloc	O
,	O
gnusb	O
,	O
BasicX	B-Language
,	O
Oak	O
Micros	O
,	O
ZX	O
Microcontrollers	B-Architecture
,	O
and	O
myAVR	O
.	O
</s>
<s>
Schneider	O
Electric	O
used	O
to	O
produce	O
the	O
M3000	O
Motor	O
and	O
Motion	O
Control	O
Chip	O
,	O
incorporating	O
an	O
Atmel	B-Architecture
AVR	I-Architecture
Core	O
and	O
an	O
advanced	O
motion	O
controller	O
for	O
use	O
in	O
a	O
variety	O
of	O
motion	O
applications	O
but	O
this	O
has	O
been	O
discontinued	O
.	O
</s>
<s>
With	O
the	O
growing	O
popularity	O
of	O
FPGAs	B-Architecture
among	O
the	O
open	O
source	O
community	O
,	O
people	O
have	O
started	O
developing	O
open	O
source	O
processors	O
compatible	O
with	O
the	O
AVR	B-Device
instruction	I-Device
set	I-Device
.	O
</s>
<s>
pAVR	O
,	O
written	O
in	O
VHDL	B-Language
,	O
is	O
aimed	O
at	O
creating	O
the	O
fastest	O
and	O
maximally	O
featured	O
AVR	O
processor	O
,	O
by	O
implementing	O
techniques	O
not	O
found	O
in	O
the	O
original	O
AVR	O
processor	O
such	O
as	O
deeper	O
pipelining	B-General_Concept
.	O
</s>
<s>
avr_core	O
,	O
written	O
in	O
VHDL	B-Language
,	O
is	O
a	O
clone	O
aimed	O
at	O
being	O
as	O
close	O
as	O
possible	O
to	O
the	O
ATmega103	O
.	O
</s>
<s>
Navré	O
,	O
written	O
in	O
Verilog	B-Language
,	O
implements	O
all	O
Classic	B-Device
Core	I-Device
instructions	O
and	O
is	O
aimed	O
at	O
high	O
performance	O
and	O
low	O
resource	O
usage	O
.	O
</s>
<s>
softavrcore	O
,	O
written	O
in	O
Verilog	B-Language
,	O
implements	O
the	O
AVR	B-Device
instruction	I-Device
set	I-Device
up	O
to	O
AVR5	O
,	O
supports	O
interrupts	O
along	O
with	O
optional	O
automatic	O
interrupt	O
acknowledgement	O
,	O
power	O
saving	O
via	O
sleep	B-Algorithm
mode	I-Algorithm
plus	O
some	O
peripheral	O
interfaces	O
and	O
hardware	O
accelerators	O
(	O
such	O
as	O
UART	O
,	O
SPI	B-Architecture
,	O
cyclic	O
redundancy	O
check	O
calculation	O
unit	O
and	O
system	O
timers	O
)	O
.	O
</s>
<s>
Within	O
the	O
package	B-Algorithm
,	O
a	O
full-featured	O
FreeRTOS	B-Operating_System
port	O
is	O
also	O
available	O
as	O
an	O
example	O
for	O
the	O
core	O
+	O
peripheral	O
utilization	O
.	O
</s>
<s>
The	O
opencores	O
project	O
written	O
in	O
VHDL	B-Language
by	O
Dr.	O
Jürgen	O
Sauermann	O
explains	O
in	O
detail	O
how	O
to	O
design	O
a	O
complete	O
AVR-based	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
(	O
SoC	O
)	O
.	O
</s>
<s>
These	O
parts	O
are	O
not	O
exact	O
clones	O
-	O
they	O
have	O
a	O
few	O
features	O
not	O
found	O
in	O
the	O
chips	O
they	O
are	O
"	O
clones	O
"	O
of	O
,	O
and	O
higher	O
maximum	O
clock	O
speeds	O
,	O
but	O
use	O
SWD	O
instead	O
of	O
ISP	O
for	O
programming	O
,	O
so	B-Algorithm
different	O
programming	O
tools	O
must	O
be	O
used	O
.	O
</s>
<s>
Microcontrollers	B-Architecture
using	O
the	O
ATmega	O
architecture	O
are	O
being	O
manufactured	O
by	O
NIIET	O
in	O
Voronezh	O
,	O
Russia	O
,	O
as	O
part	O
of	O
the	O
1887	O
series	O
of	O
integrated	O
circuits	O
.	O
</s>
