<s>
AVR32	B-Device
is	O
a	O
32-bit	O
RISC	B-Architecture
microcontroller	O
architecture	O
produced	O
by	O
Atmel	O
.	O
</s>
<s>
The	O
multiply	B-Algorithm
–	I-Algorithm
accumulate	I-Algorithm
unit	O
can	O
perform	O
a	O
32-bit	O
×	O
16-bit	B-Device
+	O
48-bit	O
arithmetic	O
operation	O
in	O
two	O
cycles	O
(	O
result	O
latency	O
)	O
,	O
issued	O
once	O
per	O
cycle	O
.	O
</s>
<s>
It	O
does	O
not	O
resemble	O
the	O
8-bit	O
AVR	B-Architecture
microcontroller	I-Architecture
family	O
,	O
even	O
though	O
they	O
were	O
both	O
designed	O
at	O
Atmel	B-Architecture
Norway	I-Architecture
,	O
in	O
Trondheim	O
.	O
</s>
<s>
Support	O
for	O
AVR32	B-Device
has	O
been	O
dropped	O
from	O
Linux	B-Application
as	O
of	O
kernel	O
4.12	O
;	O
Atmel	O
has	O
switched	O
mostly	O
to	O
M	O
variants	O
of	O
the	O
ARM	B-Architecture
architecture	I-Architecture
.	O
</s>
<s>
The	O
AVR32	B-Device
has	O
at	O
least	O
two	O
micro-architectures	O
,	O
the	O
AVR32A	B-Device
and	O
AVR32B	B-Device
.	O
</s>
<s>
These	O
differ	O
in	O
the	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
,	O
register	O
configurations	O
and	O
the	O
use	O
of	O
caches	B-General_Concept
for	O
instructions	O
and	O
data	O
.	O
</s>
<s>
The	O
AVR32A	B-Device
CPU	O
cores	O
are	O
for	O
inexpensive	O
applications	O
.	O
</s>
<s>
The	O
AVR32B	B-Device
CPU	O
cores	O
are	O
designed	O
for	O
fast	O
interrupts	O
.	O
</s>
<s>
The	O
AVR32B	B-Device
cores	O
also	O
support	O
a	O
Java	B-Language
virtual	I-Language
machine	I-Language
in	O
hardware	O
.	O
</s>
<s>
The	O
AVR32	B-Device
instruction	B-General_Concept
set	I-General_Concept
has	O
16-bit	B-Device
(	O
compact	O
)	O
and	O
32-bit	O
(	O
extended	O
)	O
instructions	O
,	O
similar	O
to	O
e.g.	O
</s>
<s>
some	O
ARM	B-Architecture
,	O
with	O
several	O
specialized	O
instructions	O
not	O
found	O
in	O
older	O
ARMv5	O
or	O
ARMv6	O
or	O
MIPS32	B-Device
.	O
</s>
<s>
Several	O
U.S.	O
patents	O
are	O
filed	O
for	O
the	O
AVR32	B-Device
ISA	O
and	O
design	O
platform	O
.	O
</s>
<s>
Just	O
like	O
the	O
AVR	B-Architecture
8-bit	I-Architecture
microcontroller	I-Architecture
architecture	O
,	O
the	O
AVR32	B-Device
was	O
designed	O
for	O
high	O
code	O
density	O
(	O
packing	O
much	O
function	O
in	O
few	O
instructions	O
)	O
and	O
fast	O
instructions	O
with	O
few	O
clock	O
cycles	O
.	O
</s>
<s>
Atmel	O
used	O
the	O
independent	O
benchmark	O
consortium	O
EEMBC	O
to	O
benchmark	O
the	O
architecture	O
with	O
various	O
compilers	O
and	O
consistently	O
outperformed	O
both	O
ARMv5	O
16-bit	B-Device
(	O
Thumb	O
)	O
code	O
and	O
ARMv5	O
32-bit	O
(	O
ARM	B-Architecture
)	O
code	O
by	O
as	O
much	O
as	O
50%	O
on	O
code-size	O
and	O
3×	O
on	O
performance	O
.	O
</s>
<s>
Atmel	O
says	O
the	O
"	O
picoPower	O
"	O
AVR32	B-Device
AT32UC3L	B-Device
consumes	O
less	O
than	O
0.48mW/MHz	O
in	O
active	O
mode	O
,	O
which	O
it	O
claimed	O
,	O
at	O
the	O
time	O
,	O
used	O
less	O
power	O
than	O
any	O
other	O
32-bit	O
CPU	O
.	O
</s>
<s>
Then	O
in	O
March	O
2015	O
,	O
they	O
claim	O
their	O
new	O
Cortex-M0	O
+	O
-based	O
microcontrollers	O
,	O
using	O
ARM	B-Architecture
Holdings	O
 '	O
ARM	B-Architecture
architecture	I-Architecture
,	O
not	O
their	O
own	O
instruction	B-General_Concept
set	I-General_Concept
,	O
"	O
has	O
broken	O
all	O
ultra-low	O
power	O
performance	O
barriers	O
to	O
date.	O
"	O
</s>
<s>
The	O
AVR32	B-Device
architecture	I-Device
was	O
used	O
only	O
in	O
Atmel	O
's	O
own	O
products	O
.	O
</s>
<s>
In	O
2006	O
,	O
Atmel	O
launched	O
the	O
AVR32A	B-Device
:	O
The	O
AVR32	B-Device
AP7	O
core	O
,	O
a	O
7-stage	O
pipelined	B-General_Concept
,	O
cache-based	O
design	O
platform	O
.	O
</s>
<s>
This	O
"	O
AP7000	O
"	O
implements	O
the	O
AVR32B	B-Device
architecture	O
,	O
and	O
supports	O
a	O
hardware	O
FPU	B-General_Concept
,	O
SIMD	B-Device
(	O
single	B-Device
instruction	I-Device
multiple	I-Device
data	I-Device
)	O
DSP	B-Architecture
(	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
)	O
instructions	O
to	O
the	O
RISC	B-Architecture
instruction-set	O
,	O
in	O
addition	O
to	O
Java	O
hardware	O
acceleration	O
.	O
</s>
<s>
It	O
includes	O
a	O
Memory	O
Management	O
Unit	O
(	O
MMU	O
)	O
and	O
supports	O
operating	O
systems	O
like	O
Linux	B-Application
.	O
</s>
<s>
In	O
2007	O
,	O
Atmel	O
launched	O
the	O
second	O
AVR32	B-Device
:	O
The	O
AVR32	B-Device
UC3	O
core	O
.	O
</s>
<s>
This	O
is	O
designed	O
for	O
microcontrollers	O
,	O
using	O
on-chip	O
flash	B-Device
memory	I-Device
for	O
program	O
storage	O
and	O
running	O
without	O
an	O
MMU	O
(	O
memory	O
management	O
unit	O
)	O
.	O
</s>
<s>
The	O
AVR32	B-Device
UC3	O
core	O
uses	O
a	O
three-stage	O
pipelined	B-General_Concept
Harvard	O
architecture	O
specially	O
designed	O
to	O
optimize	O
instruction	O
fetches	O
from	O
on-chip	O
flash	B-Device
memory	I-Device
.	O
</s>
<s>
The	O
AVR32	B-Device
UC3	O
core	O
implements	O
the	O
AVR32A	B-Device
architecture	O
.	O
</s>
<s>
It	O
shares	O
the	O
same	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
as	O
its	O
AP7	O
sibling	O
,	O
but	O
differs	O
by	O
not	O
including	O
the	O
optional	O
SIMD	B-Device
instructions	O
or	O
Java	O
support	O
.	O
</s>
<s>
The	O
FPU	B-General_Concept
instruction	B-General_Concept
set	I-General_Concept
is	O
optional	O
,	O
and	O
was	O
not	O
implemented	O
in	O
the	O
initial	O
families	O
of	O
UC3	O
microcontrollers	O
.	O
</s>
<s>
It	O
shares	O
more	O
than	O
220	O
instructions	O
with	O
the	O
AVR32B	B-Device
.	O
</s>
<s>
The	O
ISA	O
features	O
atomic	O
bit	O
manipulation	O
to	O
control	O
on-chip	O
peripherals	O
and	O
general	O
purpose	O
I/Os	O
and	O
fixed	O
point	O
DSP	B-Architecture
arithmetic	O
.	O
</s>
<s>
Both	O
implementations	O
can	O
be	O
combined	O
with	O
a	O
compatible	O
set	O
of	O
peripheral	O
controllers	O
and	O
buses	O
first	O
seen	O
in	O
the	O
AT91SAM	O
ARM-based	O
platforms	O
.	O
</s>
<s>
Some	O
peripherals	O
first	O
seen	O
in	O
the	O
AP7000	O
,	O
such	O
as	O
the	O
high	O
speed	O
USB	O
peripheral	O
controller	O
,	O
and	O
standalone	O
DMA	O
controller	O
,	O
appeared	O
later	O
in	O
updated	O
ARM9	O
platforms	O
and	O
then	O
in	O
the	O
ARM	B-Architecture
Cortex-M3	O
based	O
products	O
.	O
</s>
<s>
Both	O
AVR32	B-Device
cores	O
include	O
a	O
Nexus	O
class	O
2+	O
based	O
On-Chip	O
Debug	O
framework	O
build	O
with	O
JTAG	O
.	O
</s>
<s>
The	O
UC3	O
C	O
core	O
,	O
announced	O
at	O
the	O
Electronica	O
2010	O
in	O
Munich	O
Germany	O
on	O
November	O
10	O
,	O
2010	O
,	O
was	O
the	O
first	O
member	O
of	O
the	O
UC3	O
family	O
to	O
implement	O
FPU	B-General_Concept
support	O
.	O
</s>
