<s>
ARM	B-Architecture
big.LITTLE	I-Architecture
is	O
a	O
heterogeneous	O
computing	O
architecture	O
developed	O
by	O
ARM	O
Holdings	O
,	O
coupling	O
relatively	O
battery-saving	O
and	O
slower	O
processor	O
cores	O
(	O
LITTLE	O
)	O
with	O
relatively	O
more	O
powerful	O
and	O
power-hungry	O
ones	O
(	O
big	O
)	O
.	O
</s>
<s>
The	O
intention	O
is	O
to	O
create	O
a	O
multi-core	B-Architecture
processor	I-Architecture
that	O
can	O
adjust	O
better	O
to	O
dynamic	O
computing	O
needs	O
and	O
use	O
less	O
power	O
than	O
clock	B-General_Concept
scaling	I-General_Concept
alone	O
.	O
</s>
<s>
Most	O
commonly	O
,	O
ARM	B-Architecture
big.LITTLE	I-Architecture
architectures	O
are	O
used	O
to	O
create	O
a	O
multi-processor	B-General_Concept
system-on-chip	I-General_Concept
(	O
MPSoC	B-General_Concept
)	O
.	O
</s>
<s>
In	O
October	O
2011	O
,	O
big.LITTLE	B-Architecture
was	O
announced	O
along	O
with	O
the	O
Cortex-A7	B-Application
,	O
which	O
was	O
designed	O
to	O
be	O
architecturally	B-General_Concept
compatible	O
with	O
the	O
Cortex-A15	O
.	O
</s>
<s>
In	O
October	O
2012	O
ARM	O
announced	O
the	O
Cortex-A53	O
and	O
Cortex-A57	O
(	O
ARMv8-A	O
)	O
cores	O
,	O
which	O
are	O
also	O
intercompatible	O
to	O
allow	O
their	O
use	O
in	O
a	O
big.LITTLE	B-Architecture
chip	O
.	O
</s>
<s>
ARM	O
later	O
announced	O
the	O
Cortex-A12	B-Application
at	O
Computex	O
2013	O
followed	O
by	O
the	O
Cortex-A17	B-Application
in	O
February	O
2014	O
.	O
</s>
<s>
Both	O
the	O
Cortex-A12	B-Application
and	O
the	O
Cortex-A17	B-Application
can	O
also	O
be	O
paired	O
in	O
a	O
big.LITTLE	B-Architecture
configuration	O
with	O
the	O
Cortex-A7	B-Application
.	O
</s>
<s>
For	O
a	O
given	O
library	O
of	O
CMOS	B-Device
logic	O
,	O
active	O
power	O
increases	O
as	O
the	O
logic	O
switches	O
more	O
per	O
second	O
,	O
while	O
leakage	O
increases	O
with	O
the	O
number	O
of	O
transistors	O
.	O
</s>
<s>
When	O
a	O
very	O
fast	O
out-of-order	B-General_Concept
CPU	I-General_Concept
is	O
idling	O
at	O
very	O
low	O
speeds	O
,	O
a	O
CPU	O
with	O
much	O
less	O
leakage	O
(	O
fewer	O
transistors	O
)	O
could	O
do	O
the	O
same	O
work	O
.	O
</s>
<s>
For	O
example	O
,	O
it	O
might	O
use	O
a	O
smaller	O
(	O
fewer	O
transistors	O
)	O
memory	B-General_Concept
cache	I-General_Concept
,	O
or	O
a	O
simpler	O
microarchitecture	O
such	O
as	O
a	O
pipeline	B-General_Concept
.	O
</s>
<s>
big.LITTLE	B-Architecture
is	O
a	O
way	O
to	O
optimize	O
for	O
both	O
cases	O
:	O
Power	O
and	O
speed	O
,	O
in	O
the	O
same	O
system	O
.	O
</s>
<s>
In	O
practice	O
,	O
a	O
big.LITTLE	B-Architecture
system	O
can	O
be	O
surprisingly	O
inflexible	O
.	O
</s>
<s>
These	O
may	O
not	O
match	O
the	O
standard	O
power	O
management	O
features	O
offered	O
by	O
an	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
There	O
are	O
three	O
ways	O
for	O
the	O
different	O
processor	O
cores	O
to	O
be	O
arranged	O
in	O
a	O
big.LITTLE	B-Architecture
design	O
,	O
depending	O
on	O
the	O
scheduler	O
implemented	O
in	O
the	O
kernel	B-Operating_System
.	O
</s>
<s>
The	O
operating	B-General_Concept
system	I-General_Concept
scheduler	O
can	O
only	O
see	O
one	O
cluster	O
at	O
a	O
time	O
;	O
when	O
the	O
load	B-Operating_System
on	O
the	O
whole	O
processor	O
changes	O
between	O
low	O
and	O
high	O
,	O
the	O
system	O
transitions	O
to	O
the	O
other	O
cluster	O
.	O
</s>
<s>
All	O
relevant	O
data	O
are	O
then	O
passed	O
through	O
the	O
common	O
L2	O
cache	B-General_Concept
,	O
the	O
active	O
core	O
cluster	O
is	O
powered	O
off	O
and	O
the	O
other	O
one	O
is	O
activated	O
.	O
</s>
<s>
A	O
Cache	B-Architecture
Coherent	I-Architecture
Interconnect	I-Architecture
(	O
CCI	O
)	O
is	O
used	O
.	O
</s>
<s>
This	O
model	O
has	O
been	O
implemented	O
in	O
the	O
Samsung	B-Application
Exynos	O
5	O
Octa	O
(	O
5410	O
)	O
.	O
</s>
<s>
CPU	O
migration	O
via	O
the	O
in-kernel	O
switcher	O
(	O
IKS	O
)	O
involves	O
pairing	O
up	O
a	O
'	O
big	O
 '	O
core	O
with	O
a	O
'	O
LITTLE	O
 '	O
core	O
,	O
with	O
possibly	O
many	B-General_Concept
identical	O
pairs	O
in	O
one	O
chip	O
.	O
</s>
<s>
When	O
demand	O
on	O
the	O
virtual	O
core	O
changes	O
(	O
between	O
high	O
and	O
low	O
)	O
,	O
the	O
incoming	O
core	O
is	O
powered	O
up	O
,	O
running	B-Operating_System
state	I-Operating_System
is	I-Operating_System
transferred	I-Operating_System
,	O
the	O
outgoing	O
is	O
shut	O
down	O
,	O
and	O
processing	O
continues	O
on	O
the	O
new	O
core	O
.	O
</s>
<s>
Switching	O
is	O
done	O
via	O
the	O
cpufreq	B-General_Concept
framework	O
.	O
</s>
<s>
A	O
complete	O
big.LITTLE	B-Architecture
IKS	O
implementation	O
was	O
added	O
in	O
Linux	O
3.11	O
.	O
big.LITTLE	B-Architecture
IKS	O
is	O
an	O
improvement	O
of	O
cluster	O
migration	O
(	O
)	O
,	O
the	O
main	O
difference	O
being	O
that	O
each	O
pair	O
is	O
visible	O
to	O
the	O
scheduler	O
.	O
</s>
<s>
A	O
single	O
chip	O
could	O
have	O
one	O
or	O
two	O
'	O
big	O
 '	O
cores	O
and	O
many	B-General_Concept
more	O
'	O
LITTLE	O
 '	O
cores	O
,	O
or	O
vice	O
versa	O
.	O
</s>
<s>
Nvidia	O
created	O
something	O
similar	O
to	O
this	O
with	O
the	O
low-power	O
'	O
companion	O
core	O
 '	O
in	O
their	O
Tegra	O
3	O
System-on-Chip	B-Architecture
.	O
</s>
<s>
The	O
most	O
powerful	O
use	O
model	O
of	O
big.LITTLE	B-Architecture
architecture	O
is	O
Heterogeneous	O
Multi-Processing	B-Operating_System
(	O
HMP	O
)	O
,	O
which	O
enables	O
the	O
use	O
of	O
all	O
physical	O
cores	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
Threads	B-Operating_System
with	O
high	O
priority	O
or	O
computational	O
intensity	O
can	O
in	O
this	O
case	O
be	O
allocated	O
to	O
the	O
"	O
big	O
"	O
cores	O
while	O
threads	B-Operating_System
with	O
less	O
priority	O
or	O
less	O
computational	O
intensity	O
,	O
such	O
as	O
background	O
tasks	O
,	O
can	O
be	O
performed	O
by	O
the	O
"	O
LITTLE	O
"	O
cores	O
.	O
</s>
<s>
This	O
model	O
has	O
been	O
implemented	O
in	O
the	O
Samsung	B-Application
Exynos	O
starting	O
with	O
the	O
Exynos	O
5	O
Octa	O
series	O
(	O
5420	O
,	O
5422	O
,	O
5430	O
)	O
,	O
and	O
Apple	O
A	O
series	O
processors	O
starting	O
with	O
the	O
Apple	B-Device
A11	I-Device
.	O
</s>
<s>
The	O
paired	O
arrangement	O
allows	O
for	O
switching	O
to	O
be	O
done	O
transparently	O
to	O
the	O
operating	B-General_Concept
system	I-General_Concept
using	O
the	O
existing	O
dynamic	B-General_Concept
voltage	I-General_Concept
and	I-General_Concept
frequency	I-General_Concept
scaling	I-General_Concept
(	O
DVFS	O
)	O
facility	O
.	O
</s>
<s>
The	O
existing	O
DVFS	O
support	O
in	O
the	O
kernel	B-Operating_System
(	O
e.g.	O
</s>
<s>
cpufreq	B-General_Concept
in	O
Linux	O
)	O
will	O
simply	O
see	O
a	O
list	O
of	O
frequencies/voltages	O
and	O
will	O
switch	O
between	O
them	O
as	O
it	O
sees	O
fit	O
,	O
just	O
like	O
it	O
does	O
on	O
the	O
existing	O
hardware	O
.	O
</s>
<s>
Alternatively	O
,	O
all	O
the	O
cores	O
may	O
be	O
exposed	O
to	O
the	O
kernel	B-Operating_System
scheduler	O
,	O
which	O
will	O
decide	O
where	O
each	O
process/thread	O
is	O
executed	O
.	O
</s>
<s>
It	O
poses	O
unique	O
problems	O
for	O
the	O
kernel	B-Operating_System
scheduler	O
,	O
which	O
,	O
at	O
least	O
with	O
modern	O
commodity	O
hardware	O
,	O
has	O
been	O
able	O
to	O
assume	O
all	O
cores	O
in	O
a	O
SMP	B-Operating_System
system	O
are	O
equal	O
rather	O
than	O
heterogeneous	O
.	O
</s>
<s>
Because	O
the	O
scheduler	O
is	O
directly	O
migrating	O
tasks	O
between	O
cores	O
,	O
kernel	B-Operating_System
overhead	O
is	O
reduced	O
and	O
power	O
savings	O
can	O
be	O
correspondingly	O
increased	O
.	O
</s>
<s>
Implementation	O
in	O
the	O
scheduler	O
also	O
makes	O
switching	O
decisions	O
faster	O
than	O
in	O
the	O
cpufreq	B-General_Concept
framework	O
implemented	O
in	O
IKS	O
.	O
</s>
<s>
with	O
2	O
Cortex-A15	O
cores	O
and	O
4	O
Cortex-A7	B-Application
cores	O
)	O
.	O
</s>
<s>
In	O
May	O
2017	O
,	O
ARM	O
announced	O
as	O
the	O
successor	O
to	O
big.LITTLE	B-Architecture
.	O
</s>
<s>
DynamIQ	O
is	O
expected	O
to	O
allow	O
for	O
more	O
flexibility	O
and	O
scalability	O
when	O
designing	O
multi-core	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
In	O
contrast	O
to	O
big.LITTLE	B-Architecture
,	O
it	O
increases	O
the	O
maximum	O
number	O
of	O
cores	O
in	O
a	O
cluster	O
to	O
8	O
,	O
allows	O
for	O
varying	O
core	O
designs	O
within	O
a	O
single	O
cluster	O
,	O
and	O
up	O
to	O
32	O
total	O
clusters	O
.	O
</s>
<s>
The	O
technology	O
also	O
offers	O
more	O
fine	O
grained	O
per	O
core	O
voltage	O
control	O
and	O
faster	O
L2	O
cache	B-General_Concept
speeds	O
.	O
</s>
<s>
However	O
,	O
DynamIQ	O
is	O
incompatible	O
with	O
previous	O
ARM	O
designs	O
and	O
is	O
initially	O
only	O
supported	O
by	O
the	O
Cortex-A75	O
and	O
Cortex-A55	O
CPU	B-Architecture
cores	I-Architecture
.	O
</s>
