<s>
The	O
ARM	B-Application
Cortex-A9	I-Application
MPCore	I-Application
is	O
a	O
32-bit	O
multi-core	O
processor	O
that	O
provides	O
up	O
to	O
4	O
cache-coherent	O
cores	O
,	O
each	O
implementing	O
the	O
ARM	O
v7	O
architecture	O
instruction	O
set	O
.	O
</s>
<s>
Key	O
features	O
of	O
the	O
Cortex-A9	B-Application
core	O
are	O
:	O
</s>
<s>
Out-of-order	B-General_Concept
speculative	B-General_Concept
issue	I-General_Concept
superscalar	B-General_Concept
execution	I-General_Concept
8-stage	O
pipeline	B-General_Concept
giving	O
2.50DMIPS/MHz/core	O
.	O
</s>
<s>
NEON	O
SIMD	B-Device
instruction	O
set	O
extension	O
performing	O
up	O
to	O
16	O
operations	O
per	O
instruction	O
(	O
optional	O
)	O
.	O
</s>
<s>
Jazelle	B-Language
DBX	O
support	O
for	O
Java	O
execution	O
.	O
</s>
<s>
Jazelle	B-Language
RCT	O
for	O
JIT	O
compilation	O
.	O
</s>
<s>
Several	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
(	O
SoC	O
)	O
devices	O
implement	O
the	O
Cortex-A9	B-Application
core	O
,	O
including	O
:	O
</s>
