<s>
The	O
Socket	O
G3	O
,	O
originally	O
as	O
part	O
of	O
the	O
codenamed	O
Piranha	O
server	O
platform	O
,	O
was	O
supposed	O
to	O
be	O
the	O
intermediate	O
successor	O
to	O
Socket	O
F	O
and	O
Socket	O
F+	O
to	O
be	O
used	O
in	O
AMD	B-General_Concept
Opteron	I-General_Concept
processor	O
for	O
dual-processor	O
(	O
2P	O
)	O
and	O
above	O
server	O
platforms	O
scheduled	O
to	O
be	O
launched	O
2009	O
.	O
</s>
<s>
The	O
Socket	O
G3	O
would	O
have	O
been	O
accompanied	O
by	O
the	O
Socket	B-Device
G3	I-Device
Memory	I-Device
Extender	I-Device
(	O
Socket	O
G3MX	B-Device
)	O
,	O
for	O
connecting	O
large	O
amounts	O
of	O
memory	O
to	O
a	O
single	O
microprocessor	O
by	O
a	O
G3MX	B-Device
chip	O
placed	O
on	O
the	O
motherboard	O
.	O
</s>
<s>
AMD	O
had	O
planned	O
socket	O
G3	O
to	O
arrive	O
with	O
the	O
advent	O
of	O
the	O
previously	O
planned	O
8-core	O
MCM	B-Algorithm
chip	O
code	O
named	O
Montreal	O
.	O
</s>
<s>
Since	O
Q1	O
2008	O
,	O
the	O
plan	O
for	O
and	O
8-core	O
MCM	B-Algorithm
server	O
chip	O
based	O
on	O
45nm	O
K10.5	O
design	O
has	O
been	O
scrapped	O
in	O
favor	O
of	O
a	O
6-core	O
fully	O
integrated	O
MPU	B-General_Concept
design	O
code	O
named	O
Istanbul	O
,	O
which	O
would	O
use	O
the	O
existing	O
socket	O
F/F	O
+	O
platform	O
,	O
produced	O
by	O
Nvidia	O
,	O
Broadcom	O
,	O
as	O
well	O
as	O
Fiorano	O
to	O
be	O
introduced	O
by	O
AMD	O
in	O
2009	O
.	O
</s>
<s>
The	O
socket	O
that	O
was	O
the	O
successor	O
to	O
the	O
Socket	O
F	O
is	O
the	O
LGA	B-Algorithm
1974-pin	O
Socket	O
G34	O
.	O
</s>
