<s>
The	O
AMD	B-General_Concept
Am29000	I-General_Concept
,	O
commonly	O
shortened	O
to	O
29k	B-General_Concept
,	O
is	O
a	O
family	O
of	O
32-bit	O
RISC	B-Architecture
microprocessors	B-Architecture
and	O
microcontrollers	B-Architecture
developed	O
and	O
fabricated	O
by	O
Advanced	O
Micro	O
Devices	O
(	O
AMD	O
)	O
.	O
</s>
<s>
Based	O
on	O
the	O
seminal	O
Berkeley	B-General_Concept
RISC	I-General_Concept
,	O
the	O
29k	B-General_Concept
added	O
a	O
number	O
of	O
significant	O
improvements	O
.	O
</s>
<s>
They	O
were	O
,	O
for	O
a	O
time	O
,	O
the	O
most	O
popular	O
RISC	B-Architecture
chips	O
on	O
the	O
market	O
,	O
widely	O
used	O
in	O
laser	O
printers	O
from	O
a	O
variety	O
of	O
manufacturers	O
.	O
</s>
<s>
Developed	O
since	O
1984	O
–	O
1985	O
,	O
announced	O
in	O
March	O
1987	O
and	O
released	O
in	O
May	O
1988	O
,	O
the	O
initial	O
Am29000	B-General_Concept
was	O
followed	O
by	O
several	O
versions	O
,	O
ending	O
with	O
the	O
Am29040	O
in	O
1995	O
.	O
</s>
<s>
The	O
29050	O
was	O
notable	O
for	O
being	O
early	O
to	O
feature	O
a	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
capable	O
of	O
executing	O
one	O
multiply	B-Algorithm
–	I-Algorithm
add	I-Algorithm
operation	I-Algorithm
per	O
cycle	O
.	O
</s>
<s>
AMD	O
was	O
designing	O
a	O
superscalar	B-General_Concept
version	O
until	O
late	O
1995	O
,	O
when	O
AMD	O
dropped	O
the	O
development	O
of	O
the	O
29k	B-General_Concept
because	O
the	O
design	O
team	O
was	O
transferred	O
to	O
support	O
the	O
PC	O
(	O
x86	B-Operating_System
)	O
side	O
of	O
the	O
business	O
.	O
</s>
<s>
What	O
remained	O
of	O
AMD	O
's	O
embedded	O
business	O
was	O
realigned	O
towards	O
the	O
embedded	O
186	B-Device
family	O
of	O
80186	B-Device
derivatives	O
.	O
</s>
<s>
By	O
then	O
the	O
majority	O
of	O
AMD	O
's	O
resources	O
were	O
concentrated	O
on	O
their	O
high-performance	O
x86	B-Operating_System
processors	O
for	O
desktop	O
PCs	O
,	O
using	O
many	O
of	O
the	O
ideas	O
and	O
individual	O
parts	O
of	O
the	O
29k	B-General_Concept
designs	O
to	O
produce	O
the	O
AMD	O
K5	O
.	O
</s>
<s>
The	O
29000	O
evolved	O
from	O
the	O
same	O
Berkeley	B-General_Concept
RISC	I-General_Concept
design	O
that	O
also	O
led	O
to	O
the	O
Sun	B-Architecture
SPARC	I-Architecture
,	O
Intel	B-General_Concept
i960	I-General_Concept
,	O
ARM	B-Architecture
and	O
RISC-V	B-Device
.	O
</s>
<s>
One	O
design	O
element	O
used	O
in	O
some	O
of	O
the	O
Berkeley	O
RISC-derived	O
designs	O
is	O
the	O
concept	O
of	O
register	B-General_Concept
windows	I-General_Concept
,	O
a	O
technique	O
used	O
to	O
speed	O
up	O
procedure	O
calls	O
significantly	O
.	O
</s>
<s>
The	O
idea	O
is	O
to	O
use	O
a	O
large	O
set	O
of	O
registers	B-General_Concept
as	O
a	O
stack	O
,	O
loading	O
local	O
data	O
into	O
a	O
set	O
of	O
registers	B-General_Concept
during	O
a	O
call	O
,	O
and	O
marking	O
them	O
"	O
dead	O
"	O
when	O
the	O
procedure	B-Language
returns	I-Language
.	O
</s>
<s>
Values	O
being	O
returned	O
from	O
the	O
routines	O
would	O
be	O
placed	O
in	O
the	O
"	O
global	O
page	O
"	O
,	O
the	O
top	O
eight	O
registers	B-General_Concept
in	O
the	O
SPARC	B-Architecture
(	O
for	O
instance	O
)	O
.	O
</s>
<s>
The	O
competing	O
early	O
RISC	B-Architecture
design	O
from	O
Stanford	O
University	O
,	O
the	O
Stanford	B-General_Concept
MIPS	I-General_Concept
,	O
also	O
looked	O
at	O
this	O
concept	O
but	O
decided	O
that	O
improved	O
compilers	O
could	O
make	O
more	O
efficient	O
use	O
of	O
general	O
purpose	O
registers	B-General_Concept
than	O
a	O
hard-wired	O
window	O
.	O
</s>
<s>
In	O
the	O
original	O
Berkeley	O
design	O
,	O
SPARC	B-Architecture
,	O
and	O
i960	B-General_Concept
,	O
the	O
windows	O
were	O
fixed	O
in	O
size	O
.	O
</s>
<s>
A	O
routine	O
using	O
only	O
one	O
local	O
variable	O
would	O
still	O
use	O
up	O
eight	O
registers	B-General_Concept
on	O
the	O
SPARC	B-Architecture
,	O
wasting	O
this	O
expensive	O
resource	O
.	O
</s>
<s>
In	O
this	O
example	O
only	O
two	O
registers	B-General_Concept
would	O
be	O
used	O
,	O
one	O
for	O
the	O
local	O
variable	O
,	O
another	O
for	O
the	O
return	B-Language
address	I-Language
.	O
</s>
<s>
It	O
also	O
added	O
more	O
registers	B-General_Concept
,	O
including	O
the	O
same	O
128	O
registers	B-General_Concept
for	O
the	O
procedure	O
stack	O
,	O
but	O
adding	O
another	O
64	O
for	O
global	O
access	O
.	O
</s>
<s>
In	O
comparison	O
,	O
the	O
SPARC	B-Architecture
had	O
128	O
registers	B-General_Concept
in	O
total	O
,	O
and	O
the	O
global	O
set	O
was	O
a	O
standard	O
window	O
of	O
eight	O
.	O
</s>
<s>
The	O
29000	O
also	O
extended	O
the	O
register	B-General_Concept
window	I-General_Concept
stack	O
with	O
an	O
in-memory	O
(	O
and	O
in	O
theory	O
,	O
in-cache	O
)	O
stack	O
.	O
</s>
<s>
A	O
Branch	O
Target	O
Cache	O
(	O
512	O
bytes	O
on	O
the	O
29000	O
and	O
1024	O
bytes	O
on	O
the	O
29050	O
)	O
stored	O
sets	O
of	O
4	O
or	O
2	O
sequential	O
instructions	O
found	O
at	O
the	O
branch	O
target	O
address	O
,	O
reducing	O
the	O
instruction	O
fetch	O
latency	O
during	O
taken	O
branchesthe	O
29000	O
did	O
not	O
include	O
any	O
branch	B-General_Concept
prediction	I-General_Concept
system	I-General_Concept
so	O
there	O
was	O
a	O
delay	O
if	O
a	O
branch	O
was	O
taken	O
.	O
</s>
<s>
The	O
first	O
Am29000	B-General_Concept
was	O
released	O
in	O
1988	O
,	O
including	O
a	O
built-in	O
MMU	B-General_Concept
but	O
floating	B-Algorithm
point	I-Algorithm
support	O
was	O
offloaded	O
to	O
the	O
Am29027	O
FPU	B-General_Concept
.	O
</s>
<s>
Units	O
with	O
failed	O
MMU	B-General_Concept
or	O
Branch	O
Target	O
Cache	O
were	O
sold	O
as	O
the	O
Am29005	O
.	O
</s>
<s>
By	O
then	O
the	O
Am29050	O
had	O
also	O
become	O
available	O
,	O
without	O
on-chip	O
cache	O
but	O
featuring	O
a	O
floating-point	B-General_Concept
unit	I-General_Concept
with	O
fully	O
pipelined	O
multiply	B-Algorithm
–	I-Algorithm
accumulate	I-Algorithm
operations	I-Algorithm
,	O
a	O
larger	O
1KB	O
Branch	O
Target	O
Cache	O
with	O
a	O
claimed	O
80%	O
hit	O
rate	O
,	O
and	O
better-pipelined	O
load	O
operations	O
sped	O
up	O
by	O
a	O
4-entry	O
TLB-like	O
Physical	O
Address	O
Cache	O
.	O
</s>
<s>
Though	O
it	O
is	O
not	O
a	O
superscalar	B-General_Concept
processor	I-General_Concept
,	O
it	O
permits	O
a	O
floating-point	B-Algorithm
operation	O
and	O
an	O
integer	O
operation	O
to	O
complete	O
at	O
the	O
same	O
cycle	O
.	O
</s>
<s>
The	O
integer	O
and	O
floating-point	B-Algorithm
sides	O
each	O
have	O
an	O
own	O
write	O
port	O
to	O
the	O
registers	B-General_Concept
.	O
</s>
<s>
A	O
superscalar	B-General_Concept
version	O
of	O
29K	B-General_Concept
was	O
being	O
designed	O
,	O
but	O
canceled	O
in	O
favor	O
of	O
x86	B-Operating_System
.	O
</s>
<s>
It	O
was	O
an	O
advanced	O
design	O
,	O
capable	O
of	O
four-way	O
dispatch	O
into	O
six	O
reservation	B-General_Concept
stations	I-General_Concept
and	O
speculative	B-General_Concept
out-of-order	B-General_Concept
execution	I-General_Concept
of	O
instructions	O
,	O
with	O
four-way	O
retire	O
.	O
</s>
<s>
It	O
had	O
no	O
on-chip	O
FPU	B-General_Concept
due	O
to	O
cost	O
reasons	O
and	O
the	O
target	O
market	O
.	O
</s>
<s>
AMD	O
used	O
the	O
unreleased	O
29K	B-General_Concept
microarchitecture	O
as	O
the	O
basis	O
of	O
the	O
K5	O
series	O
of	O
x86-compatible	O
processors	O
.	O
</s>
<s>
The	O
ALUs	O
were	O
carried	O
over	O
,	O
as	O
was	O
the	O
re-order	B-General_Concept
buffer	I-General_Concept
with	O
a	O
slight	O
modification	O
.	O
</s>
<s>
The	O
FPU	B-General_Concept
was	O
taken	O
from	O
the	O
29050	O
,	O
but	O
extended	O
to	O
80	O
bits	O
precision	O
.	O
</s>
<s>
The	O
K5	O
translated	O
the	O
x86	B-Operating_System
instructions	O
into	O
"	O
RISC-OPs	O
"	O
upon	O
decoding	O
,	O
aided	O
by	O
the	O
predecode	O
information	O
held	O
of	O
the	O
cached	O
instructions	O
.	O
</s>
<s>
AMD	O
claimed	O
that	O
the	O
superscalar	B-General_Concept
29K	B-General_Concept
would	O
have	O
only	O
a	O
slightly	O
lower	O
performance	O
than	O
the	O
K5	O
,	O
but	O
much	O
lower	O
cost	O
due	O
to	O
the	O
size	O
difference	O
.	O
</s>
