<s>
An	O
Advanced	B-Algorithm
Encryption	I-Algorithm
Standard	I-Algorithm
instruction	B-General_Concept
set	I-General_Concept
is	O
now	O
integrated	O
into	O
many	O
processors	O
.	O
</s>
<s>
The	O
purpose	O
of	O
the	O
instruction	B-General_Concept
set	I-General_Concept
is	O
to	O
improve	O
the	O
speed	O
and	O
security	O
of	O
applications	O
performing	O
encryption	O
and	O
decryption	O
using	O
Advanced	B-Algorithm
Encryption	I-Algorithm
Standard	I-Algorithm
(	O
AES	B-Algorithm
)	O
.	O
</s>
<s>
They	O
are	O
often	O
implemented	O
as	O
instructions	O
implementing	O
a	O
single	O
round	O
of	O
AES	B-Algorithm
along	O
with	O
a	O
special	O
version	O
for	O
the	O
last	O
round	O
which	O
has	O
a	O
slightly	O
different	O
method	O
.	O
</s>
<s>
The	O
side	O
channel	O
attack	O
surface	O
of	O
AES	B-Algorithm
is	O
reduced	O
when	O
implemented	O
in	O
an	O
instruction	B-General_Concept
set	I-General_Concept
,	O
compared	O
to	O
when	O
AES	B-Algorithm
is	O
implemented	O
in	O
software	O
only	O
.	O
</s>
<s>
AES-NI	O
(	O
or	O
the	O
Intel	O
Advanced	B-Algorithm
Encryption	I-Algorithm
Standard	I-Algorithm
New	O
Instructions	O
;	O
AES-NI	O
)	O
was	O
the	O
first	O
major	O
implementation	O
.	O
</s>
<s>
AES-NI	O
is	O
an	O
extension	O
to	O
the	O
x86	B-Operating_System
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
for	O
microprocessors	B-Architecture
from	O
Intel	O
and	O
AMD	O
proposed	O
by	O
Intel	O
in	O
March	O
2008	O
.	O
</s>
<s>
The	O
following	O
Intel	O
processors	O
support	O
the	O
AES-NI	O
instruction	B-General_Concept
set	I-General_Concept
:	O
</s>
<s>
Westmere	B-Device
based	O
processors	O
,	O
specifically	O
:	O
</s>
<s>
Westmere-EP	O
(	O
a.k.a.	O
</s>
<s>
Sandy	B-Device
Bridge	I-Device
processors	O
:	O
</s>
<s>
Several	O
vendors	O
have	O
shipped	O
BIOS	B-Operating_System
configurations	O
with	O
the	O
extension	O
disabled	O
;	O
a	O
BIOS	B-Operating_System
update	O
is	O
required	O
to	O
enable	O
them	O
.	O
</s>
<s>
Several	O
AMD	O
processors	O
support	O
AES	B-Algorithm
instructions	O
:	O
</s>
<s>
AES	B-Algorithm
support	O
with	O
unprivileged	O
processor	O
instructions	O
is	O
also	O
available	O
in	O
the	O
latest	O
SPARC	B-Architecture
processors	O
(	O
T3	B-Device
,	O
T4	B-Device
,	O
T5	B-Device
,	O
M5	O
,	O
and	O
forward	O
)	O
and	O
in	O
latest	O
ARM	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
The	O
SPARC	B-Device
T4	I-Device
processor	O
,	O
introduced	O
in	O
2011	O
,	O
has	O
user-level	O
instructions	O
implementing	O
AES	B-Algorithm
rounds	O
.	O
</s>
<s>
The	O
ARMv8-A	O
processor	O
architecture	O
,	O
announced	O
in	O
2011	O
,	O
including	O
the	O
ARM	B-Architecture
Cortex-A53	O
and	O
A57	O
(	O
but	O
not	O
previous	O
v7	O
processors	O
like	O
the	O
Cortex	O
A5	O
,	O
7	O
,	O
8	O
,	O
9	O
,	O
11	O
,	O
15	O
)	O
also	O
have	O
user-level	O
instructions	O
which	O
implement	O
AES	B-Algorithm
rounds	O
.	O
</s>
<s>
VIA	B-Device
x86	I-Device
CPUs	I-Device
,	O
AMD	B-Device
Geode	I-Device
,	O
and	O
Marvell	O
Kirkwood	O
(	O
ARM	B-Architecture
,	O
mv_cesa	O
in	O
Linux	O
)	O
use	O
driver-based	O
accelerated	O
AES	B-Algorithm
handling	O
instead	O
.	O
</s>
<s>
(	O
See	O
Crypto	B-Application
API	I-Application
(	O
Linux	O
)	O
.	O
)	O
</s>
<s>
The	O
following	O
chips	O
,	O
while	O
supporting	O
AES	B-Algorithm
hardware	O
acceleration	O
,	O
do	O
not	O
support	O
AES-NI	O
:	O
</s>
<s>
Programming	O
information	O
is	O
available	O
in	O
ARM	B-Architecture
Architecture	I-Architecture
Reference	O
Manual	O
ARMv8	O
,	O
for	O
ARMv8-A	O
architecture	O
profile	O
(	O
Section	O
A2.3	O
"	O
The	O
Armv8	O
Cryptographic	O
Extension	O
"	O
)	O
.	O
</s>
<s>
Whilst	O
the	O
RISC-V	B-Device
architecture	I-Device
does	O
not	O
include	O
AES-specific	O
instructions	O
,	O
a	O
number	O
of	O
RISC-V	B-Device
chips	O
include	O
integrated	O
AES	B-Algorithm
co-processors	O
.	O
</s>
<s>
Dual-core	O
RISC-V	B-Device
64	O
bits	O
Sipeed-M1	O
support	O
AES	B-Algorithm
and	O
SHA256	O
.	O
</s>
<s>
RISC-V	B-Device
architecture	I-Device
based	O
ESP32-C	O
(	O
as	O
well	O
as	O
Xtensa-based	O
ESP32	B-Device
)	O
,	O
support	O
AES	B-Algorithm
,	O
SHA	O
,	O
RSA	O
,	O
RNG	O
,	O
HMAC	O
,	O
digital	O
signature	O
and	O
XTS	O
128	O
for	O
flash	O
.	O
</s>
<s>
Bouffalo	O
Labs	O
BL602/604	O
32-bit	O
RISC-V	B-Device
supports	O
various	O
AES	B-Algorithm
and	O
SHA	O
variants	O
.	O
</s>
<s>
Since	O
the	O
Power	O
ISA	O
v.2.07	O
,	O
the	O
instructions	O
vcipher	O
and	O
vcipyherlast	O
implement	O
one	O
round	O
of	O
AES	B-Algorithm
directly	O
.	O
</s>
<s>
IBM	O
z9	O
or	O
later	O
mainframe	O
processors	O
support	O
AES	B-Algorithm
as	O
single-opcode	O
(	O
KM	O
,	O
KMC	O
)	O
AES	B-Algorithm
ECB/CBC	O
instructions	O
via	O
IBM	O
's	O
CryptoExpress	O
hardware	O
.	O
</s>
<s>
These	O
single-instruction	O
AES	B-Algorithm
versions	O
are	O
therefore	O
easier	O
to	O
use	O
than	O
Intel	O
NI	O
ones	O
,	O
but	O
may	O
not	O
be	O
extended	O
to	O
implement	O
other	O
algorithms	O
based	O
on	O
AES	B-Algorithm
round	O
functions	O
(	O
such	O
as	O
the	O
Whirlpool	B-Algorithm
and	O
Grøstl	B-Algorithm
hash	O
functions	O
)	O
.	O
</s>
<s>
SPARC	B-Device
T3	I-Device
and	O
later	O
processors	O
have	O
hardware	O
support	O
for	O
several	O
cryptographic	O
algorithms	O
,	O
including	O
AES	B-Algorithm
.	O
</s>
<s>
Cavium	O
Octeon	O
MIPS	O
All	O
Cavium	O
Octeon	O
MIPS-based	O
processors	O
have	O
hardware	O
support	O
for	O
several	O
cryptographic	O
algorithms	O
,	O
including	O
AES	B-Algorithm
using	O
special	O
coprocessor	O
3	O
instructions	O
.	O
</s>
<s>
In	O
AES-NI	O
Performance	O
Analyzed	O
,	O
Patrick	O
Schmid	O
and	O
Achim	O
Roos	O
found	O
"	O
impressive	O
results	O
from	O
a	O
handful	O
of	O
applications	O
already	O
optimized	O
to	O
take	O
advantage	O
of	O
Intel	O
's	O
AES-NI	O
capability	O
"	O
.	O
</s>
<s>
A	O
performance	O
analysis	O
using	O
the	O
Crypto++	B-Language
security	B-Library
library	I-Library
showed	O
an	O
increase	O
in	O
throughput	O
from	O
approximately	O
28.0	O
cycles	O
per	O
byte	O
to	O
3.5	O
cycles	O
per	O
byte	O
with	O
AES/GCM	O
versus	O
a	O
Pentium	B-General_Concept
4	I-General_Concept
with	O
no	O
acceleration	O
.	O
</s>
<s>
Most	O
modern	O
compilers	O
can	O
emit	O
AES	B-Algorithm
instructions	O
.	O
</s>
<s>
Much	O
security	O
and	O
cryptography	O
software	O
supports	O
the	O
AES	B-Algorithm
instruction	I-Algorithm
set	I-Algorithm
,	O
including	O
the	O
following	O
notable	O
core	O
infrastructure	O
:	O
</s>
<s>
A	O
fringe	O
use	O
of	O
the	O
AES	B-Algorithm
instruction	I-Algorithm
set	I-Algorithm
involves	O
using	O
it	O
on	O
block	O
ciphers	O
with	O
a	O
similarly-structured	O
S-box	B-Algorithm
,	O
using	O
affine	O
isomorphism	O
to	O
convert	O
between	O
the	O
two	O
.	O
</s>
<s>
SM4	B-Algorithm
and	O
Camellia	B-Algorithm
have	O
been	O
accelerated	O
using	O
AES-NI	O
.	O
</s>
