<s>
In	O
semiconductor	B-Architecture
manufacturing	I-Architecture
,	O
the	O
International	O
Technology	O
Roadmap	O
for	O
Semiconductors	O
defines	O
the	O
7	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
as	O
the	O
MOSFET	B-Architecture
technology	O
node	O
following	O
the	O
10	B-Algorithm
nm	I-Algorithm
node	O
.	O
</s>
<s>
It	O
is	O
based	O
on	O
FinFET	O
(	O
fin	O
field-effect	O
transistor	O
)	O
technology	O
,	O
a	O
type	O
of	O
multi-gate	B-Algorithm
MOSFET	I-Algorithm
technology	O
.	O
</s>
<s>
Taiwan	O
Semiconductor	B-Architecture
Manufacturing	I-Architecture
Company	O
(	O
TSMC	O
)	O
began	O
production	O
of	O
256Mbit	O
SRAM	B-Architecture
memory	O
chips	O
using	O
a	O
7nm	B-Algorithm
process	O
called	O
N7	O
in	O
June	O
2016	O
,	O
before	O
Samsung	B-Application
began	O
mass	O
production	O
of	O
their	O
7nm	B-Algorithm
process	O
called	O
7LPP	O
devices	O
in	O
2018	O
.	O
</s>
<s>
The	O
first	O
mainstream	O
7nm	B-Algorithm
mobile	O
processor	O
intended	O
for	O
mass	O
market	O
use	O
,	O
the	O
Apple	B-Device
A12	I-Device
Bionic	I-Device
,	O
was	O
released	O
at	O
Apple	O
's	O
September	O
2018	O
event	O
.	O
</s>
<s>
Although	O
Huawei	O
announced	O
its	O
own	O
7nm	B-Algorithm
processor	O
before	O
the	O
Apple	B-Device
A12	I-Device
Bionic	I-Device
,	O
the	O
Kirin	O
980	O
on	O
August	O
31	O
,	O
2018	O
,	O
the	O
Apple	B-Device
A12	I-Device
Bionic	I-Device
was	O
released	O
for	O
public	O
,	O
mass	O
market	O
use	O
to	O
consumers	O
before	O
the	O
Kirin	O
980	O
.	O
</s>
<s>
However	O
,	O
the	O
I/O	O
die	O
on	O
the	O
Rome	O
multi-chip	B-Algorithm
module	I-Algorithm
(	O
MCM	O
)	O
is	O
fabricated	O
with	O
the	O
GlobalFoundries	O
 '	O
14nm	O
(	O
14HP	O
)	O
process	O
,	O
while	O
the	O
Matisse	O
's	O
I/O	O
die	O
uses	O
the	O
GlobalFoundries	O
 '	O
12nm	O
(	O
12LP+	O
)	O
process	O
.	O
</s>
<s>
The	O
Radeon	B-Device
RX	I-Device
5000	I-Device
series	I-Device
is	O
also	O
based	O
on	O
TSMC	O
's	O
N7	O
process	O
.	O
</s>
<s>
TSMC	O
and	O
Samsung	B-Application
's	O
10nm	B-Algorithm
(	O
10	O
LPE	O
)	O
processes	O
are	O
somewhere	O
between	O
Intel	O
's	O
14nm	O
and	O
10nm	B-Algorithm
processes	O
in	O
transistor	O
density	O
.	O
</s>
<s>
7nm	B-Algorithm
scale	O
MOSFETs	B-Architecture
were	O
first	O
demonstrated	O
by	O
researchers	O
in	O
the	O
early	O
2000s	O
.	O
</s>
<s>
In	O
2002	O
,	O
an	O
IBM	O
research	O
team	O
including	O
Bruce	O
Doris	O
,	O
Omer	O
Dokumaci	O
,	O
Meikei	O
Ieong	O
and	O
Anda	O
Mocuta	O
fabricated	O
a	O
6nm	O
silicon-on-insulator	B-Algorithm
(	O
SOI	O
)	O
MOSFET	B-Architecture
.	O
</s>
<s>
In	O
2003	O
,	O
NEC	O
's	O
research	O
team	O
led	O
by	O
Hitoshi	O
Wakabayashi	O
and	O
Shigeharu	O
Yamagami	O
fabricated	O
a	O
5	O
nm	O
MOSFET	B-Architecture
.	O
</s>
<s>
In	O
July	O
2015	O
,	O
IBM	O
announced	O
that	O
they	O
had	O
built	O
the	O
first	O
functional	O
transistors	O
with	O
7nm	B-Algorithm
technology	O
,	O
using	O
a	O
silicon-germanium	O
process	O
.	O
</s>
<s>
In	O
June	O
2016	O
,	O
TSMC	O
had	O
produced	O
256Mbit	O
SRAM	B-Architecture
memory	O
cells	O
at	O
their	O
7nm	B-Algorithm
process	O
,	O
with	O
a	O
cell	O
area	O
of	O
0.027square	O
micrometers	O
(	O
550F2	O
)	O
with	O
reasonable	O
risk	O
production	O
yields	O
.	O
</s>
<s>
In	O
April	O
2016	O
,	O
TSMC	O
announced	O
that	O
7nm	B-Algorithm
trial	O
production	O
would	O
begin	O
in	O
the	O
first	O
half	O
of	O
2017	O
.	O
</s>
<s>
In	O
April	O
2017	O
,	O
TSMC	O
began	O
risk	O
production	O
of	O
256Mbit	O
SRAM	B-Architecture
memory	O
chips	O
using	O
a	O
7nm	B-Algorithm
(	O
N7FF+	O
)	O
process	O
,	O
with	O
extreme	B-Algorithm
ultraviolet	I-Algorithm
lithography	I-Algorithm
(	O
EUV	O
)	O
.	O
</s>
<s>
TSMC	O
's	O
7nm	B-Algorithm
production	O
plans	O
,	O
as	O
of	O
early	O
2017	O
,	O
were	O
to	O
use	O
deep	O
ultraviolet	O
(	O
DUV	O
)	O
immersion	O
lithography	O
initially	O
on	O
this	O
process	O
node	O
(	O
N7FF	O
)	O
,	O
and	O
transition	O
from	O
risk	O
to	O
commercial	O
volume	O
manufacturing	O
from	O
Q2	O
2017	O
to	O
Q2	O
2018	O
.	O
</s>
<s>
Also	O
,	O
their	O
later	O
generation	O
7nm	B-Algorithm
(	O
N7FF+	O
)	O
production	O
is	O
planned	O
to	O
use	O
EUV	O
multiple	B-Algorithm
patterning	I-Algorithm
and	O
to	O
have	O
an	O
estimated	O
transition	O
from	O
risk	O
to	O
volume	O
manufacturing	O
between	O
2018	O
and	O
2019	O
.	O
</s>
<s>
In	O
February	O
2017	O
,	O
Intel	O
announced	O
Fab	O
42	O
in	O
Chandler	O
,	O
Arizona	O
will	O
produce	O
microprocessors	O
using	O
7nm	B-Algorithm
(	O
Intel	O
4	O
)	O
manufacturing	O
process	O
.	O
</s>
<s>
In	O
April	O
2018	O
,	O
TSMC	O
announced	O
volume	O
production	O
of	O
7nm	B-Algorithm
(	O
CLN7FF	O
,	O
N7	O
)	O
chips	O
.	O
</s>
<s>
In	O
May	O
2018	O
,	O
Samsung	B-Application
announced	O
production	O
of	O
7nm	B-Algorithm
(	O
7LPP	O
)	O
chips	O
this	O
year	O
.	O
</s>
<s>
ASML	O
Holding	O
NV	O
is	O
their	O
main	O
supplier	O
of	O
EUV	B-Algorithm
lithography	I-Algorithm
machines	O
.	O
</s>
<s>
In	O
August	O
2018	O
,	O
GlobalFoundries	O
announced	O
it	O
was	O
stopping	O
development	O
of	O
7nm	B-Algorithm
chips	O
,	O
citing	O
cost	O
.	O
</s>
<s>
On	O
October	O
28	O
,	O
2018	O
,	O
Samsung	B-Application
announced	O
their	O
second	O
generation	O
7nm	B-Algorithm
process	O
(	O
7LPP	O
)	O
had	O
entered	O
risk	O
production	O
and	O
should	O
enter	O
mass	O
production	O
in	O
2019	O
.	O
</s>
<s>
On	O
January	O
17	O
,	O
2019	O
,	O
for	O
the	O
Q4	O
2018	O
earnings	O
call	O
,	O
TSMC	O
mentioned	O
that	O
different	O
customers	O
will	O
have	O
"	O
different	O
flavors	O
"	O
of	O
second	O
generation	O
7nm	B-Algorithm
.	O
</s>
<s>
N6	O
uses	O
EUVL	B-Algorithm
in	O
up	O
to	O
5	O
layers	O
,	O
compared	O
to	O
up	O
to	O
4	O
layers	O
in	O
their	O
N7+	O
process	O
.	O
</s>
<s>
On	O
July	O
28	O
,	O
2019	O
,	O
TSMC	O
announced	O
their	O
second	O
gen	O
7nm	B-Algorithm
process	O
called	O
N7P	O
,	O
which	O
is	O
DUV-based	O
like	O
their	O
N7	O
process	O
.	O
</s>
<s>
Since	O
N7P	O
is	O
fully	O
IP-compatible	O
with	O
the	O
original	O
7nm	B-Algorithm
,	O
while	O
N7+	O
(	O
which	O
uses	O
EUV	O
)	O
is	O
not	O
,	O
N7+	O
(	O
announced	O
earlier	O
as	O
'	O
7nm+	O
 '	O
)	O
is	O
a	O
separate	O
process	O
from	O
'	O
7nm	B-Algorithm
 '	O
.	O
</s>
<s>
N6	O
( 	O
 '	O
6nm	O
 '	O
)	O
,	O
another	O
EUV-based	O
process	O
,	O
is	O
planned	O
to	O
be	O
released	O
later	O
than	O
even	O
TSMC	O
's	O
5nm	B-Algorithm
(	O
N5	O
)	O
process	O
,	O
with	O
the	O
IP-compatibility	O
with	O
N7	O
.	O
</s>
<s>
Intel	O
's	O
10nm	B-Algorithm
Enhanced	O
SuperFin	O
(	O
10ESF	O
)	O
,	O
which	O
is	O
roughly	O
equivalent	O
to	O
TSMC	O
's	O
N7	O
process	O
,	O
would	O
now	O
be	O
known	O
as	O
Intel	O
7	O
,	O
while	O
their	O
earlier	O
7nm	B-Algorithm
process	O
would	O
now	O
be	O
called	O
Intel	O
4	O
.	O
</s>
<s>
This	O
means	O
that	O
their	O
first	O
processors	O
based	O
on	O
the	O
new	O
7nm	B-Algorithm
would	O
start	O
shipping	O
by	O
the	O
second	O
half	O
of	O
2022	O
.	O
</s>
<s>
Intel	O
earlier	O
announced	O
that	O
they	O
would	O
launch	O
7nm	B-Algorithm
processors	O
in	O
2023	O
.	O
</s>
<s>
In	O
June	O
2018	O
,	O
AMD	O
announced	O
7nm	B-Algorithm
Radeon	B-Operating_System
Instinct	I-Operating_System
GPUs	O
launching	O
in	O
the	O
second	O
half	O
of	O
2018	O
.	O
</s>
<s>
On	O
August	O
21	O
,	O
2018	O
,	O
Huawei	O
announced	O
their	O
HiSilicon	O
Kirin	O
980	O
SoC	O
to	O
be	O
used	O
in	O
their	O
Huawei	B-Application
Mate	I-Application
20	I-Application
and	I-Application
Mate	I-Application
20	I-Application
Pro	I-Application
built	O
using	O
TSMC	O
's	O
7nm	B-Algorithm
(	O
N7	O
)	O
process	O
.	O
</s>
<s>
On	O
September	O
12	O
,	O
2018	O
,	O
Apple	O
announced	O
their	O
A12	B-Device
Bionic	I-Device
chip	I-Device
used	O
in	O
iPhone	B-Operating_System
XS	I-Operating_System
and	O
iPhone	B-Operating_System
XR	I-Operating_System
built	O
using	O
TSMC	O
's	O
7nm	B-Algorithm
(	O
N7	O
)	O
process	O
.	O
</s>
<s>
The	O
A12	O
processor	O
became	O
the	O
first	O
7nm	B-Algorithm
chip	O
for	O
mass	O
market	O
use	O
as	O
it	O
released	O
before	O
the	O
Huawei	B-Application
Mate	I-Application
20	I-Application
.	O
</s>
<s>
On	O
October	O
30	O
,	O
2018	O
,	O
Apple	O
announced	O
their	O
A12X	B-Device
Bionic	I-Device
chip	O
used	O
in	O
iPad	B-Device
Pro	I-Device
built	O
using	O
TSMC	O
's	O
7nm	B-Algorithm
(	O
N7	O
)	O
process	O
.	O
</s>
<s>
On	O
December	O
4	O
,	O
2018	O
,	O
Qualcomm	O
announced	O
their	O
Snapdragon	B-Architecture
855	O
and	O
8cx	O
built	O
using	O
TSMC	O
's	O
7nm	B-Algorithm
(	O
N7	O
)	O
process	O
.	O
</s>
<s>
The	O
first	O
mass	O
product	O
featuring	O
the	O
Snapdragon	B-Architecture
855	O
was	O
the	O
Lenovo	O
Z5	O
Pro	O
GT	O
,	O
which	O
was	O
announced	O
on	O
December	O
18	O
,	O
2018	O
.	O
</s>
<s>
On	O
May	O
29	O
,	O
2019	O
,	O
MediaTek	B-Architecture
announced	O
their	O
5G	O
SoC	O
built	O
using	O
a	O
TSMC	O
7nm	B-Algorithm
process	O
.	O
</s>
<s>
On	O
July	O
7	O
,	O
2019	O
,	O
AMD	O
officially	O
launched	O
their	O
Ryzen	O
3000	O
series	O
of	O
central	O
processing	O
units	O
,	O
based	O
on	O
the	O
TSMC	O
7nm	B-Algorithm
process	O
and	O
Zen	O
2	O
microarchitecture	O
.	O
</s>
<s>
On	O
August	O
6	O
,	O
2019	O
,	O
Samsung	B-Application
announced	O
their	O
Exynos	O
9825	O
SoC	O
,	O
the	O
first	O
chip	O
built	O
using	O
their	O
7LPP	O
process	O
.	O
</s>
<s>
The	O
Exynos	O
9825	O
is	O
the	O
first	O
mass	O
market	O
chip	O
built	O
featuring	O
EUVL	B-Algorithm
.	O
</s>
<s>
On	O
September	O
10	O
,	O
2019	O
,	O
Apple	O
announced	O
their	O
A13	B-Device
Bionic	I-Device
chip	I-Device
used	O
in	O
iPhone	B-Operating_System
11	I-Operating_System
and	O
iPhone	B-Operating_System
11	I-Operating_System
Pro	I-Operating_System
built	O
using	O
TSMC	O
's	O
2nd	O
gen	O
N7P	O
process	O
.	O
</s>
<s>
7nm	B-Algorithm
(	O
N7	O
nodes	O
)	O
manufacturing	O
made	O
up	O
36%	O
of	O
TSMC	O
's	O
revenue	O
in	O
the	O
second	O
quarter	O
of	O
2020	O
.	O
</s>
<s>
On	O
August	O
17	O
,	O
2020	O
,	O
IBM	O
announced	O
their	O
Power10	B-Operating_System
processor	O
.	O
</s>
<s>
On	O
July	O
26	O
,	O
2021	O
,	O
Intel	O
announced	O
that	O
their	O
Alder	B-Device
Lake	I-Device
processors	O
would	O
be	O
manufactured	O
using	O
their	O
newly	O
rebranded	O
Intel	O
7	O
process	O
,	O
previously	O
known	O
as	O
10nm	B-Algorithm
Enhanced	O
SuperFin	O
.	O
</s>
<s>
The	O
company	O
earlier	O
confirmed	O
a	O
7nm	B-Algorithm
,	O
now	O
called	O
Intel	O
4	O
,	O
microprocessor	O
family	O
called	O
Meteor	O
Lake	O
to	O
be	O
released	O
in	O
2023	O
.	O
</s>
<s>
The	O
7nm	B-Algorithm
foundry	O
node	O
is	O
expected	O
to	O
utilize	O
any	O
of	O
or	O
a	O
combination	O
of	O
the	O
following	O
patterning	O
technologies	O
:	O
pitch	B-Algorithm
splitting	I-Algorithm
,	O
self-aligned	B-Algorithm
patterning	I-Algorithm
,	O
and	O
EUV	B-Algorithm
lithography	I-Algorithm
.	O
</s>
<s>
Pitch	B-Algorithm
splitting	I-Algorithm
involves	O
splitting	O
features	O
that	O
are	O
too	O
close	O
together	O
onto	O
different	O
masks	O
,	O
which	O
are	O
exposed	O
successively	O
,	O
followed	O
by	O
litho-etch	O
processing	O
.	O
</s>
<s>
For	O
FEOL	B-Algorithm
features	O
like	O
gate	O
or	O
active	O
area	O
isolation	O
(	O
e.g.	O
,	O
fins	O
)	O
,	O
the	O
trench	O
CD	O
is	O
not	O
as	O
critical	O
as	O
the	O
spacer-defined	O
CD	O
,	O
in	O
which	O
case	O
,	O
spacer	O
patterning	O
is	O
actually	O
the	O
preferred	O
patterning	O
approach	O
.	O
</s>
<s>
When	O
self-aligned	O
quadruple	O
patterning	O
(	O
SAQP	B-Algorithm
)	O
is	O
used	O
,	O
there	O
is	O
a	O
second	O
spacer	O
that	O
is	O
utilized	O
,	O
replacing	O
the	O
first	O
one	O
.	O
</s>
<s>
This	O
is	O
actually	O
expected	O
to	O
have	O
less	O
variation	O
than	O
pitch	B-Algorithm
splitting	I-Algorithm
,	O
where	O
an	O
additional	O
exposure	O
defines	O
its	O
own	O
CD	O
,	O
both	O
directly	O
and	O
through	O
overlay	O
.	O
</s>
<s>
Self-aligned	O
litho-etch-litho-etch	O
(	O
SALELE	O
)	O
has	O
been	O
implemented	O
for	O
7nm	B-Algorithm
BEOL	B-Algorithm
patterning	O
.	O
</s>
<s>
Extreme	B-Algorithm
ultraviolet	I-Algorithm
lithography	I-Algorithm
(	O
also	O
known	O
as	O
EUV	O
or	O
EUVL	B-Algorithm
)	O
is	O
capable	O
of	O
resolving	O
features	O
below	O
20nm	O
in	O
conventional	O
lithography	O
style	O
.	O
</s>
<s>
This	O
effect	O
may	O
be	O
similar	O
to	O
what	O
may	O
be	O
encountered	O
with	O
pitch	B-Algorithm
splitting	I-Algorithm
.	O
</s>
<s>
Attenuated	B-Algorithm
phase	I-Algorithm
shift	I-Algorithm
masks	I-Algorithm
have	O
been	O
used	O
in	O
production	O
for	O
90	O
nm	O
node	O
for	O
adequate	O
focus	O
windows	O
for	O
arbitrarily	O
pitched	O
contacts	O
with	O
the	O
ArF	O
laser	O
wavelength	O
(	O
193nm	O
)	O
,	O
whereas	O
this	O
resolution	O
enhancement	O
is	O
not	O
available	O
for	O
EUV	O
.	O
</s>
<s>
At	O
2021	O
SPIE	O
's	O
EUV	B-Algorithm
Lithography	I-Algorithm
conference	O
,	O
it	O
was	O
reported	O
by	O
a	O
TSMC	O
customer	O
that	O
EUV	O
contact	O
yield	O
was	O
comparable	O
to	O
immersion	O
multipatterning	B-Algorithm
yield	O
.	O
</s>
<s>
Due	O
to	O
these	O
challenges	O
,	O
7nm	B-Algorithm
poses	O
unprecedented	O
patterning	O
difficulty	O
in	O
the	O
back	B-Algorithm
end	I-Algorithm
of	I-Algorithm
line	I-Algorithm
(	O
BEOL	B-Algorithm
)	O
.	O
</s>
<s>
The	O
previous	O
high-volume	O
,	O
long-lived	O
foundry	O
node	O
(	O
Samsung	B-Application
10nm	B-Algorithm
,	O
TSMC	O
16nm	O
)	O
used	O
pitch	B-Algorithm
splitting	I-Algorithm
for	O
the	O
tighter	O
pitch	O
metal	O
layers	O
.	O
</s>
<s>
Due	O
to	O
the	O
immersion	O
tools	O
being	O
faster	O
presently	O
,	O
multipatterning	B-Algorithm
is	O
still	O
used	O
on	O
most	O
layers	O
.	O
</s>
<s>
On	O
the	O
other	O
layers	O
,	O
immersion	O
would	O
be	O
more	O
productive	O
at	O
completing	O
the	O
layer	O
even	O
with	O
multipatterning	B-Algorithm
.	O
</s>
<s>
The	O
7nm	B-Algorithm
metal	O
patterning	O
currently	O
practiced	O
by	O
TSMC	O
involves	O
self-aligned	O
double	B-Algorithm
patterning	I-Algorithm
(	O
SADP	O
)	O
lines	O
with	O
cuts	O
inserted	O
within	O
a	O
cell	O
on	O
a	O
separate	O
mask	O
as	O
needed	O
to	O
reduce	O
cell	O
height	O
.	O
</s>
<s>
However	O
,	O
self-aligned	O
quad	O
patterning	O
(	O
SAQP	B-Algorithm
)	O
is	O
used	O
to	O
form	O
the	O
fin	O
,	O
the	O
most	O
important	O
factor	O
to	O
performance	O
.	O
</s>
<s>
Design	O
rule	O
checks	O
also	O
allow	O
via	O
multi-patterning	B-Algorithm
to	O
be	O
avoided	O
,	O
and	O
provide	O
enough	O
clearances	O
for	O
cuts	O
that	O
only	O
one	O
cut	O
mask	O
is	O
needed	O
.	O
</s>
<s>
The	O
naming	O
of	O
process	O
nodes	O
by	O
4	O
different	O
manufacturers	O
(	O
TSMC	O
,	O
Samsung	B-Application
,	O
SMIC	O
,	O
Intel	O
)	O
is	O
partially	O
marketing-driven	O
and	O
not	O
directly	O
related	O
to	O
any	O
measurable	O
distance	O
on	O
a	O
chip	O
for	O
example	O
TSMC	O
's	O
7nm	B-Algorithm
node	O
was	O
previously	O
similar	O
in	O
some	O
key	O
dimensions	O
to	O
Intel	O
's	O
planned	O
first-iteration	O
10nm	B-Algorithm
node	O
,	O
before	O
Intel	O
released	O
further	O
iterations	O
,	O
culminating	O
in	O
"	O
10nm	B-Algorithm
Enhanced	O
SuperFin	O
"	O
,	O
which	O
was	O
later	O
renamed	O
to	O
"	O
Intel	O
7	O
"	O
for	O
marketing	O
reasons	O
.	O
</s>
<s>
Since	O
EUV	O
implementation	O
at	O
7nm	B-Algorithm
is	O
still	O
limited	O
,	O
multipatterning	B-Algorithm
still	O
plays	O
an	O
important	O
part	O
in	O
cost	O
and	O
yield	O
;	O
EUV	O
adds	O
extra	O
considerations	O
.	O
</s>
<s>
The	O
resolution	O
for	O
most	O
critical	O
layers	O
is	O
still	O
determined	O
by	O
multiple	B-Algorithm
patterning	I-Algorithm
.	O
</s>
<s>
For	O
example	O
,	O
for	O
Samsung	B-Application
's	O
7nm	B-Algorithm
,	O
even	O
with	O
EUV	O
single-patterned	O
36nm	O
pitch	O
layers	O
,	O
44nm	O
pitch	O
layers	O
would	O
still	O
be	O
quadruple	O
patterned	O
.	O
</s>
<s>
+	O
7	O
nm	O
process	O
nodes	O
and	O
process	O
offerings	O
SamsungTSMC	O
IntelSMIC	O
Process	O
name	O
7LPP	O
6LPP	O
N7IEDM	O
2016	O
N7P	O
N7+	O
N6	O
Intel	O
7	O
N+1	O
(	O
>7	O
nm	O
)	O
N+2	O
(	O
7	O
nm	O
)	O
7	O
nm	O
EUV	O
Transistor	O
density	O
(	O
MTr/mm2	O
)	O
95.08	O
–	O
100.59	O
112.7991.2	O
–	O
96.5	O
113.9	O
114.2	O
100.76	O
–	O
106.1	O
60.41	O
89	O
SRAM	B-Architecture
bit-cell	O
size	O
0.0262	O
μm2	O
0.027	O
μm2	O
0.0312	O
μm2	O
Transistor	O
gate	O
pitch	O
54	O
nm	O
54	O
nm	O
54	O
nm	O
Transistor	O
fin	O
pitch	O
27	O
nm	O
N/A	O
34	O
nm	O
Transistor	O
fin	O
height	O
N/A	O
53	O
nm	O
Minimum	O
(	O
metal	O
)	O
pitch	O
46	O
nm	O
40	O
nm	O
<	O
40	O
nm	O
40	O
nm	O
EUV	O
implementation	O
36	O
nm	O
pitch	O
metal	O
;	O
20%	O
of	O
total	O
layer	O
set	O
None	O
,	O
used	O
self-aligned	O
quad	O
patterning	O
(	O
SAQP	B-Algorithm
)	O
instead	O
4	O
layers	O
5	O
layers	O
None	O
.	O
</s>
<s>
GlobalFoundries	O
 '	O
7nm	B-Algorithm
7LP	O
(	O
Leading	O
Performance	O
)	O
process	O
would	O
have	O
offered	O
40%	O
higher	O
performance	O
or	O
60%+	O
lower	O
power	O
with	O
a	O
2x	O
scaling	O
in	O
density	O
and	O
at	O
a	O
30-45	O
+%	O
lower	O
cost	O
per	O
die	O
over	O
its	O
14nm	O
process	O
.	O
</s>
<s>
The	O
Contacted	O
Poly	O
Pitch	O
(	O
CPP	O
)	O
would	O
have	O
been	O
56nm	O
and	O
the	O
Minimum	O
Metal	O
Pitch	O
(	O
MMP	O
)	O
would	O
have	O
been	O
40nm	O
,	O
produced	O
with	O
Self-Aligned	O
Double	B-Algorithm
Patterning	I-Algorithm
(	O
SADP	O
)	O
.	O
</s>
<s>
A	O
6T	O
SRAM	B-Architecture
cell	O
would	O
have	O
been	O
0.269	O
square	O
microns	O
in	O
size	O
.	O
</s>
<s>
GlobalFoundries	O
planned	O
to	O
eventually	O
use	O
EUV	B-Algorithm
lithography	I-Algorithm
in	O
an	O
improved	O
process	O
called	O
7LP+	O
.	O
</s>
<s>
GlobalFoundries	O
later	O
stopped	O
all	O
7nm	B-Algorithm
and	O
beyond	O
process	O
development	O
.	O
</s>
<s>
Intel	O
's	O
new	O
"	O
Intel	O
7	O
"	O
process	O
,	O
previously	O
known	O
as	O
10nm	B-Algorithm
Enhanced	O
SuperFin	O
(	O
10ESF	O
)	O
,	O
is	O
based	O
on	O
its	O
previous	O
10nm	B-Algorithm
node	O
.	O
</s>
<s>
Meanwhile	O
,	O
their	O
old	O
7nm	B-Algorithm
process	O
,	O
now	O
called	O
"	O
Intel	O
4	O
"	O
,	O
is	O
expected	O
to	O
be	O
released	O
in	O
2023	O
.	O
</s>
