<s>
In	O
semiconductor	B-Architecture
manufacturing	I-Architecture
,	O
the	O
International	O
Roadmap	O
for	O
Devices	O
and	O
Systems	O
defines	O
the	O
5	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
as	O
the	O
MOSFET	B-Architecture
technology	O
node	O
following	O
the	O
7	B-Algorithm
nm	I-Algorithm
node	O
.	O
</s>
<s>
In	O
2020	O
,	O
Samsung	B-Application
and	O
TSMC	O
entered	O
volume	O
production	O
of	O
5nm	B-Algorithm
chips	O
,	O
manufactured	O
for	O
companies	O
including	O
Apple	O
,	O
Marvell	O
,	O
Huawei	O
and	O
Qualcomm	O
.	O
</s>
<s>
The	O
term	O
"	O
5	B-Algorithm
nm	I-Algorithm
"	O
has	O
no	O
relation	O
to	O
any	O
actual	O
physical	O
feature	O
(	O
such	O
as	O
gate	O
length	O
,	O
metal	O
pitch	O
or	O
gate	O
pitch	O
)	O
of	O
the	O
transistors	B-Application
being	O
5	B-Algorithm
nanometers	I-Algorithm
in	O
size	O
.	O
</s>
<s>
According	O
to	O
the	O
projections	O
contained	O
in	O
the	O
2021	O
update	O
of	O
the	O
International	O
Roadmap	O
for	O
Devices	O
and	O
Systems	O
published	O
by	O
IEEE	O
Standards	O
Association	O
Industry	O
Connection	O
,	O
a	O
"	O
5	B-Algorithm
nm	I-Algorithm
node	O
is	O
expected	O
to	O
have	O
a	O
contacted	O
gate	O
pitch	O
of	O
51	O
nanometers	O
and	O
a	O
tightest	O
metal	O
pitch	O
of	O
30	O
nanometers	O
"	O
.	O
</s>
<s>
However	O
,	O
in	O
real	O
world	O
commercial	O
practice	O
,	O
"	O
5	B-Algorithm
nm	I-Algorithm
"	O
is	O
used	O
primarily	O
as	O
a	O
marketing	O
term	O
by	O
individual	O
microchip	O
manufacturers	O
to	O
refer	O
to	O
a	O
new	O
,	O
improved	O
generation	O
of	O
silicon	O
semiconductor	O
chips	O
in	O
terms	O
of	O
increased	O
transistor	B-Application
density	O
(	O
i.e.	O
</s>
<s>
a	O
higher	O
degree	O
of	O
miniaturization	O
)	O
,	O
increased	O
speed	O
and	O
reduced	O
power	O
consumption	O
compared	O
to	O
the	O
previous	O
7	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
.	O
</s>
<s>
Quantum	O
tunnelling	O
effects	O
through	O
the	O
gate	O
oxide	O
layer	O
on	O
7nm	B-Algorithm
and	O
5nm	B-Algorithm
transistors	B-Application
became	O
increasingly	O
difficult	O
to	O
manage	O
using	O
existing	O
semiconductor	O
processes	O
.	O
</s>
<s>
Single-transistor	O
devices	O
below	O
7nm	B-Algorithm
were	O
first	O
demonstrated	O
by	O
researchers	O
in	O
the	O
early	O
2000s	O
.	O
</s>
<s>
In	O
2002	O
,	O
an	O
IBM	O
research	O
team	O
including	O
Bruce	O
Doris	O
,	O
Omer	O
Dokumaci	O
,	O
Meikei	O
Ieong	O
and	O
Anda	O
Mocuta	O
fabricated	O
a	O
6-nanometre	O
silicon-on-insulator	B-Algorithm
(	O
SOI	O
)	O
MOSFET	B-Architecture
.	O
</s>
<s>
In	O
2003	O
,	O
a	O
Japanese	O
research	O
team	O
at	O
NEC	O
,	O
led	O
by	O
Hitoshi	O
Wakabayashi	O
and	O
Shigeharu	O
Yamagami	O
,	O
fabricated	O
the	O
first	O
5nm	B-Algorithm
MOSFET	B-Architecture
.	O
</s>
<s>
In	O
2015	O
,	O
IMEC	O
and	O
Cadence	O
had	O
fabricated	O
5nm	B-Algorithm
test	O
chips	O
.	O
</s>
<s>
In	O
2015	O
,	O
Intel	O
described	O
a	O
lateral	O
nanowire	O
(	O
or	O
gate-all-around	O
)	O
FET	O
concept	O
for	O
the	O
5nm	B-Algorithm
node	O
.	O
</s>
<s>
In	O
2017	O
,	O
IBM	O
revealed	O
that	O
it	O
had	O
created	O
5nm	B-Algorithm
silicon	O
chips	O
,	O
using	O
silicon	O
nanosheets	O
in	O
a	O
gate-all-around	O
configuration	O
(	O
GAAFET	O
)	O
,	O
a	O
break	O
from	O
the	O
usual	O
FinFET	O
design	O
.	O
</s>
<s>
The	O
GAAFET	O
transistors	B-Application
used	O
had	O
3	O
nanosheets	O
stacked	O
on	O
top	O
of	O
each	O
other	O
,	O
covered	O
in	O
their	O
entirety	O
by	O
the	O
same	O
gate	O
,	O
just	O
like	O
FinFETs	O
usually	O
have	O
several	O
physical	O
fins	O
side	O
by	O
side	O
that	O
are	O
electrically	O
a	O
single	O
unit	O
and	O
are	O
covered	O
in	O
their	O
entirety	O
by	O
the	O
same	O
gate	O
.	O
</s>
<s>
IBM	O
's	O
chip	O
measured	O
50mm2	O
and	O
had	O
600	O
million	O
transistors	B-Application
per	O
mm2	O
,	O
for	O
a	O
total	O
of	O
30	O
billion	O
transistors	B-Application
(	O
1667	O
nm	O
2	O
per	O
transistor	B-Application
or	O
41	O
nm	O
transistor	B-Application
spacing	O
)	O
.	O
</s>
<s>
In	O
April	O
2019	O
,	O
Samsung	B-Application
Electronics	O
announced	O
they	O
had	O
been	O
offering	O
their	O
5nm	B-Algorithm
process	O
(	O
5LPE	O
)	O
tools	O
to	O
their	O
customers	O
since	O
2018	O
Q4	O
.	O
</s>
<s>
In	O
April	O
2019	O
,	O
TSMC	O
announced	O
that	O
their	O
5nm	B-Algorithm
process	O
(	O
CLN5FF	O
,	O
N5	O
)	O
had	O
begun	O
risk	O
production	O
,	O
and	O
that	O
full	O
chip	O
design	O
specifications	O
were	O
now	O
available	O
to	O
potential	O
customers	O
.	O
</s>
<s>
The	O
N5	O
process	O
can	O
use	O
EUVL	B-Algorithm
on	O
up	O
to	O
14	O
layers	O
,	O
compared	O
to	O
only	O
5	O
or	O
4	O
layers	O
in	O
N6	O
and	O
N7++	O
.	O
</s>
<s>
For	O
their	O
5nm	B-Algorithm
process	O
,	O
Samsung	B-Application
started	O
process	O
defect	O
mitigation	O
by	O
automated	O
check	O
and	O
fix	O
,	O
due	O
to	O
occurrence	O
of	O
stochastic	O
(	O
random	O
)	O
defects	O
in	O
the	O
metal	O
and	O
via	O
layers	O
.	O
</s>
<s>
In	O
October	O
2019	O
,	O
TSMC	O
reportedly	O
started	O
sampling	O
5nm	B-Algorithm
A14	B-Device
processors	I-Device
for	I-Device
Apple	I-Device
.	O
</s>
<s>
In	O
December	O
2019	O
,	O
TSMC	O
announced	O
an	O
average	O
yield	O
of	O
approximately	O
80%	O
,	O
with	O
a	O
peak	O
yield	O
per	O
wafer	O
of	O
over	O
90%	O
for	O
their	O
5nm	B-Algorithm
test	O
chips	O
with	O
a	O
die	O
size	O
of	O
17.92mm2	O
.	O
</s>
<s>
In	O
mid	O
2020	O
TSMC	O
claimed	O
its	O
(	O
N5	O
)	O
5nm	B-Algorithm
process	O
offered	O
1.8x	O
the	O
density	O
of	O
its	O
7nm	B-Algorithm
N7	O
process	O
,	O
with	O
15%	O
speed	O
improvement	O
or	O
30%	O
lower	O
power	O
consumption	O
;	O
an	O
improved	O
sub-version	O
(	O
N5P	O
or	O
N4	O
)	O
was	O
claimed	O
to	O
improve	O
on	O
N5	O
with	O
+5%	O
speed	O
or	O
-10	O
%	O
power	O
.	O
</s>
<s>
On	O
13	O
October	O
2020	O
,	O
Apple	O
announced	O
a	O
new	O
iPhone	B-Operating_System
12	I-Operating_System
lineup	O
using	O
the	O
A14	B-Device
.	O
</s>
<s>
Together	O
with	O
the	O
Huawei	B-Application
Mate	I-Application
40	I-Application
lineup	O
using	O
the	O
HiSilicon	O
Kirin	O
9000	O
,	O
the	O
A14	B-Device
and	O
Kirin	O
9000	O
were	O
the	O
first	O
devices	O
to	O
be	O
commercialized	O
on	O
TSMC	O
's	O
5nm	B-Algorithm
node	O
.	O
</s>
<s>
Later	O
,	O
on	O
10	O
November	O
2020	O
,	O
Apple	O
also	O
revealed	O
three	O
new	O
Mac	O
models	O
using	O
the	O
Apple	B-Device
M1	I-Device
,	O
another	O
5nm	B-Algorithm
chip	O
.	O
</s>
<s>
According	O
to	O
Semianalysis	O
,	O
the	O
A14	B-Device
processor	O
has	O
a	O
transistor	B-Application
density	O
of	O
134	O
million	O
transistors	B-Application
per	O
mm2	O
.	O
</s>
<s>
In	O
October	O
2021	O
,	O
TSMC	O
introduced	O
a	O
new	O
member	O
of	O
its	O
5nm	B-Algorithm
process	O
family	O
:	O
N4P	O
.	O
</s>
<s>
Compared	O
to	O
N5	O
,	O
the	O
node	O
offers	O
11%	O
higher	O
performance	O
(	O
6%	O
higher	O
vs	O
N4	O
)	O
,	O
22%	O
higher	O
power	O
efficiency	O
,	O
6%	O
higher	O
transistor	B-Application
density	O
and	O
lower	O
mask	O
count	O
.	O
</s>
<s>
In	O
December	O
2021	O
,	O
TSMC	O
announced	O
a	O
new	O
member	O
of	O
its	O
5nm	B-Algorithm
process	O
family	O
designed	O
for	O
HPC	O
applications	O
:	O
N4X	O
.	O
</s>
<s>
The	O
process	O
features	O
optimized	O
transistor	B-Application
design	O
and	O
structures	O
,	O
reduced	O
resistance	O
and	O
capacitance	O
of	O
targeted	O
metal	O
layers	O
and	O
high-density	O
MiM	O
capacitors	O
.	O
</s>
<s>
In	O
June	O
2022	O
,	O
Intel	O
presented	O
some	O
details	O
about	O
the	O
Intel	O
4	O
process	O
(	O
known	O
as	O
7nm	B-Algorithm
before	O
renaming	O
in	O
2021	O
)	O
:	O
the	O
company	O
's	O
first	O
process	O
to	O
use	O
EUV	O
,	O
2x	O
higher	O
transistor	B-Application
density	O
compared	O
to	O
Intel	O
7	O
(	O
known	O
as	O
10nm	O
ESF	O
(	O
Enhanced	O
Super	O
Fin	O
)	O
before	O
the	O
renaming	O
)	O
,	O
use	O
of	O
cobalt-clad	O
copper	O
for	O
the	O
finest	O
five	O
layers	O
of	O
interconnect	O
,	O
21.5	O
%	O
higher	O
performance	O
at	O
iso	O
power	O
or	O
40%	O
lower	O
power	O
at	O
iso	O
frequency	O
at	O
0.65	O
V	O
compared	O
to	O
Intel	O
7	O
etc	O
.	O
</s>
<s>
The	O
process	O
is	O
optimized	O
for	O
HPC	O
applications	O
and	O
supports	O
voltage	O
from	O
<	O
0.65	O
V	O
to	O
>1.3	O
V	O
.	O
WikiChip	O
's	O
transistor	B-Application
density	O
estimate	O
for	O
Intel	O
4	O
is	O
123.4	O
Mtr./mm²	O
,	O
2.04x	O
from	O
60.5	O
Mtr./mm²	O
for	O
Intel	O
7	O
.	O
</s>
<s>
On	O
27	O
September	O
2022	O
,	O
AMD	O
officially	O
launched	O
their	O
Ryzen	O
7000	O
series	O
of	O
central	O
processing	O
units	O
,	O
based	O
on	O
the	O
TSMC	O
5	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
and	O
Zen	O
4	O
microarchitecture	O
.	O
</s>
<s>
Zen	O
4	O
marks	O
the	O
first	O
utilization	O
of	O
the	O
5	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
for	O
x86-based	O
desktop	O
processors	O
.	O
</s>
<s>
AMD	O
also	O
launched	O
the	O
Radeon	B-Device
7000	O
series	O
of	O
graphics	O
processing	O
unit	O
based	O
on	O
RDNA	O
3	O
which	O
also	O
uses	O
TSMC	O
5nm	B-Algorithm
process	O
.	O
</s>
<s>
Transistor	B-Application
gate	O
pitch	O
is	O
also	O
referred	O
to	O
as	O
CPP	O
(	O
contacted	O
poly	O
pitch	O
)	O
and	O
interconnect	O
pitch	O
is	O
also	O
referred	O
to	O
as	O
MMP	O
(	O
minimum	O
metal	O
pitch	O
)	O
.	O
</s>
<s>
3	O
nm	O
(	O
3-nanometer	O
)	O
is	O
the	O
usual	O
term	O
for	O
the	O
next	O
node	O
after	O
5nm	B-Algorithm
.	O
</s>
<s>
,	O
TSMC	O
plans	O
to	O
commercialize	O
the	O
3nm	B-Algorithm
node	O
for	O
2022	O
,	O
while	O
Samsung	B-Application
and	O
Intel	O
have	O
plans	O
for	O
2023	O
.	O
</s>
<s>
3.5nm	O
has	O
also	O
been	O
given	O
as	O
a	O
name	O
for	O
the	O
first	O
node	O
beyond	O
5nm	B-Algorithm
.	O
</s>
