<s>
The	O
32	B-Algorithm
nm	I-Algorithm
node	O
is	O
the	O
step	O
following	O
the	O
45	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
in	O
CMOS	B-Device
(	O
MOSFET	B-Architecture
)	O
semiconductor	B-Architecture
device	I-Architecture
fabrication	I-Architecture
.	O
</s>
<s>
"	O
32-nanometre	O
"	O
refers	O
to	O
the	O
average	O
half-pitch	O
(	O
i.e.	O
,	O
half	O
the	O
distance	O
between	O
identical	O
features	O
)	O
of	O
a	O
memory	B-Algorithm
cell	I-Algorithm
at	O
this	O
technology	O
level	O
.	O
</s>
<s>
Toshiba	O
produced	O
commercial	O
32GiB	O
NAND	O
flash	O
memory	O
chips	O
with	O
the	O
32nm	B-Algorithm
process	O
in	O
2009	O
.	O
</s>
<s>
IBM	O
and	O
the	O
Common	O
Platform	O
also	O
developed	O
a	O
32nm	B-Algorithm
high-κ	B-Algorithm
metal	O
gate	O
process	O
.	O
</s>
<s>
Intel	O
began	O
selling	O
its	O
first	O
32nm	B-Algorithm
processors	O
using	O
the	O
Westmere	B-Device
architecture	I-Device
on	O
7	O
January	O
2010	O
.	O
</s>
<s>
The	O
32nm	B-Algorithm
process	O
was	O
superseded	O
by	O
commercial	O
22	B-Algorithm
nm	I-Algorithm
technology	O
in	O
2012	O
.	O
</s>
<s>
Prototypes	O
using	O
32nm	B-Algorithm
technology	O
first	O
emerged	O
in	O
the	O
mid-2000s	O
.	O
</s>
<s>
In	O
2004	O
,	O
IBM	O
demonstrated	O
a	O
0.143μm2	O
SRAM	B-Algorithm
cell	I-Algorithm
with	O
a	O
poly	O
gate	O
pitch	O
of	O
135nm	O
,	O
produced	O
using	O
electron-beam	B-Architecture
lithography	I-Architecture
and	O
photolithography	B-Algorithm
on	O
the	O
same	O
layer	O
.	O
</s>
<s>
In	O
October	O
2006	O
,	O
the	O
Interuniversity	O
Microelectronics	O
Centre	O
(	O
IMEC	O
)	O
demonstrated	O
a	O
32nm	B-Algorithm
flash	O
patterning	O
capability	O
based	O
on	O
double	B-Algorithm
patterning	I-Algorithm
and	O
immersion	B-Algorithm
lithography	I-Algorithm
.	O
</s>
<s>
The	O
necessity	O
of	O
introducing	O
double	B-Algorithm
patterning	I-Algorithm
and	O
hyper-NA	O
tools	O
to	O
reduce	O
memory	B-Algorithm
cell	I-Algorithm
area	O
offset	O
some	O
of	O
the	O
cost	O
advantages	O
of	O
moving	O
to	O
this	O
node	O
from	O
the	O
45nm	B-Algorithm
node	O
.	O
</s>
<s>
TSMC	O
similarly	O
used	O
double	B-Algorithm
patterning	I-Algorithm
combined	O
with	O
immersion	B-Algorithm
lithography	I-Algorithm
to	O
produce	O
a	O
32nm	B-Algorithm
node	O
0.183μm2	O
six-transistor	O
SRAM	B-Algorithm
cell	I-Algorithm
in	O
2005	O
.	O
</s>
<s>
Intel	O
Corporation	O
revealed	O
its	O
first	O
32nm	B-Algorithm
test	O
chips	O
to	O
the	O
public	O
on	O
18	O
September	O
2007	O
at	O
the	O
Intel	O
Developer	O
Forum	O
.	O
</s>
<s>
The	O
test	O
chips	O
had	O
a	O
cell	O
size	O
of	O
0.182μm2	O
,	O
used	O
a	O
second-generation	O
high-κ	B-Algorithm
gate	O
dielectric	O
and	O
metal	O
gate	O
,	O
and	O
contained	O
almost	O
two	O
billion	O
transistors	O
.	O
</s>
<s>
193nm	O
immersion	B-Algorithm
lithography	I-Algorithm
was	O
used	O
for	O
the	O
critical	O
layers	O
,	O
while	O
193nm	O
or	O
248nm	O
dry	O
lithography	O
was	O
used	O
on	O
less	O
critical	O
layers	O
.	O
</s>
<s>
Intel	O
's	O
Core	O
i3	O
and	O
i5	O
processors	O
,	O
released	O
in	O
January	O
2010	O
,	O
were	O
among	O
the	O
first	O
mass-produced	O
processors	O
to	O
use	O
32nm	B-Algorithm
technology	O
.	O
</s>
<s>
Intel	O
's	O
second-generation	O
Core	O
processors	O
,	O
codenamed	O
Sandy	B-Device
Bridge	I-Device
,	O
also	O
used	O
the	O
32nm	B-Algorithm
manufacturing	O
process	O
.	O
</s>
<s>
Intel	O
's	O
6-core	O
processor	O
,	O
codenamed	O
Gulftown	B-Device
and	O
built	O
on	O
the	O
Westmere	B-Device
architecture	I-Device
,	O
was	O
released	O
on	O
16	O
March	O
2010	O
as	O
the	O
Core	O
i7	O
980x	O
Extreme	O
Edition	O
,	O
retailing	O
for	O
approximately	O
US$	O
1,000	O
.	O
</s>
<s>
AMD	O
also	O
released	O
32nm	B-Algorithm
SOI	O
processors	O
in	O
the	O
early	O
2010s	O
.	O
</s>
<s>
The	O
technology	O
utilised	O
a	O
32nm	B-Algorithm
SOI	O
process	O
,	O
two	O
CPU	O
cores	O
per	O
module	O
,	O
and	O
up	O
to	O
four	O
modules	O
,	O
ranging	O
from	O
a	O
quad-core	O
design	O
costing	O
approximately	O
US$130	O
to	O
a	O
$280	O
eight-core	O
design	O
.	O
</s>
<s>
In	O
September	O
2011	O
,	O
Ambarella	O
Inc	O
.	O
announced	O
the	O
availability	O
of	O
the	O
32nm-based	O
A7L	O
system-on-a-chip	B-Architecture
circuit	O
for	O
digital	O
still	O
cameras	O
,	O
providing	O
1080p60	O
high-definition	O
video	O
capabilities	O
.	O
</s>
<s>
The	O
successor	O
to	O
32nm	B-Algorithm
technology	O
was	O
the	O
22nm	B-Algorithm
node	O
,	O
per	O
the	O
International	O
Technology	O
Roadmap	O
for	O
Semiconductors	O
.	O
</s>
<s>
Intel	O
began	O
mass	O
production	O
of	O
22nm	B-Algorithm
semiconductors	O
in	O
late	O
2011	O
,	O
and	O
announced	O
the	O
release	O
of	O
its	O
first	O
commercial	O
22nm	B-Algorithm
devices	O
in	O
April	O
2012	O
.	O
</s>
<s>
TSMC	O
bypassed	O
32nm	B-Algorithm
,	O
jumping	O
from	O
40nm	O
in	O
2008	O
to	O
28nm	O
in	O
2011	O
.	O
</s>
