<s>
In	O
computer	B-General_Concept
architecture	I-General_Concept
,	O
26-bit	B-Architecture
integers	O
,	O
memory	B-General_Concept
addresses	I-General_Concept
,	O
or	O
other	O
data	B-General_Concept
units	O
are	O
those	O
that	O
are	O
26	B-Architecture
bits	I-Architecture
wide	O
,	O
and	O
thus	O
can	O
represent	O
unsigned	O
values	O
up	O
to	O
67,108,863	O
.	O
</s>
<s>
Two	O
examples	O
of	O
computer	O
processors	O
that	O
featured	O
26-bit	B-Architecture
memory	B-General_Concept
addressing	I-General_Concept
are	O
certain	O
second	O
generation	O
IBM	B-Device
System/370	I-Device
mainframe	B-Architecture
computer	I-Architecture
models	O
introduced	O
in	O
1981	O
(	O
and	O
several	O
subsequent	O
models	O
)	O
,	O
which	O
had	O
26-bit	B-Architecture
physical	O
addresses	O
but	O
had	O
only	O
the	O
same	O
24-bit	O
virtual	O
addresses	O
as	O
earlier	O
models	O
,	O
and	O
the	O
first	O
generations	O
of	O
ARM	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
As	O
data	B-General_Concept
processing	I-General_Concept
needs	O
continued	O
to	O
grow	O
,	O
IBM	O
and	O
their	O
customers	O
faced	O
challenges	O
directly	O
addressing	O
larger	O
memory	B-Architecture
sizes	O
.	O
</s>
<s>
In	O
what	O
ended	O
up	O
being	O
a	O
short-term	O
"	O
emergency	O
"	O
solution	O
,	O
a	O
pair	O
of	O
IBM	O
's	O
second	O
wave	O
of	O
System/370	B-Device
models	O
,	O
the	O
3033	O
and	O
3081	O
,	O
introduced	O
26-bit	B-Architecture
real	O
memory	B-General_Concept
addressing	I-General_Concept
,	O
increasing	O
the	O
System/370	B-Device
'	O
s	O
amount	O
of	O
physical	O
memory	B-Architecture
that	O
could	O
be	O
attached	O
by	O
a	O
factor	O
of	O
4	O
from	O
the	O
previous	O
24-bit	O
limit	O
of	O
16MB	O
.	O
</s>
<s>
IBM	O
referred	O
to	O
26-bit	B-Architecture
addressing	O
as	O
"	O
extended	O
real	O
addressing	O
,	O
"	O
and	O
some	O
subsequent	O
models	O
also	O
included	O
26-bit	B-Architecture
support	O
.	O
</s>
<s>
However	O
,	O
only	O
2	O
years	O
later	O
,	O
IBM	O
introduced	O
31-bit	O
memory	B-General_Concept
addressing	I-General_Concept
,	O
expanding	O
both	O
physical	O
and	O
virtual	O
addresses	O
to	O
31	O
bits	O
,	O
with	O
its	O
System/370	B-Device
-XA	I-Device
models	O
,	O
and	O
even	O
the	O
popular	O
3081	O
was	O
upgradeable	O
to	O
XA	O
standard	O
.	O
</s>
<s>
Given	O
26-bit	B-Architecture
'	O
s	O
brief	O
history	O
as	O
the	O
state-of-the-art	O
in	O
memory	B-General_Concept
addressing	I-General_Concept
available	O
in	O
IBM	O
's	O
model	O
range	O
,	O
and	O
given	O
that	O
virtual	O
addresses	O
were	O
still	O
limited	O
to	O
24	O
bits	O
,	O
software	O
exploitation	O
of	O
26-bit	B-Architecture
mode	O
was	O
limited	O
.	O
</s>
<s>
The	O
few	O
customers	O
that	O
exploited	O
26-bit	B-Architecture
mode	O
eventually	O
adjusted	O
their	O
applications	O
to	O
support	O
31-bit	O
addressing	O
,	O
and	O
IBM	O
dropped	O
support	O
for	O
26-bit	B-Architecture
mode	O
after	O
several	O
years	O
producing	O
models	O
supporting	O
24-bit	O
,	O
26-bit	B-Architecture
,	O
and	O
31-bit	O
modes	O
.	O
</s>
<s>
The	O
26-bit	B-Architecture
mode	O
is	O
the	O
only	O
addressing	O
mode	O
that	O
IBM	O
removed	O
from	O
its	O
line	O
of	O
mainframe	B-Architecture
computers	I-Architecture
descended	O
from	O
the	O
System/360	B-Application
.	O
</s>
<s>
All	O
the	O
other	O
addressing	O
modes	O
,	O
including	O
now	O
64-bit	O
mode	O
,	O
are	O
supported	O
in	O
current	O
model	O
mainframes	B-Architecture
.	O
</s>
<s>
In	O
the	O
ARM	B-Architecture
processor	I-Architecture
architecture	O
,	O
26-bit	B-Architecture
refers	O
to	O
the	O
design	O
used	O
in	O
the	O
original	O
ARM	B-Architecture
processors	I-Architecture
where	O
the	O
Program	B-General_Concept
Counter	I-General_Concept
(	O
PC	O
)	O
and	O
Processor	O
Status	O
Register	O
(	O
PSR	O
)	O
were	O
combined	O
into	O
one	O
32-bit	O
register	O
(	O
R15	O
)	O
,	O
the	O
status	O
flags	O
filling	O
the	O
high	O
6	O
bits	O
and	O
the	O
Program	B-General_Concept
Counter	I-General_Concept
taking	O
up	O
the	O
lower	O
26	B-Architecture
bits	I-Architecture
.	O
</s>
<s>
In	O
fact	O
,	O
because	O
the	O
program	B-General_Concept
counter	I-General_Concept
is	O
always	O
word-aligned	O
the	O
lowest	O
two	O
bits	O
are	O
always	O
zero	O
which	O
allowed	O
the	O
designers	O
to	O
reuse	O
these	O
two	O
bits	O
to	O
hold	O
the	O
processor	O
's	O
mode	O
bits	O
too	O
.	O
</s>
<s>
The	O
four	O
modes	O
allowed	O
were	O
USR26	O
,	O
SVC26	O
,	O
IRQ26	O
,	O
FIQ26	O
;	O
contrast	O
this	O
with	O
the	O
32	O
possible	O
modes	O
available	O
when	O
the	O
program	O
status	O
was	O
separated	O
from	O
the	O
program	B-General_Concept
counter	I-General_Concept
in	O
more	O
recent	O
ARM	B-Architecture
architectures	I-Architecture
.	O
</s>
<s>
This	O
design	O
enabled	O
more	O
efficient	O
program	O
execution	O
,	O
as	O
the	O
Program	B-General_Concept
Counter	I-General_Concept
and	O
status	O
flags	O
could	O
be	O
saved	O
and	O
restored	O
with	O
a	O
single	O
operation	O
.	O
</s>
<s>
This	O
resulted	O
in	O
faster	O
subroutine	O
calls	O
and	O
interrupt	B-Application
response	O
than	O
traditional	O
designs	O
,	O
which	O
would	O
have	O
to	O
do	O
two	O
register	O
loads	O
or	O
saves	O
when	O
calling	O
or	O
returning	O
from	O
a	O
subroutine	O
.	O
</s>
<s>
Despite	O
having	O
a	O
32-bit	O
ALU	O
and	O
word-length	O
,	O
processors	O
based	O
on	O
ARM	B-Architecture
architecture	I-Architecture
version	O
1	O
and	O
2	O
had	O
only	O
a	O
26-bit	B-Architecture
PC	O
and	O
address	B-Architecture
bus	I-Architecture
,	O
and	O
were	O
consequently	O
limited	O
to	O
64MiB	O
of	O
addressable	O
memory	B-Architecture
.	O
</s>
<s>
This	O
was	O
still	O
a	O
vast	O
amount	O
of	O
memory	B-Architecture
at	O
the	O
time	O
,	O
but	O
because	O
of	O
this	O
limitation	O
,	O
architectures	O
since	O
have	O
included	O
various	O
steps	O
away	O
from	O
the	O
original	O
26-bit	B-Architecture
design	O
.	O
</s>
<s>
The	O
ARM	B-Architecture
architecture	I-Architecture
version	O
3	O
introduced	O
a	O
32-bit	O
PC	O
and	O
separate	O
PSR	O
,	O
as	O
well	O
as	O
a	O
32-bit	O
address	B-Architecture
bus	I-Architecture
,	O
allowing	O
4	O
GiB	O
of	O
memory	B-Architecture
to	O
be	O
addressed	O
.	O
</s>
<s>
The	O
change	O
in	O
the	O
PC/PSR	O
layout	O
caused	O
incompatibility	O
with	O
code	O
written	O
for	O
previous	O
architectures	O
,	O
so	O
the	O
processor	O
also	O
included	O
a	O
26-bit	B-Architecture
compatibility	O
mode	O
which	O
used	O
the	O
old	O
PC/PSR	O
combination	O
.	O
</s>
<s>
This	O
mode	O
was	O
used	O
by	O
RISC	B-Operating_System
OS	I-Operating_System
running	O
on	O
the	O
Acorn	O
Risc	O
PC	O
to	O
utilise	O
the	O
new	O
processors	O
while	O
retaining	O
compatibility	O
with	O
existing	O
software	O
.	O
</s>
<s>
ARM	B-Architecture
architecture	I-Architecture
version	O
4	O
made	O
the	O
support	O
of	O
the	O
26-bit	B-Architecture
addressing	O
modes	O
optional	O
,	O
and	O
ARM	B-Architecture
architecture	I-Architecture
version	O
5	O
onwards	O
has	O
removed	O
them	O
entirely	O
.	O
</s>
