<s>
The	O
22	B-Algorithm
nm	I-Algorithm
node	O
is	O
the	O
process	O
step	O
following	O
32	B-Algorithm
nm	I-Algorithm
in	O
CMOS	B-Device
MOSFET	B-Architecture
semiconductor	B-Architecture
device	I-Architecture
fabrication	I-Architecture
.	O
</s>
<s>
The	O
typical	O
half-pitch	O
(	O
i.e.	O
,	O
half	O
the	O
distance	O
between	O
identical	O
features	O
in	O
an	O
array	O
)	O
for	O
a	O
memory	O
cell	O
using	O
the	O
process	O
is	O
around	O
22nm	B-Algorithm
.	O
</s>
<s>
It	O
was	O
first	O
demonstrated	O
by	O
semiconductor	O
companies	O
for	O
use	O
in	O
RAM	B-Architecture
memory	I-Architecture
in	O
2008	O
.	O
</s>
<s>
In	O
2010	O
,	O
Toshiba	O
began	O
shipping	O
24nm	O
flash	B-Device
memory	I-Device
chips	O
,	O
and	O
Samsung	B-Application
Electronics	O
began	O
mass-producing	O
20nm	O
flash	B-Device
memory	I-Device
chips	O
.	O
</s>
<s>
The	O
first	O
consumer-level	O
CPU	B-General_Concept
deliveries	O
using	O
a	O
22nm	B-Algorithm
process	O
started	O
in	O
April	O
2012	O
with	O
the	O
Intel	B-Device
Ivy	I-Device
Bridge	I-Device
processors	O
.	O
</s>
<s>
The	O
ITRS	O
2006	O
Front	O
End	O
Process	O
Update	O
indicates	O
that	O
equivalent	O
physical	O
oxide	O
thickness	O
will	O
not	O
scale	O
below	O
0.5nm	O
(	O
about	O
twice	O
the	O
diameter	O
of	O
a	O
silicon	O
atom	B-Language
)	O
,	O
which	O
is	O
the	O
expected	O
value	O
at	O
the	O
22nm	B-Algorithm
node	O
.	O
</s>
<s>
This	O
is	O
an	O
indication	O
that	O
CMOS	B-Device
scaling	O
in	O
this	O
area	O
has	O
reached	O
a	O
wall	O
at	O
this	O
point	O
,	O
possibly	O
disturbing	O
Moore	O
's	O
law	O
.	O
</s>
<s>
The	O
22nm	B-Algorithm
process	O
was	O
superseded	O
by	O
commercial	O
14	O
nm	O
FinFET	O
technology	O
in	O
2014	O
.	O
</s>
<s>
On	O
August	O
18	O
,	O
2008	O
,	O
AMD	O
,	O
Freescale	O
,	O
IBM	O
,	O
STMicroelectronics	O
,	O
Toshiba	O
,	O
and	O
the	O
College	O
of	O
Nanoscale	O
Science	O
and	O
Engineering	O
(	O
CNSE	O
)	O
announced	O
that	O
they	O
jointly	O
developed	O
and	O
manufactured	O
a	O
22nm	B-Algorithm
SRAM	B-Architecture
cell	O
,	O
built	O
on	O
a	O
traditional	O
six-transistor	O
design	O
on	O
a	O
300mm	O
wafer	B-Architecture
,	O
which	O
had	O
a	O
memory	O
cell	O
size	O
of	O
just	O
0.1	O
μm2	O
.	O
</s>
<s>
The	O
cell	O
was	O
printed	O
using	O
immersion	B-Algorithm
lithography	I-Algorithm
.	O
</s>
<s>
The	O
22nm	B-Algorithm
node	O
may	O
be	O
the	O
first	O
time	O
where	O
the	O
gate	O
length	O
is	O
not	O
necessarily	O
smaller	O
than	O
the	O
technology	O
node	O
designation	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
25nm	O
gate	O
length	O
would	O
be	O
typical	O
for	O
the	O
22nm	B-Algorithm
node	O
.	O
</s>
<s>
On	O
September	O
22	O
,	O
2009	O
,	O
during	O
the	O
Intel	O
Developer	O
Forum	O
Fall	O
2009	O
,	O
Intel	O
showed	O
a	O
22nm	B-Algorithm
wafer	B-Architecture
and	O
announced	O
that	O
chips	O
with	O
22nm	B-Algorithm
technology	O
would	O
be	O
available	O
in	O
the	O
second	O
half	O
of	O
2011	O
.	O
</s>
<s>
SRAM	B-Architecture
cell	O
size	O
is	O
said	O
to	O
be	O
0.092	O
μm2	O
,	O
smallest	O
reported	O
to	O
date	O
.	O
</s>
<s>
On	O
May	O
2	O
,	O
2011	O
,	O
Intel	O
announced	O
its	O
first	O
22nm	B-Algorithm
microprocessor	O
,	O
codenamed	O
Ivy	B-Device
Bridge	I-Device
,	O
using	O
a	O
FinFET	O
technology	O
called	O
3-D	O
tri-gate	O
.	O
</s>
<s>
IBM	O
's	O
POWER8	B-Device
processors	O
are	O
produced	O
in	O
a	O
22nm	B-Algorithm
SOI	B-Algorithm
process	O
.	O
</s>
<s>
Toshiba	O
announced	O
that	O
it	O
was	O
shipping	O
24nm	O
flash	B-Device
memory	I-Device
NAND	O
devices	O
on	O
August	O
31	O
,	O
2010	O
.	O
</s>
<s>
In	O
2010	O
,	O
Samsung	B-Application
Electronics	O
began	O
mass	O
production	O
of	O
64Gbit	O
NAND	O
flash	B-Device
memory	I-Device
chips	O
using	O
a	O
20nm	O
process	O
.	O
</s>
<s>
Also	O
in	O
2010	O
,	O
Hynix	O
introduced	O
a	O
64Gbit	O
NAND	O
flash	B-Device
memory	I-Device
chip	O
using	O
a	O
20nm	O
process	O
.	O
</s>
<s>
On	O
April	O
23	O
,	O
2012	O
,	O
Intel	B-Device
Core	I-Device
i7	O
and	O
Intel	B-Device
Core	I-Device
i5	O
processors	O
based	O
on	O
Intel	O
's	O
Ivy	B-Device
Bridge	I-Device
22nm	B-Algorithm
technology	O
for	O
series	O
7	O
chipsets	O
went	O
on	O
sale	O
worldwide	O
.	O
</s>
<s>
Volume	O
production	O
of	O
22nm	B-Algorithm
processors	O
began	O
more	O
than	O
six	O
months	O
earlier	O
,	O
as	O
confirmed	O
by	O
former	O
Intel	O
CEO	O
Paul	O
Otellini	O
on	O
October	O
19	O
,	O
2011	O
.	O
</s>
<s>
On	O
June	O
3	O
,	O
2013	O
,	O
Intel	O
started	O
shipping	O
Intel	B-Device
Core	I-Device
i7	O
and	O
Intel	B-Device
Core	I-Device
i5	O
processors	O
based	O
on	O
Intel	O
's	O
Haswell	B-Device
microarchitecture	I-Device
in	O
22nm	B-Algorithm
tri-gate	O
FinFET	O
technology	O
for	O
series	O
8	O
chipsets	O
.	O
</s>
