|Publication number||US5166765 A|
|Application number||US 07/749,772|
|Publication date||Nov 24, 1992|
|Filing date||Aug 26, 1991|
|Priority date||Aug 26, 1991|
|Also published as||DE69228278D1, DE69228278T2, EP0529950A1, EP0529950B1|
|Publication number||07749772, 749772, US 5166765 A, US 5166765A, US-A-5166765, US5166765 A, US5166765A|
|Inventors||Kwing F. Lee, Abbas Ourmazd, Ran-Hong Yan|
|Original Assignee||At&T Bell Laboratories|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Non-Patent Citations (12), Referenced by (105), Classifications (14), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates to the field of silicon MOSFETs, and more particularly, to those having effective channel lengths smaller than 1 μm.
For many years, practitioners in the field of VLSI have strived to integrate an ever increasing number of devices, while maintaining high yield and reliability. However, as device dimensions are reduced to fractions of a micrometer, conventional MOSFET designs fail to achieve desired threshold behavior, and instead, approach ohmic behavior. This difficulty has been addressed in the prior art by increasing the doping of the channel, which tends, undesirably, both to increase the threshold voltage and to increase capacitance. These problems are particularly acute because they militate against reducing the power supply voltage, although such reduction is often desirable in order to satisfy reliability constraints. In practice, the combination of high channel doping, increased capacitance, increased threshold voltage, and reduced supply voltage imposes severe trade-offs between standby power and circuit speed.
Fully depleted silicon-on-insulator (SOI) structures have been proposed as one potential solution to these problems. (See, for example, S. M. Sze, Ed., VLSI Technology, 2d Edition, McGraw-Hill Book Company, New York, 1988, pp. 88-89.) In a SOI structure, the junction capacitance of the device is reduced by incorporating a thick buried oxide directly beneath the channel. Additionally, the use of a thin silicon layer relaxes the need to highly dope the channel in order to prevent punch-through. That is, the rapid vertical modulation of the electric field, together with the concomitant large lateral potential curvature, augments the potential barrier preventing electron flow from the source. Thus, the vertical structure is used to control horizontal leakage.
However, SOI structures are not entirely satisfactory for a number of reasons. For example, the silicon film thickness in SOI structures having 0.1-μm gate lengths is only about 500 Å or even less. The precise thickness of such thin films is difficult to control with current technology. Moreover, the substrates of fully depleted, SOI MOSFETs tend to float electrically, because it is difficult to achieve good body contact to the thin silicon film. However, as the lateral electric field increases, impact-ionization-generated holes tend to become trapped within the floating body, leading to unpredictable subthreshold behavior. Still further, the wafer cost of SOI structures tend to be quite high, simply because the fabrication process is relatively complicated.
In an alternate approach, the deleterious effects of high channel doping are mitigated through the use of retrograde doping. (See, for example, L. C. Parrillo, "CMOS Active and Field Device Fabrication," Semiconductor International (April 1988) p. 67; and D. M. Brown, et al., "Trends in Advanced Process Technology--Submicrometer CMOS Device Design and Process Requirement," Proceedings of the IEEE 74 (December 1986) pp. 1681-1682, 1685-1686. In retrograde doping, a high-energy well implant is used to create a zone of peak dopant concentration that lies below the MOS device region. Punchthrough tends to be suppressed, e.g., because the high doping density reduces the lateral extent of the drain depletion region, preventing the drain field from penetrating into the source region.
However, conventional retrograde doped structures suffer certain disadvantages as well. For example, the high-level doping typically extends more deeply than the junction. As a result, the junction capacitance can still be intolerably high, even though the surface filed may be reduced. Moreover, the exact position of the high doping region, as taught in the prior art, is somewhat arbitrary. However, the precise placement of that region is critically important to the operation of deep submicron devices. Still further, the presence of high-level doping beneath the source and drain regions of conventional retrograde doped structures may contribute undesirable junction capacitance.
Thus, practitioners in the field have hitherto failed to provide a silicon MOSFET design which offers all of the advantages of SOI designs, while preserving the simplicity and cost-effectiveness of conventional VLSI fabrication techniques.
We have discovered a MOSFET design which can be implemented on a silicon substrate and incorporated in an integrated circuit on such substrate, and which can be miniaturized into the submicron regime without incurring severe short-channel effects. The inventive MOSFET includes a gate oxide layer of thickness tox overlying a portion of the substrate; a source region, and a drain region spaced from the source region, each defined in a portion of the substrate and extending to a junction depth tj beneath the principal surface; and first and second channel regions defined within the substrate and located between the source and drain regions. The first channel region at least partially overlies the second channel region, and the gate oxide layer overlies the first channel region. The first channel region extends from the substrate surface to a depth, to be referred to as tSi, which is less than or equal to about 500 Å, and the second channel region extends substantially from tSi to a depth that is is less than or equal to about tj. The room-temperature carrier density in the first channel region is less than about 2×1017 cm-3, and the room-temperature carrier density in the second channel region is greater than about 5×1017 cm-3.
FIG. 1 is a schematic representation of an idealized ground plane structure for a MOSFET.
FIG. 2 is a schematic representation of a practical realization of the structure of FIG. 1.
FIG. 3 is a graph of an idealized doping profile for the structure of FIG. 2.
FIG. 4 is a graphical representation of a scaling rule for silicon MOSFETs which relates the minimum permissible channel length to structural dimensions of the transistor.
FIG. 5 is a graph of drain current versus gate voltage. Compared in the figure are a computer simulation of a MOSFET which has pulse-shaped doping according to the invention, and a MOSFET which has conventional, uniform doping.
According to a well-known mathematical model described in K. K. Young, "Short-Channel Effect in Fully Depleted SOI MOSFETs," IEEE Trans. Electron Devices 36 (1989) p. 399, the potential distribution in the channel region of an SOI structure can be described in terms of a natural length scale λSOI. Let Φ(x,y) denote the potential, where x represents the horizontal (i.e., source-to-drain) direction, and y represents the vertical (i.e., perpendicular to the substrate surface) direction. Significantly, y is equal to zero at the interface between the silicon channel and the gate oxide, and increases with depth into the substrate. Assume that Φ(x,y) can be expressed as a second-order polynomial in y, with each coefficient a function of x. When this expression is substituted into Poisson's equation subject to appropriate boundary conditions, a new mathematical expression of great simplicity emerges. Let Φf (x,y) evaluated at y=0, let the scale length λSOI be defined by ##EQU1## and let φ(x) be defined by
φ(x)=Φf (x)-Φgs +(qNA /εSi)λ2 SOI,
where εSi denotes the dielectric constant of silicon, εox denotes the dielectric constant of the gate oxide, tSi denotes the thickness of the silicon film in the SOI structure, tox denotes the thickness of the gate oxide, q denotes the magnitude of the electronic charge, Φgs denotes the potential difference between the gate and the source, and NA denotes the channel doping density.
Then the horizontal variation of φ(x) is found to obey the equation: ##EQU2## It is this respect that the natural length scale λ emerges. We have found that in order for an SOI device having an effective channel length Leff to operate substantially free of short-channel effects such as punchthrough, the ratio λSOI /Leff should be no more than about 0.1-0.2, although specific applications will dictate more precisely what ratio is small enough.
We have applied a similar theoretical analysis to a structure, the "ground plane" structure, which has different boundary conditions than the SOI structure. As discussed below, we have discovered not only that the ground plane structure is at least as effective as the SOI structure for reducing λ, but also that it can be practically realized in bulk silicon.
The ground plane structure is depicted schematically in FIG. 1. As is apparent from the figure, a gate oxide layer 10 overlies a silicon layer 20. A portion of the silicon layer overlies a buried ground plane 30. Significantly (for the purposes of this idealized picture), the lateral dimensions of the gate oxide, the channel region 40, and the ground plane are assumed to be identical. The ground plane is considered to be maintained at a fixed potential, exemplarily ground potential.
We have found that such a structure has a natural length scale λ, analogous to λSOI, which is approximately given by: ##EQU3## In the long channel regime, i.e., where λ is less than about 0.2Leff, the threshold voltage Vth for this structure, in e.g., an NMOS device, is approximately given by:
Vth =qNA tSiI tox /2εSi +(εSi /εox)(tox /tSi)Vbi, (3)
where Vbi denotes the built-in voltage between the n+ source or drain (assuming the device is NMOS) and the channel. It should be noted that the second term in this expression is due to the ground-plane configuration.
We have compared λSOI to λ for respective SOI and ground plane structures having exemplary gate oxide thickness of 40 Å and exemplary silicon film thickness of 250 521 . For the fully depleted SOI structure, λSOI was 175 Å, whereas for the ground plane structure, λ was only 101 Å.
Depicted in FIG. 2 is an exemplary implementation of the ground plane structure in bulk silicon. Included in the figure are source 50, drain 60, polysilicon gate electrode 70, gate oxide 80, ground plane 90, and compensated channel region 100. Region 100 is analogous to channel region 40 of FIG. 1.
Depicted in FIG. 3 is an exemplary schematic doping for the structure of FIG. 2. Because the doping profile resembles a spatial pulse, we describe the ground plane structure, in its preferred embodiment, as "pulse-shaped doped (PSD)". It should be noted, however, that due to dopant diffusion and other physical effects occurring during processing, an actual doping profile is likely to exhibit some spreading, and thus to deviate form an idealized rectangular pulse shape.
It should be noted that the invention is not limited to devices having channels of a particular conductivity type, but, rather, is generally applicable to PMOS, NMOS, CMOS, and related technologies. For illustrative purposes, we describe, below, a currently preferred method for making an NMOS device which embodies the invention.
At least one self-aligned, silicon-gate, ion-implanted, enhancement-mode NMOS transistor structure is formed by conventional techniques on a lightly doped p-type (100)-silicon wafer coated with conventional layers of, respectively, thermal silicon dioxide and silicon nitride. After lithographic patterning of the silicon nitride, a high-energy boron-ion implant is performed to create channel-stop regions. The field oxide is grown, the silicon nitride is stripped, and the gate oxide is grown, all according to conventional techniques.
Typically, ion implantation is then performed through the gate oxide. (Ion implantation is optionally performed before gate oxide formation.) The specific implantation steps that are performed represent a departure from the prior art, and result in a structure which exhibits behavior characteristic of the buried ground plane.
Exemplarily, boron ions are implanted at an energy of about 2 keV and a flux of about 2×1013 cm-2, resulting in a doping profile extending from about 100 Å to about 500 Å, and having an average doping density of about 1018 cm-3. A second implant is then performed in, exemplarily, three steps using arsenic ions at respective energies of about 10, 20, and 40 keV and respective fluxes of about 2, 8, and 30×1011 cm-2. The arsenic ions are stopped in the first approximately 250 Å of the silicon channel. As a result, this region is doped to an arsenic ion density of about 1018 cm-3. The purpose of the arsenic is to compensate the boron doping in the arsenic-implanted region, such that the carrier density in that region is reduced to a level near the intrinsic carrier density (at room temperature). Typically, the compensated carrier density will be about 1017 cm-3. By contrast, the uncompensated, boron-doped region will typically have a carrier density (at room temperature) of about 1018 cm-3. It should be noted in this regard that the exact implantation conditions will depend on the actual thermal treatment of the substrate during the entire process. Moreover, variations of the exemplary procedure here described will be apparent to the skilled practitioner, in which, for example, the number of separate boron implantation steps is not limited to a single step, and the number of separate arsenic implantation steps is not limited to three.
Polysilicon gates are next conventionally deposited and patterned. Insulating sidewalls are optionally formed, and then source and drain implants are performed according to conventional techniques. A metal silicide is conventionally formed on the gate, source, and drain areas, and then an insulating dielectric layer is deposited and contact windows are opened on the source, drain, and gate, This is followed by conventional deposition and patterning of a metallization layer.
The buried ground plane (region 90 of FIG. 2) is embodied in the uncompensated, boron-doped region lying below the arsenic-implanted region (region 100 of FIG. 2) within the channel. In preferred embodiments, the buried ground plane is laterally confined between the source and drain regions, and is no longer than the written channel length. The top of the buried ground plane is defined by the bottom of the compensated region. The bottom of the buried ground plane is preferably no deeper than the source and drain junction depth, which is typically about 1500 Å. In this regard, a portion of the channel is considered to lie outside the buried ground plane if it has a carrier density (at room temperature, i.e., 20° C.) that is less than 10% of the peak carrier density in the buried ground plane.
The depth of the compensated region, which corresponds to the dimension tSi, is preferably at least about 150 Å, but not more than about 500 Å. (As noted, a typical thickness is about 250 Å.) The junction depths are preferably no more than about 1000 Å. Accordingly, in preferred embodiments, the buried ground plane lies between a depth of about 500 Å or less, and a depth of about 1000 Å or less.
According to our current understanding, transistors are readily fabricated by this technique with effective channel lengths as small as 0.10 μm-0.15 μm, and even as small as 0.075 μm, and with λ no greater than 0.2 times the effective channel length. (Written channel lengths corresponding to effective channel lengths of 0.075-0.10 μm would typically lie in the approximate range 0.10-0.15 μm.) According to Equation 2, the value of λ is determined by the selection of the dimensions tox and tSi. Thus, for an exemplary gate oxide thickness of 40 Å, a λ value of 250 Å is obtained when tSi= 500 Å, and a λ value of 175 Å is obtained when tSi =250 Å.
It should be further noted, in this regard, that a well-known empirical formula, described in J. R. Brews, et al., "Generalized Guide for MOSFET Miniaturization, " IEEE Electron Device Lett. 1, (1980), p. 2, has been used to predict the smallest effective channel length Lmin that can be used without incurring undesirable short channel effects in MOSFETs of conventional, bulk-silicon design. Brews' formula is expressed by
log Lmin =log A+(1/3)log[tj tox (ws +wd)2 ], (4)
where tj denotes the junction depth, A is a constant equal to 0.41 Å-1/3, and ws and wd are the respective source and drain depletion widths. As shown in FIG. 4, a log-log plot of Lmin, as predicted by this equation, against Brews' parameter (the argument of the logarithmic function in the right-hand side of the equation) yields a straight-line curve, labeled E in the figure. We have found that inventive MOSFETs can be designed such that at a given value of Brews' parameter, Lmin is less than 75% (curve F), and even as small as 60% or less (curve G), of the value predicted by Brews' formula.
We conducted a computer simulation of the PSD structure shown in FIG. 2, using a computer code capable of numerically solving the two-dimensional Poisson equation. In the modeled device, the junction depth was 500 Å, the compensated layer thickness tSi was 250 Å, the oxide thickness tox was 40 Å, and the effective channel length Leff was 0.1 μm.
The scaling behavior of the modeled device is shown in FIG. 4 as the data point plotted on curve G. It is evident that Lmin is about 60% of the value predicted by Brews' formula.
Curves A and B of FIG. 5 show the drain current calculated as a function of gate voltage for that structure. Curve A corresponds to a drain-to-source bias of 1.1 V, and curve B corresponds to a bias of 0.1 V. Curves C and D of the same figure are presented for purposes of comparison. They represent the performance of a MOSFET structure uniformly doped at 1018 cm-3, at respective biases of 1.1 V and 0.1 V. It is apparent from the figure that the subthreshold behavior of the uniform doping structure is preserved in the behavior of the PSD structure. The threshold voltage of the PSD structure is lower because of the reduced dopant concentration in the channel region, above the ground plane. In particular, the figure predicts that a threshold voltage less than about 0.6 V can be readily achieved in the inventive transistor structure. We have found, further, that the predicted junction capacitance of the PSD structure is less than one-third that of the corresponding uniformly doped structure.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4242691 *||Sep 18, 1978||Dec 30, 1980||Mitsubishi Denki Kabushiki Kaisha||MOS Semiconductor device|
|US4656492 *||Oct 15, 1985||Apr 7, 1987||Hitachi, Ltd.||Insulated gate field effect transistor|
|US4908681 *||Oct 27, 1988||Mar 13, 1990||Sanyo Electric Co., Ltd.||Insulated gate field effect transistor with buried layer|
|US4943537 *||Jun 27, 1989||Jul 24, 1990||Dallas Semiconductor Corporation||CMOS integrated circuit with reduced susceptibility to PMOS punchthrough|
|1||D. M. Brown, et al., Proceedings of the IEEE 74, Dec. 1986, "Trends in Advanced Process Technology-Submicrometer CMOS Device Design and Process Requirements," pp. 1681-1682, 1685-1686.|
|2||*||D. M. Brown, et al., Proceedings of the IEEE 74, Dec. 1986, Trends in Advanced Process Technology Submicrometer CMOS Device Design and Process Requirements, pp. 1681 1682, 1685 1686.|
|3||H. Nihira et al., Technical Digest, International Electron Devices Meeting, 1978, Washington, D.C., "Anomalous Drain Curent in N-MOSFET's and Its Suppression By Deep Ion Implantations," pp. 487-491.|
|4||*||H. Nihira et al., Technical Digest, International Electron Devices Meeting, 1978, Washington, D.C., Anomalous Drain Curent in N MOSFET s and Its Suppression By Deep Ion Implantations, pp. 487 491.|
|5||J. R. Brews, et al., IEEE Electron Device Lett. 1, 1980, "Generalized Guide for MOSFET Miniaturization," p. 2.|
|6||*||J. R. Brews, et al., IEEE Electron Device Lett. 1, 1980, Generalized Guide for MOSFET Miniaturization, p. 2.|
|7||K. K. Young, IEEE Trans. Electron Devices 36, 1989, "Short-Channel Effect in Fully Depleted SOI MOSFETs," p. 399.|
|8||*||K. K. Young, IEEE Trans. Electron Devices 36, 1989, Short Channel Effect in Fully Depleted SOI MOSFETs, p. 399.|
|9||L. C. Parrillo, Semiconductor International, Apr. 1988, "CMOS Active and Field Device Fabrication," p. 67.|
|10||*||L. C. Parrillo, Semiconductor International, Apr. 1988, CMOS Active and Field Device Fabrication, p. 67.|
|11||*||S. M. Sze, Ed., VLSI Technology, 2nd, McGraw Hill Book Company, New York, 1988, pp. 88 89.|
|12||S. M. Sze, Ed., VLSI Technology, 2nd, McGraw-Hill Book Company, New York, 1988, pp. 88-89.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5329138 *||Jul 29, 1992||Jul 12, 1994||Hitachi, Ltd.||Short channel CMOS device capable of high performance at low voltage|
|US5622880 *||Mar 31, 1995||Apr 22, 1997||Sun Microsystems, Inc.||Method of making a low power, high performance junction transistor|
|US5719422 *||Apr 9, 1997||Feb 17, 1998||Sun Microsystems, Inc.||Low threshold voltage, high performance junction transistor|
|US5773863 *||Aug 18, 1994||Jun 30, 1998||Sun Microsystems, Inc.||Low power, high performance junction transistor|
|US5937293 *||Apr 9, 1998||Aug 10, 1999||Lg Semicon Co., Ltd.||Method of fabricating a source/drain with LDD and halo|
|US5942781 *||Jun 8, 1998||Aug 24, 1999||Sun Microsystems, Inc.||Tunable threshold SOI device using back gate well|
|US5982002 *||Jan 27, 1993||Nov 9, 1999||Seiko Instruments Inc.||Light valve having a semiconductor film and a fabrication process thereof|
|US6078081 *||Jun 7, 1999||Jun 20, 2000||Lg Semicon Co., Ltd.||Semiconductor device for improving short channel effect|
|US6097205 *||Sep 30, 1997||Aug 1, 2000||Semitest, Inc.||Method and apparatus for characterizing a specimen of semiconductor material|
|US6137141 *||Apr 30, 1998||Oct 24, 2000||Lg Semicon Co., Ltd.||MOS device and fabrication method|
|US6271551||Dec 13, 1996||Aug 7, 2001||U.S. Philips Corporation||Si-Ge CMOS semiconductor device|
|US6383876||Jul 27, 2000||May 7, 2002||Lg Semicon Co., Ltd.||MOS device having non-uniform dopant concentration and method for fabricating the same|
|US6432754||Feb 20, 2001||Aug 13, 2002||International Business Machines Corporation||Double SOI device with recess etch and epitaxy|
|US6432777||Jun 6, 2001||Aug 13, 2002||International Business Machines Corporation||Method for increasing the effective well doping in a MOSFET as the gate length decreases|
|US6503805 *||Dec 19, 2000||Jan 7, 2003||Micron Technology, Inc.||Channel implant through gate polysilicon|
|US6657261||Jan 9, 2001||Dec 2, 2003||International Business Machines Corporation||Ground-plane device with back oxide topography|
|US6716682 *||Oct 10, 2002||Apr 6, 2004||Micron Technology, Inc.||SOI CMOS device with reduced DIBL|
|US6872640||Mar 16, 2004||Mar 29, 2005||Micron Technology, Inc.||SOI CMOS device with reduced DIBL|
|US6905918||Dec 29, 2003||Jun 14, 2005||Micron Technology, Inc.||SOI device with reduced drain induced barrier lowering|
|US7009250||Aug 20, 2004||Mar 7, 2006||Micron Technology, Inc.||FinFET device with reduced DIBL|
|US7122411||Aug 19, 2004||Oct 17, 2006||Micron Technology, Inc||SOI device with reduced drain induced barrier lowering|
|US7235468||Aug 10, 2005||Jun 26, 2007||Micron Technology, Inc.||FinFET device with reduced DIBL|
|US7566600||Sep 28, 2006||Jul 28, 2009||Micron Technology, Inc.||SOI device with reduced drain induced barrier lowering|
|US8273617||Feb 18, 2010||Sep 25, 2012||Suvolta, Inc.||Electronic devices and systems, and methods for making and using the same|
|US8377783||Feb 19, 2013||Suvolta, Inc.||Method for reducing punch-through in a transistor device|
|US8400219||Mar 24, 2011||Mar 19, 2013||Suvolta, Inc.||Analog circuits having improved transistors, and methods therefor|
|US8404551||Dec 3, 2010||Mar 26, 2013||Suvolta, Inc.||Source/drain extension control for advanced transistors|
|US8421162||Apr 16, 2013||Suvolta, Inc.||Advanced transistors with punch through suppression|
|US8461875||Feb 18, 2011||Jun 11, 2013||Suvolta, Inc.||Digital circuits having improved transistors, and methods therefor|
|US8525271||Mar 3, 2011||Sep 3, 2013||Suvolta, Inc.||Semiconductor structure with improved channel stack and method for fabrication thereof|
|US8530286||Dec 17, 2010||Sep 10, 2013||Suvolta, Inc.||Low power semiconductor transistor structure and method of fabrication thereof|
|US8541824||Jul 19, 2012||Sep 24, 2013||Suvolta, Inc.||Electronic devices and systems, and methods for making and using the same|
|US8563384||Feb 19, 2013||Oct 22, 2013||Suvolta, Inc.||Source/drain extension control for advanced transistors|
|US8569128||Dec 3, 2010||Oct 29, 2013||Suvolta, Inc.||Semiconductor structure and method of fabrication thereof with mixed metal types|
|US8569156||May 16, 2012||Oct 29, 2013||Suvolta, Inc.||Reducing or eliminating pre-amorphization in transistor manufacture|
|US8599623||Dec 23, 2011||Dec 3, 2013||Suvolta, Inc.||Circuits and methods for measuring circuit elements in an integrated circuit device|
|US8604527||Sep 14, 2012||Dec 10, 2013||Suvolta, Inc.||Electronic devices and systems, and methods for making and using the same|
|US8604530||Sep 14, 2012||Dec 10, 2013||Suvolta, Inc.||Electronic devices and systems, and methods for making and using the same|
|US8614128||Aug 22, 2012||Dec 24, 2013||Suvolta, Inc.||CMOS structures and processes based on selective thinning|
|US8629016||Apr 30, 2012||Jan 14, 2014||Suvolta, Inc.||Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer|
|US8637955||Aug 31, 2012||Jan 28, 2014||Suvolta, Inc.||Semiconductor structure with reduced junction leakage and method of fabrication thereof|
|US8645878||Aug 22, 2012||Feb 4, 2014||Suvolta, Inc.||Porting a circuit design from a first semiconductor process to a second semiconductor process|
|US8653604||Sep 21, 2012||Feb 18, 2014||Suvolta, Inc.||Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer|
|US8686511||Sep 18, 2013||Apr 1, 2014||Suvolta, Inc.||Source/drain extension control for advanced transistors|
|US8713511||Sep 17, 2012||Apr 29, 2014||Suvolta, Inc.||Tools and methods for yield-aware semiconductor manufacturing process target generation|
|US8735987||Jun 6, 2012||May 27, 2014||Suvolta, Inc.||CMOS gate stack structures and processes|
|US8748270||Jul 20, 2012||Jun 10, 2014||Suvolta, Inc.||Process for manufacturing an improved analog transistor|
|US8748986||Jul 26, 2012||Jun 10, 2014||Suvolta, Inc.||Electronic device with controlled threshold voltage|
|US8759872||Dec 17, 2010||Jun 24, 2014||Suvolta, Inc.||Transistor with threshold voltage set notch and method of fabrication thereof|
|US8796048||May 11, 2012||Aug 5, 2014||Suvolta, Inc.||Monitoring and measurement of thin film layers|
|US8806395||Feb 3, 2014||Aug 12, 2014||Suvolta, Inc.||Porting a circuit design from a first semiconductor process to a second semiconductor process|
|US8811068||May 14, 2012||Aug 19, 2014||Suvolta, Inc.||Integrated circuit devices and methods|
|US8816754||Nov 2, 2012||Aug 26, 2014||Suvolta, Inc.||Body bias circuits and methods|
|US8819603||Dec 14, 2012||Aug 26, 2014||Suvolta, Inc.||Memory circuits and methods of making and designing the same|
|US8847684||Feb 19, 2013||Sep 30, 2014||Suvolta, Inc.||Analog circuits having improved transistors, and methods therefor|
|US8863064||Feb 26, 2013||Oct 14, 2014||Suvolta, Inc.||SRAM cell layout structure and devices therefrom|
|US8877619||Jan 23, 2013||Nov 4, 2014||Suvolta, Inc.||Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom|
|US8883600||Dec 21, 2012||Nov 11, 2014||Suvolta, Inc.||Transistor having reduced junction leakage and methods of forming thereof|
|US8895327||Dec 8, 2012||Nov 25, 2014||Suvolta, Inc.||Tipless transistors, short-tip transistors, and methods and circuits therefor|
|US8916937||Feb 14, 2014||Dec 23, 2014||Suvolta, Inc.||Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer|
|US8937005||Oct 4, 2013||Jan 20, 2015||Suvolta, Inc.||Reducing or eliminating pre-amorphization in transistor manufacture|
|US8963249||May 30, 2014||Feb 24, 2015||Suvolta, Inc.||Electronic device with controlled threshold voltage|
|US8970289||Jan 22, 2013||Mar 3, 2015||Suvolta, Inc.||Circuits and devices for generating bi-directional body bias voltages, and methods therefor|
|US8975128||Nov 18, 2013||Mar 10, 2015||Suvolta, Inc.||Electronic devices and systems, and methods for making and using the same|
|US8976575||Aug 29, 2013||Mar 10, 2015||Suvolta, Inc.||SRAM performance monitor|
|US8988153||Mar 9, 2013||Mar 24, 2015||Suvolta, Inc.||Ring oscillator with NMOS or PMOS variation insensitivity|
|US8994415||Mar 1, 2013||Mar 31, 2015||Suvolta, Inc.||Multiple VDD clock buffer|
|US8995204||Jun 23, 2011||Mar 31, 2015||Suvolta, Inc.||Circuit devices and methods having adjustable transistor body bias|
|US8999861||May 11, 2012||Apr 7, 2015||Suvolta, Inc.||Semiconductor structure with substitutional boron and method for fabrication thereof|
|US9006843||Feb 24, 2014||Apr 14, 2015||Suvolta, Inc.||Source/drain extension control for advanced transistors|
|US9041126||Sep 5, 2013||May 26, 2015||Mie Fujitsu Semiconductor Limited||Deeply depleted MOS transistors having a screening layer and methods thereof|
|US9054219||Feb 5, 2014||Jun 9, 2015||Mie Fujitsu Semiconductor Limited||Semiconductor devices having fin structures and fabrication methods thereof|
|US9070477||Dec 12, 2013||Jun 30, 2015||Mie Fujitsu Semiconductor Limited||Bit interleaved low voltage static random access memory (SRAM) and related methods|
|US9093469||May 9, 2014||Jul 28, 2015||Mie Fujitsu Semiconductor Limited||Analog transistor|
|US9093550||Jan 31, 2013||Jul 28, 2015||Mie Fujitsu Semiconductor Limited||Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same|
|US9093997||Nov 15, 2013||Jul 28, 2015||Mie Fujitsu Semiconductor Limited||Slew based process and bias monitors and related methods|
|US9105711||Dec 19, 2013||Aug 11, 2015||Mie Fujitsu Semiconductor Limited||Semiconductor structure with reduced junction leakage and method of fabrication thereof|
|US9111785||Jul 31, 2013||Aug 18, 2015||Mie Fujitsu Semiconductor Limited||Semiconductor structure with improved channel stack and method for fabrication thereof|
|US9112057||Sep 18, 2012||Aug 18, 2015||Mie Fujitsu Semiconductor Limited||Semiconductor devices with dopant migration suppression and method of fabrication thereof|
|US9112484||Dec 20, 2013||Aug 18, 2015||Mie Fujitsu Semiconductor Limited||Integrated circuit process and bias monitors and related methods|
|US9112495||Mar 15, 2013||Aug 18, 2015||Mie Fujitsu Semiconductor Limited||Integrated circuit device body bias circuits and methods|
|US9117746||Jul 21, 2014||Aug 25, 2015||Mie Fujitsu Semiconductor Limited||Porting a circuit design from a first semiconductor process to a second semiconductor process|
|US9154123||Aug 19, 2014||Oct 6, 2015||Mie Fujitsu Semiconductor Limited||Body bias circuits and methods|
|US9184750||May 10, 2013||Nov 10, 2015||Mie Fujitsu Semiconductor Limited||Digital circuits having improved transistors, and methods therefor|
|US9196727||Nov 6, 2014||Nov 24, 2015||Mie Fujitsu Semiconductor Limited||High uniformity screen and epitaxial layers for CMOS devices|
|US9224733||Oct 4, 2013||Dec 29, 2015||Mie Fujitsu Semiconductor Limited||Semiconductor structure and method of fabrication thereof with mixed metal types|
|US9231541||Sep 29, 2014||Jan 5, 2016||Mie Fujitsu Semiconductor Limited||Analog circuits having improved transistors, and methods therefor|
|US9236466||Oct 5, 2012||Jan 12, 2016||Mie Fujitsu Semiconductor Limited||Analog circuits having improved insulated gate transistors, and methods therefor|
|US9263523||Feb 24, 2014||Feb 16, 2016||Mie Fujitsu Semiconductor Limited||Advanced transistors with punch through suppression|
|US9268885||Feb 28, 2013||Feb 23, 2016||Mie Fujitsu Semiconductor Limited||Integrated circuit device methods and models with predicted device metric variations|
|US9276561||Jul 24, 2015||Mar 1, 2016||Mie Fujitsu Semiconductor Limited||Integrated circuit process and bias monitors and related methods|
|US9281248||Apr 30, 2014||Mar 8, 2016||Mie Fujitsu Semiconductor Limited||CMOS gate stack structures and processes|
|US9297850||Sep 15, 2014||Mar 29, 2016||Mie Fujitsu Semiconductor Limited||Circuits and methods for measuring circuit elements in an integrated circuit device|
|US9299698||Jun 25, 2013||Mar 29, 2016||Mie Fujitsu Semiconductor Limited||Semiconductor structure with multiple transistors having various threshold voltages|
|US9299801||Mar 14, 2013||Mar 29, 2016||Mie Fujitsu Semiconductor Limited||Method for fabricating a transistor device with a tuned dopant profile|
|US9319013||Aug 19, 2014||Apr 19, 2016||Mie Fujitsu Semiconductor Limited||Operational amplifier input offset correction with transistor threshold voltage adjustment|
|US9319034||Jun 30, 2015||Apr 19, 2016||Mie Fujitsu Semiconductor Limited||Slew based process and bias monitors and related methods|
|US20030034516 *||Sep 7, 2001||Feb 20, 2003||Tso-Hung Fan||Structure of a non-volatile memory|
|US20050020041 *||Aug 19, 2004||Jan 27, 2005||Mouli Chandra V.||SOI device with reduced drain induced barrier lowering|
|US20050205931 *||Jan 28, 2005||Sep 22, 2005||Mouli Chandra V||SOI CMOS device with reduced DIBL|
|US20070026652 *||Sep 28, 2006||Feb 1, 2007||Mouli Chandra V||SOI device with reduced drain induced barrier lowering|
|EP0697740A2 *||Aug 16, 1995||Feb 21, 1996||Sun Microsystems, Inc.||Low threshold voltage, high performance junction transistor|
|WO1997023000A1 *||Nov 26, 1996||Jun 26, 1997||Philips Electronics N.V.||SEMICONDUCTOR FIELD EFFECT DEVICE COMPRISING A SiGe LAYER|
|WO2000057480A1 *||Mar 16, 2000||Sep 28, 2000||France Telecom||Novel semiconductor device combining the advantages of solid and soi architectures, and method for making same|
|WO2011163169A1 *||Jun 21, 2011||Dec 29, 2011||Suvolta, Inc.||Advanced transistors with punch through suppression|
|U.S. Classification||257/345, 257/E29.109, 257/392, 257/E29.063, 257/E29.055|
|International Classification||H01L29/10, H01L29/36, H01L29/78|
|Cooperative Classification||H01L29/36, H01L29/105, H01L29/1083|
|European Classification||H01L29/10D2B3, H01L29/10F2B2, H01L29/36|
|Aug 26, 1991||AS||Assignment|
Owner name: AMERICAN TELEPHONE AND TELEGRAPH COMPANY, A CORPOR
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:LEE, KWING FAI;OURMAZD, ABBAS;YAN, RAN-HONG;REEL/FRAME:005825/0133
Effective date: 19910815
|Apr 15, 1996||FPAY||Fee payment|
Year of fee payment: 4
|Apr 27, 2000||FPAY||Fee payment|
Year of fee payment: 8
|May 24, 2004||FPAY||Fee payment|
Year of fee payment: 12