- Deep Learning and Digital Signal Processing: A Conversation with Cadence's Chris Rowen
- Jeff Bier’s Impulse Response—Your Autonomous Vehicle Is Ready Now…For Your Living Room
- Case Study: BDTI Expertise Enables Selection of the Best Processor for Vision Applications
- CEVA-X Processor Cores Tout DSP, Control Plane Balance for Wireless
- Texas Instruments' SoCs Aspire to Bring Advanced Driver Assistance to the Masses
BDTI Releases Benchmark Results for Toshiba's Venezia Platform
BDTI recently completed a benchmark analysis of the Toshiba MeP “Media embedded Processor” core and “IVC2” SIMD coprocessor, both of which are used in Toshiba’s Venezia mobile multimedia platform.
The MeP is a licensable core that is intended to be used as a building block in multi-core, multimedia-oriented SoCs, typically with multiple MeP cores on a chip. Each MeP core can be customized with specialized instructions, co-processors, and memory sizes.
The base MeP core is a single-issue 32-bit RISC architecture that uses a mixed-width 16/32-bit instruction set. The MeP core is provided as a soft macro, and Toshiba reports that it has already been licensed to several customers and universities.
Venezia is a licensable, scalable multicore platform that can include up to eight MeP cores, each of which can be augmented with Toshiba’s IVC2 “Image Processing VLIW co-processor.” IVC2 adds a 64-bit SIMD data path and support for three-way VLIW instructions. The IVC2 data path can support, for example, four 16-bit multiplies in parallel.
Venezia is multi-threaded, and the platform includes a thread scheduler. (CriticalBlue has already ported its multicore performance analysis tool, “Prism,” to Venezia.) The Venezia platform is intended to operate as a multimedia coprocessor in an SoC, typically attached to an ARM or MIPS CPU. In addition to offering the Venezia platform for licensing, Toshiba is currently developing its own Venezia-based SoC for mobile applications.
Each of the MeP cores in the Venezia platform can be customized to efficiently run specific portions of a multimedia application. Toshiba has demonstrated a 65 nm Venezia evaluation chip containing eight MeP cores augmented with IVC2 coprocessors; the processors in this chip execute at 333 MHz. According to Toshiba, an MeP core plus IVC2 co-processor and caches (collectively referred to as a “media processing engine”) requires 1.3 mm² in a 65 nm process.
BDTI has evaluated the DSP performance of a single MeP core plus IVC2 coprocessor using the BDTI DSP Kernel Benchmarks™, a suite of 12 digital signal processing algorithms. The benchmark results obtained on the twelve individual BDTI DSP Kernel Benchmarks are used to generate a BDTIsimMark2000™ score, which is a summary measure of digital signal processing speed. A higher score indicates a faster processor.
Based on the 333 MHz clock speed of the Venezia evaluation chip (Venezia-EX), a single “media processing engine” comprising an MeP plus an IVC2 achieves a projected BDTIsimMark2000 score of 2620. This result is similar to that of a single Texas Instruments C55x+ core at 400 MHz or a mid-range Analog Devices Blackfin chip. Since Venezia-based chips are expected to include multiple media processing engines, however, their overall performance will be much higher.
On a per MHz basis, the MeP plus IVC2 scores 7.9 BDTIsimMark2000/MHz. Neglecting differences in clock speed, this result is quite similar to that of the ARM Cortex-A8 with NEON, which has a result of 7.6 BDTIsimMark2000/MHz. ARM is targeting a higher clock speed with the Cortex-A8, however, with clock speed projections ranging from 600 MHz to 1 GHz in 65 nm (depending on the fabrication optimizations used). But the ARM core is also a lot bigger; ARM characterizes the area of the Cortex-A8 as being < 4mm² in a 65 nm process, and this figure excludes NEON.
Based on BDTI’s benchmark results, it’s clear that a Venezia-based multimedia chip with eight media processing engines (like the Toshiba evaluation chip) would be a powerful multimedia processing engine. Toshiba has said that it plans to increase clock speeds and add functionality to the cores, along with increasing the number of cores supported from 8 to 16 or 32. Toshiba believes that Venezia’s programmability and its ability to support many different codecs using customized MeP cores and coprocessors are key advantages relative to solutions based on hardwired codec accelerators.