Programmable Logic/Verilog Always and Initial
This page is going to look at the Verilog keywords always and initial
Synchronous and Asynchronous
always blocks can be either synchronous or asynchronous structures. The instructions inside these structures are said to occur synchronously with the given condition, or asynchronously (if no condition is specified).
Initial blocks are non-synthesisable blocks. These are normally used in test benches. Initial blocks cause certain instructions to be performed at the beginning of the simulation, before any other instructions operate. Initial blocks only operate once.
Always blocks describe things that should repeat indefinitely, or things that should repeat on a given synchronization condition. An always block with no condition is asynchronous:
always begin ... end
This block of code will continuously execute regardless of the clock signal of the circuit.
Hardware modules may not be instantiated inside an always block. All of the always blocks in a module are considered to be parallel blocks of hardware. Likewise, modules are considered to be separate hardware blocks that operate in parallel. Functions, however, can be instantiated in an always block.
A wire or register may not be written to by more than one always block. A wand or wor can, however, be written by multiple blocks.
The always @ structure is a synchronous condition structure. It takes the form:
always @(<condition> <signal>)
<condition> can be either posedge, negedge, or omitted. The
<signal> parameter is the signal to be synchronized against (usually a clock signal). For instance, if we want a particular block of code to execute at the positive edge of every clock pulse, we would write:
always @(posedge clock)
If we do not put in either posedge or negedge qualifiers, the always block will be triggered at every change (every positive and negative edge of the signal). For example:
will perform at the positive and negative edges of the clock signal.
Always blocks can be considered to be circuit constructs where the input to that circuit is controlled by a latch. The event that triggers the always block is considered to be the clock input to the latch. The circuit only receives new input when the correct condition is received on the latch's trigger input.
The keywords posedge and negedge are edge trigger conditions, and are only used with always blocks.