LaMeres' Research Overview
MSU's FPGA-Based Research Computer (LEFT) Flying the HASP Balloon System on 9/2/13 and (RIGHT) Flying on UP Aerospace SL-9 Sounding Rocket on 10/23/14.
Exploiting Programmable Fabrics for Effective Computing
Reconfigurable digital circuitry has always provided inherent design flexibility.
Historically, this flexibility has come at the expense of performance. However, with
advances in IC fabrication technology, programmable logic performance has advanced
to the point where it is meeting the computation needs of modern applications. This
has created a paradigm shift in the way digital circuitry can be implemented. If programmable
logic cells can perform as well as dedicated IC blocks, then the standard VLSI design
flow will need to be reinvented. Reprogrammable fabrics now have the capacity to contain
not only custom hardware but multiple soft processor cores. This capability enables
computing approaches such as single-chip hardware accelerated processors, dynamically
scalable parallel processing, and reconfigurable computing. The capability that now
exists in computing hardware makes the effective partitioning between hardware and
software a difficult challenge due to the endless implementation possibilities.
Reconfigurable fabrics also have enabled novel architectures to address the robustness of a computer system. Redundancy (both static and dynamic) can be used to detect and recover from faults and spatial avoidance of faults can be used to extend lifetime of a part. These opportunities for fault tolerance are of great interest to the military and aerospace industry due to their unique need for robust computing platforms.
Currently, research is being conducted in the ECE department at MSU in the area of effective hardware/software partitioning using soft processors on FPGAs. Research is also being conducted on the design of a radiation tolerant computing system for the aerospace industry which exploits partial reconfiguration of an FPGA to spatially move soft processors to different locations on the FPGA in order to avoid radiation strikes. Reconfiguration is also used to dynamically recover from a non-damaging radiation strike. Sponsors of this work include NASA, the Montana Space Grant Consortium, the National Space Grant Consortium, and the Office of Naval Research.
The picture shown here is a Radiation Tolerant Many Core Computing System implemented on a Xilinx Virtex-6 FPGA. This system was developed for NASA to help increase reliability in interplanetary flight systems. This system contains 16 soft processors. At any given time, 3 of the processors are used in Triple Modular Redundancy (TMR) to check for faults due to radiation. Upon a soft radiation strike, the TMR system reboots and resynchronizes the faulted processors. If the fault occurs in the reconfiguration RAM of the FPGA, the system performs partial reconfiguration on the effected processor in order to recover. If the fault is unrecoverable, the system brings on a new spare processor to form the TMR configuration and marks the damaged area as unusable.
- LaMeres "FPGA-Based Radation Tolerant Computing" 6/14/14)
- LaMeres "Research Overview in 20min" (9/19/14)
- LaMeres "Research Overview in 10min" (9/19/14)
- LaMeres "Online Learning in STEM" (11/14/14)
- LaMeres "Conducting Research in Space" (1/15/15)
Current Research Projects
Artemis "Radiation Tolerant Computing Mission on the International Space Station (RTcMISS)"
- Artemis CAD Model, Rev001, SolidWorks 2014+ (150Mb zip, 1/15/15)
- Artemis Theory of Operation, Rev001 (PDF, 1/15/15)
- Artemis Yr1 Report Supporting Docs (68Mb zip, 5/4/15)
RadSat - Small Satellite Demonstration of a Radiation Tolerant Computing System
- SL-9 Launch, 10/23/14, 408,000 ft (1min)
- KTVM News Story about SL-9 Launch, 10-23-14 (1M)
- SL-9 Flight Pictures (200 Mb zip, 2/10/15)