Swallow Many-core Research Project
The Swallow many-core project, led by Dr Simon Hollis, aims to produce a 480 processor embedded system, based on the XMOS XS1 architecture. The system will be used to explore how large numbers of lightweight cores can be effectively used. The platform is designed to allow energy monitoring of both the cores and the communication, with the aim of producing a system that can illustrate the energy use of parallel, communicating algorithms.
EACOP: the Energy-Aware Computing Platform
Energy-aware computing is a challenge that requires investigating the entire "system stack" from application software and algorithms, via programming languages, compiler tool chains, operating systems, processor instruction sets and micro architectures, down to the hardware. While hardware can be designed to save a modest amount of energy, the potential for savings are far greater at the higher levels of abstraction; the greatest savings are expected from energy consumption-aware software.
To achieve this, transparency needs to be introduced in the system stack so that energy consumption values can be propagated from the hardware platform to the upper layers in the system stack. The EACOP project, led by Dr Kerstin Eder, bridges exactly this gap between hardware and software by creating a computing platform that provides real-time energy monitoring of computations. It is supported by University of Bristol Research Strategy Funding.
ENTRA: Whole Systems ENergy TRAnsparency
The goal of the ENTRA project is to promote energy-aware system development, using advanced program analysis and energy modelling techniques to make predictions of energy usage available to the system developer and tool chain. This will enable optimizations both during code development and at run-time and lead to more energy-efficient computer systems.
The Effect of Compiler Optimisations on Energy Consumption
This project studied the effect that compiler optimisation have on energy consumption. A extensive amount of optimisations were analysed across many benchmarks and platforms. The study used a fractional factorial design to ensure that the effect of each optimisation could be seperated.
NEMIAC: Nano-Electro-Mechanical Integration And Computation
Nano-Electro-Mechanical Integration And Computation (NEMIAC) is an exciting FP7 funded project at the cutting edge of semiconductor electronics to build a processor using a fundamentally new digital logic technology using nano-electro-mechanical (NEM) relays. The promise of NEM relays is the elimination of subthreshold or leakage current, which limits the use of conventional CMOS technologies in emerging ultra-low power technologies such as wireless sensor networks. Innovation is required at the technology level, in fabricating reliable and miniaturised relays, at the logic design level, in designing logic networks with the new switching elements, and in modelling and system design. The intended final demonstrator is a 4 bit microprocessor with a reliability of 1 million switching cycles.
The consortium is led by IBM Zurich who have a very strong track record in disruptive technologies for nanoscale electronics and is one of the world leaders in innovation in Information Technology. The other industrial partner is STMicroelectronics, while the academic partners are the University of Bristol UK, Royal Institute of Technology (KTH) Sweden, École Polytechnique Fédérale De Lausanne (EPFL) Switzerland and Lancaster University UK. The European Commission has awarded €2.44 million to the consortium.
Dr. Pamunuwa is the PI from University of Bristol who contribute in modelling, simulation and design activities. Dr. Sunil Rana, a PDRA, and Tyson Tian Qin, a PhD student, are the other members of the Bristol team.
DeSyRe: On-demand System Reliability
The DeSyRe project performs research on the design of future reliable Systems-on-Chip. These are systems that guarantee continuous and correct operation in the existence of different types of faults. It is a well known fact that various systems are extremely sensitive to faults; typical examples are medical embedded systems, in which a single malfunction will put the life of a patient in danger. At the increasing fault-rates, expected in the upcoming technology generations, DeSyRe will develop new design techniques for future SoCs, improving their reliability and reducing their power and performance overheads for fault-tolerance.
DeSyRe is an EU project in collaboration with six other academic institutions. Prof Dhiraj Pradhan is leading the work at Bristol to develop software modules for online testing, checkpointing and detection and correction of faults.
Process Variation Aware Synthesis of Nano-CMOS Circuits
In the context of development of nanoscale CMOS technology, the challenges for design engineers have increased. Design decisions are based on the nominal values of power, and performance decisions are based on the assumption that all the transistors are alike across dies and wafers. However, in reality, when the transistors are quite small, the transistor parameters vary from die to die or even in the same die. In other words, each transistor in a die or wafer is different. The transistor parameter variations may be due to several factors, including changes in dielectric thickness, substrate, polysilicon, and implant impurity levels; surface charge; and lithographic process. Thus, the design decisions based on the nominal models may not be correct because the models are either overestimations or underestimations of actual values; hence, the resultant circuits may not be optimal. Accurate modelling and estimation of all the forms of power and performance accounting process variation, including all leakage components, are crucial for making correct decisions on design for manufacturing. Unfortunately, no comprehensive model or tools exist for accurate estimation during digital system design when the target technology is nanoscale CMOS. Some forms of the power dissipation, such as due to gate-oxide/junction tunneling, have not received much attention. Process-variation-aware modelling of any of the (leakage) current components or delay is significantly challenging when treated at system level. Moreover, no tool exists that can provide power-performance design space exploration when a system is a behavioural hardware description language (HDL).
This project, led by Prof Dhiraj Pradhan, intends to develop process variation aware architectural power-delay statistical models and estimator that can be used for fast and accurate estimation of power-performance values of nanoscale-CMOS design alternatives of digital systems expressed as a behavioural HDL.
Yield and Reliability Enhancement Techniques for Novel Memory Devices
Recently developed memory architectures based on resistive-variable devices such as Phase Charge Memories, Programmable Metallization Cell or memristors have reliability issues very different from those affecting CMOS- based memories. These novel memories although based on different technologies, all share the principle of storing information as the resistance value imposed to a resistive- variable devices and consequently are prone to very different type of faults that may occur. Led by Prof Dhiraj Pradhan, this project proposes to exploit both information and architectural redundancies to enhance reliability and yield of these devices.
High performance computing
Accelerating Ligand-Based Virtual Screening
Technology Strategy Board funded Knowledge Transfer Partnership (KTP) with Cresset BioMolecular Discovery Ltd. to implement new GPU-based algorithms for Ligang-based screening. More details are available on the Cresset website.
Adaptive Multi-Resolution Massively-Multicore Hybrid Dynamics
EPSRC-funded HPC software project in collaboration with Prof Adrian Mulholland and Dr Christopher Woods to develop a new way to submit and manage your HPC computing jobs, called Conspire. Using this, python, perl or bash job scripts can be turned into intuitive graphical interfaces, which can be used to submit and manage your HPC jobs across all of the HPC clusters to which you have access. Dr Ben Long is the PDRA on this project. More information on the project website.
BUDE: Bristol University Docking Engine
BBSRC-funded project for the further development of BUDE, a many-core accelerated molecular docking code, in collaboration with Dr Richard Sessions in Biochemistry. BUDE already scales across hundreds of GPUs, and is starting early trials with academic and industrial partners. is the PDRA on this project, starting September 2012. Dr Amaurys Ibarra is the PDRA on this project, starting September 2012
e-Infrastructure South Centre for Innovation
The e-Infrastructure South Consortium's Centre for Innovation project has awarded an EPSRC-funded £3.8m to procure shared High Performance Computing resources. This is in collaboration with Oxford, Southampton and UCL and has been used to establish two significant systems: Emerald, the largest GPU cluster in the UK in March 2012, and Iridis, a 12,000 core x86 cluster.
EESI-2: European Exascale Software Project 2
As part of the FP7-funded European Exascale Software Project 2, Simon McIntosh-Smith is chairing the Energy Efficient Computing working group.
Porting HPC codes to Emerald
In an EPSRC-funded University of Bristol internal competition, the Micro group won £31K to support the porting of HPC codes developed within the e-Infrastructure South consortium to the Emerald GPU supercomputer. Dan Curran, a recent CS graduate and GPU porting expert, was appointed in July 2012 and is currently working with Prof Chris Allen to enhance his CFD code so that it can exploit heterogeneous many-core systems, such as GPU accelerated servers.
RIVERAS: Robust Integrated Verification of Autonomous Systems
Dr Kerstin Eder is leading a multi-disciplinary research team to develop techniques and methodologies that can be used to design autonomous intelligent systems that are verifiably trustworthy. This enables engineers to ensure that the strict safety requirement necessary for such systems are met, allowing for a more rapid route to market while at the same time building customer confidence.
RoboSafe: Trustworthy Robotic Assistants
The development of robotic assistants is being held back by the lack of a coherent and credible safety framework. Consequently, robotic assistant applications are confined either to research labs or, in practice, to scenarios where physical interaction with humans is purposely limited. So, how can we enhance robots so that they can participate in sophisticated interactions with humans in a safe and trustworthy manner? The RoboSafe project aims to verify high-level behaviours of robotic assistants during interaction with humans, i.e. not only whether the robot makes safe moves, but whether it knowingly or deliberately makes unsafe moves.