Post-Silicon Validation, Design Methodology, and Constraint Satisfaction
The Post-Silicon Validation, Design Methodology, and Constraint Satisfaction group has three main missions:
Despite the improvements in both dynamic and formal pre-silicon verification tools, post-silicon functional validation remains a crucial step in ensuring the functional correctness of the design.
We aim to establish a unified verification methodology, spanning pre-silicon RTL simulation, acceleration, and functional validation on actual silicon.
As part of this work, we have developed Threadmill, a bare-metal user-directed exerciser for acceleration and silicon-based verification.
With the growth in complexity of processor designs, the number of functional bugs grows beyond the capability of verification to handle. We are seeking to improve the logic design process so that the design is created with less functional bugs.
Our primary goal is to provide a constraint satisfaction solver as a core technology for the functional verification tools in our area. Beyond verification, we use our expertise and solving capabilities to solve complex constraint satisfaction problems in other areas, such as design floorplanning, pipeline scheduling, workforce management, truck configuration, and more.