|Publication number||US7408258 B2|
|Application number||US 10/783,662|
|Publication date||Aug 5, 2008|
|Filing date||Feb 20, 2004|
|Priority date||Aug 20, 2003|
|Also published as||US20050040513, WO2005020648A2, WO2005020648A3|
|Publication number||10783662, 783662, US 7408258 B2, US 7408258B2, US-B2-7408258, US7408258 B2, US7408258B2|
|Inventors||Peter C. Salmon|
|Original Assignee||Salmon Technologies, Llc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (107), Non-Patent Citations (6), Referenced by (3), Classifications (33), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority to provisional Application Ser. No. 60/496,948 filed Aug. 20, 2003.
This invention relates to apparatus and method for building microelectronic modules having one or two conductive faceplates, imprinting methods, and their application to blade servers and supercomputers.
Conventional printed circuit boards are constructed using copper signal planes laminated between glass-epoxy layers. Copper planes (foils) are also used for ground and for power supply voltages. For conventional epoxy laminate boards, trace and space dimensions are typically 100 microns each for a trace pitch of 200 microns, and hole diameters for plated through holes are typically 340 microns or more. More advanced boards are available from companies such as Unitive, Inc. of Research Triangle Park, N.C., USA. Unitive's boards employ BCB, a spin-on resin available from Dow Chemical Company, rather than glass-epoxy. For a copper trace thickness of 2-3 microns, these boards achieve trace widths as small as 12 microns and trace spacing as small as 13 microns; traces on different levels are connected using vias with a diameter of 35 microns and a pitch of 45-55 microns.
At 10 GHz the dielectric constant of BCB is 2.65 and its dissipation factor is 0.002. Its coefficient of thermal expansion (CTE) is 52 ppm/° C., and its moisture uptake is 0.14% by weight (as reported by Dow Chemical). Moisture uptake is critical because small amounts of absorbed water can substantially raise the effective dielectric constant, and a higher dielectric constant may effectively prohibit high frequency operation. The CTE of copper is 17 ppm/° C.; various researchers list the CTE of silicon as 2.6-4.2 ppm/° C. The coefficients of thermal expansion are important because the manufacturing process typically requires thermal cycles, and mismatches in CTE between materials in a stacked configuration result in mechanical stresses that can damage the board, or components attached to it. Additional thermal cycling is typically present during operation of the board, but usually this variation is less than during manufacturing and assembly.
In recent years, imprinting methods have been developed for several products. An example is the compact disc (CD) that has been manufactured by pressing a master tool into a plastic material, leaving an imprint of the desired pattern. A feature size of one micron and a fabrication cost less than a dollar per square foot have been reported. For both integrated circuit manufacture and printed circuit board manufacture, the imprinting method has potential to be an inexpensive patterning method compared with current photolithographic patterning methods. Photolithography has been the mainstay of integrated circuit patterning for many decades; it generally requires highly sophisticated tools for projecting a beam of light through a mask onto photosensitive materials. A fabrication facility to process silicon wafers by this method typically costs more than US$1 B today. By contrast, imprinting requires unsophisticated tools, yet it can produce fine features, smaller than 100 nanometers in some applications. The tools required for imprinting generally include a laminating press with provisions for aligning the layers, and for heating the thermoplastic material to be patterned. Cold embossing has also been developed using glass tools with embossed features etched therein, and UV curable dielectrics.
Electroplating is typically used to build up the copper layers, and chemical/mechanical polishing (CMP) is preferably used for planarizing each layer after plating. Imprinting and CMP methods can be combined to implement a dual damascene process using copper as the conductor material. Dual damascene processes are known in the art; “dual” refers to the fact that two depths of copper are implemented: trenches used for creating traces have a lesser depth than cylindrical holes for vias. The combination of tools for imprinting, plating and CMP may cost less than 1% of the cost of equivalent photolithographic tools. Other conductors may be used instead of copper, but copper offers a compelling combination of good electrical and thermal conductivity, adequate mechanical properties (especially in the form of dispersion strengthened copper, to be further discussed), and an infrastructure of existing tools and processes for drilling, electroplating, etching, and polishing at reasonable cost.
Liquid crystal display (LCD) panel fabrication plants are now being built for glass panels measuring 1870×2200 mm. The thickness of these glass panels is 0.7 mm, similar to the preferred thickness of 0.6 mm for copper substrates of the current invention. This means that an infrastructure of semiconductor processing equipment, particularly including thin film coating and etching equipment could be adapted to handle copper substrates in panel sizes up to around 2 meters square. This may be useful for coating thin film adhesion layers and seed layers on large panels of the current invention, and for plasma etching dielectric materials, as will be further described. The photolithographic patterning capability for large panels, generally employing step and repeat exposure systems (“steppers”), may also be used for fabricating the embossing tools described herein.
The preferred method of imprinting discussed herein uses an embossing tool in the form of a flexible foil, hereinafter called a “toolfoil”. It is also possible to use rigid embossing tools, particularly if release agents are applied to the tool to aid in separation; also if the impressions are shallow they require a relatively small force for release. A release agent comprised of low surface energy material such as teflon is also preferably provided on the toolfoils discussed herein. One method of making a toolfoil is to electroplate nickel in an additive process to create a master or “father” foil. The sidewalls of the plated features preferably have an angle of about 5° to the vertical. This release angle is useful so that negatives of fathers can be made to produce “mothers”, and negatives of mothers are made to produce “sons”, which are the equivalent of photo-tool working plates. Suitable toolfoils can be obtained from Tecan Components Ltd., Dorset, England. If the toolfoil is used to implement a dual damascene process, then two nickel thicknesses are required and two photo-tools (glass masks) will be used in the fabrication of the master.
An alternative embodiment of the imprinting method may be used for large patterns that require a step and repeat methodology. Molecular Imprints of Austin, Tex., USA, has developed a step and flash imprint lithography process called S-Fil. In this process, a substrate is coated with an organic planarization layer. Then a low viscosity photo-polymerizable imprint solution is dispensed on the surface. A surface treated transparent template bearing patterned relief structures is aligned over the coated substrate. The template is lowered into contact with the substrate, thereby displacing the solution, filling the imprint field, and trapping the photo-polymerizable imprint solution in the template relief. Irradiation with UV light through the backside of the template cures the solution. The template is then separated from the substrate leaving a relief image on the surface that is a replica of the template pattern. A short halogen etch is used to clear any remaining thin webs of undisplaced material. A subsequent reactive ion etch into the planarization layer may be used to amplify the aspect ratio of the relief image.
Liquid crystal polymer (LCP) is a new dielectric material that has recently become available for imprinting applications in the printed circuit board arena. An example of this material is R/Flex 3800 available from Rogers Corp., Circuit Materials Division, Chandler Arizona. It is available with a CTE matched to copper at 17 ppm/° C. Melting points of 280° C. and 315° C. are available, with thickness varying from 25 microns to 100 microns. From 1-10 GHz the dielectric constant is 2.9 and the dissipation factor is 0.002. The moisture uptake is 0.04% by weight (compared with 0.14% for BCB), resulting in good stability for high frequency applications.
Dispersion strengthening is a method for improving the strength properties of copper, without seriously affecting its electrical and thermal conductivity. Cold rolled sheets of dispersion strengthened copper (DSC) known as Glidcop are available from SCM Metal Products, Inc., North Carolina. For use as a substrate for a printed circuit of the current invention, this material is available in thickness ranging from 125-625 microns. By incorporating minute amounts of aluminum oxide to pin the grain boundaries of the copper, the yield strength of DSC is typically improved by about 10 times, while the thermal and electrical properties are degraded by less than 1%.
Electroplating methods are well known in the art. Current processes support fabrication of via structures with aspect ratios (depth:diameter) as great as 10. Using layered plating solutions and sophisticated power supplies including reverse pulse biasing, void-free plated structures are achievable.
CMP is also well known in the art. A substrate to be polished is held in a polishing chuck so that typically one third of its edge dimension extends below the chuck. A polishing slurry is provided between the exposed surface and a rotating wheel having a finely textured surface; the substrate may simultaneously rotate and orbit in a planetary motion with respect to the wheel. The desired result is a polished planar surface with clearly defined copper features embedded in the dielectric resin.
Modern computer circuits such as multi-chip modules for computer server applications typically operate at GHz frequencies and with large power supply currents at low operating voltages: 200 amps at 1.0V is a typical requirement. Cooling of the module is a critical issue, and building such circuits on a copper substrate can help address the cooling requirements. In addition, a “copper sandwich” will be described having integral copper plates at both the top and bottom of the assembly for improved ruggedness and better thermal access to the heat-producing chips.
Flip chip assembly is generally recognized as the most advanced assembly method in terms of system density and performance. It enables bare integrated circuit (IC) chips to be assembled, in preference to packaged parts. The chips can have area arrays of input/output (I/O) bonding pads, rather than just at the chip periphery. Inductance of these chip-to-board connections is substantially lower than that of wire bonds, and power pins can be located close to the circuit blocks that need the power. Advanced flip chip assembly methods have recently been reported. One such method is to provide gold stud bumps on the IC chips, and corresponding wells filled with solder on the board. This structure supports pad pitches of 100 microns or less and also routine replacement of defective die using a rework process.
There have been two major impediments to the integration of large systems that are exclusively or primarily assembled using flip chip assembly methods: the inability to effectively test such a system (particularly a functional test at full system speed), and the inability to rework defective chips in the assembly. For these reasons, many flip chip assemblies have been limited to 10 IC chips or fewer, because the cost of scrapping defective assemblies becomes prohibitive with a greater number of chips. Solutions to these problems have been recently proposed. Firstly, a special-purpose test chip or chips may be provided on the board under test; working together with a test support computer this chip can provide the means to functionally test the module at full system speed. The test chip preferably includes high speed sampling circuits and comparators that are under control of the support computer. The support computer performs low speed testing chores such as boundary scan and loading of test files, and also hosts diagnostic software for aiding a test operator in determining which chips need to be replaced, if any. Secondly, the proposed variation of flip chip assembly allows effective rework of defective chips. In summary, the rework method is as follows. The board is placed on a hot plate and the temperature is raised to a level just below the melting point of the solder in the wells (the preferred melting point of the preferred In:Ag solder is 143° C.). Then a rework wand emitting hot inert gas is directed at the backside of the defective chip; the solder in the wells melts for this chip, but not for neighboring chips that are not defective. Focused infra red systems have also been deployed for heating the area local to a single chip without melting the solder of surrounding chips. After the solder of the defective chip is molten, the stud bumps are withdrawn from the wells, the surface is inspected and cleaned as necessary, the wells are touched up with additional solder paste as required, and a replacement part is picked, flipped, aligned, and inserted. After re-flowing the solder for the replacement part and validating the assembly with another module test, the rework cycle is complete. There is preferably no epoxy under layer beneath the defective chip (whose removal would be labor intensive, difficult, and potentially damaging to the board). Also, there are no delicate traces around or near the I/O pads that can be damaged during the rework process; the receiving terminal becomes the solder paste in the well rather than the pad. Finally, the materials used easily tolerate the rework temperatures. These factors result in a rework procedure that may be repeated as many times as necessary, enabling the integration of systems comprising hundreds or thousands of IC chips, assembled onto a single monolithic high performance substrate (or blade). This high level of integration in turn enables supercomputer architectures of the current invention.
The purpose of the epoxy under layer between chip and board is to prevent mechanical failure such as cracking that can arise from stresses accompanying temperature excursions that occur during manufacturing or operation. Part of the justification for eliminating this under layer in the proposed flip chip mounting structure is that the preferred arrangement of gold stud bumps inserted into wells filled with solder is mechanically stronger (shear forces can not easily detach a stud bump from its pad or a well from its pad). Because the stud bumps are formed from gold, and because gold is one of the most ductile materials, and because the proposed stud bumps have a pointed shape, the proposed structure is also more mechanically compliant than previous structures such as solder balls re-flowed onto matching lands. In addition, the low melting point of the proposed indium based solder (143° C.) results in lower thermal strains than would occur with commonly used solders that melt at higher temperatures (63:37 Sn:Pb solder melts at 183° C.). Even with this improved flip chip attachment it may be necessary to limit the maximum chip size in the proposed assembly structures, to limit the stress imposed.
For interconnecting modules, module access cables have been proposed that use a similar arrangement of stud bumps and wells as described for attaching the IC chips. These module access cables can support pin pitches of 100 microns or less, and should be re-workable using the same method as outlined for reworking the IC chips.
The current invention is intended to address the need for microelectronic assemblies that support operating frequencies of the order of 10 GHz (data rates of the order of 10 Gbps), and power supply currents of several hundred amps. An alternative application is to make lower performance electronic assemblies (sub 1 GHz) less expensively than using current printed circuit board and assembly methods.
The preferred embodiment has a base copper layer for mechanical support. A method is described for fabricating feedthroughs in the copper substrate for signals and power. By alternately fabricating layers of dielectric resin and copper conductors, a printed circuit with multiple power and signal planes is built up. Imprinting is used to pattern the layers, preferably using nickel toolfoils. A special assembly layer is preferably fabricated on top of the interconnection circuit wherein a well filled with solder paste is provided at each I/O pad of the board. IC chips are provided with a gold stud bump at each of their I/O pads, and the chips are assembled onto the board by inserting the stud bumps into the wells, then melting the solder to form mechanical and electrical connections. In the preferred embodiment, no epoxy under layer is used between the IC chips and the board. After all the chips are assembled, tested, and reworked as required, a top copper plate may be attached to the backsides of the assembled IC chips, to make a robust mechanical, electrical and thermal package at the module level.
An alternate embodiment supports fabrication of modules such as multi-chip modules (MCMs) or system in package (SIP) devices that are integrated onto a motherboard. The motherboard may be a conventional board employing glass-epoxy laminate for example, or a large interconnection circuit fabricated on a copper substrate using methods described herein. For either case, the copper substrate of the attached module is preferably provided with feeds for power and signals that pass through it and connect to the motherboard, typically on a 1 mm grid.
In the preferred embodiment, imprinting is used to pattern thermo-plastic dielectric layers, and copper conductors are employed. LCP is the preferred dielectric material and DSC is the preferred form of copper for the base layer. After CMP has been used to polish and planarize the surface of a preceding layer, the following sequence summarizes the steps to form the next pair of interleaved dielectric and conducting layers:
A variation of this imprinting procedure will be described for forming the special assembly layer having wells at each of the I/O pads of the interconnection circuit. “Imprinting” and “embossing” are used interchangeably in this application.
These techniques are employed to create copper-faced modules configured as blade servers, plus their integration into liquid-cooled supercomputers of the current invention.
Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
The copper-faced modules described herein can be integrated into servers and supercomputers to provide greater functional density and better cooling than have been available to date.
As previously discussed, a semiconductor manufacturing infrastructure exists for flat panels as large as 2 meters on a side. In principle, large toolfoils could be fabricated for imprinting such a large panel in one step; the photo-imaging of such a large toolfoil area could be accomplished using a stepper exposure system, employing photolithographic exposure systems already in service for LCD manufacture. If this is done, the preferred dielectric material (LCP) can be used and high frequency circuits can be produced in large panels using a single imprint cycle. Alternatively, imprinting of large panels can be achieved using a step and repeat imprinting process like the S-Fil process already described.
For pad pitches as small as 100 microns, as shown in
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8492762||Jun 27, 2006||Jul 23, 2013||General Electric Company||Electrical interface for a sensor array|
|US20080006773 *||Jun 27, 2006||Jan 10, 2008||James Wilson Rose||Electrical interface for a sensor array|
|US20080068815 *||Sep 18, 2006||Mar 20, 2008||Oliver Richard Astley||Interface Assembly And Method for Integrating A Data Acquisition System on a Sensor Array|
|U.S. Classification||257/699, 257/706, 257/698|
|International Classification||H05K3/46, H05K1/05, H05K3/10, H05K3/42, H05K3/44, H01L21/48, H05K3/38, H01L23/04, H05K3/00|
|Cooperative Classification||H05K3/445, H01L21/486, H05K2201/09563, H05K1/056, H05K3/4608, H01L2924/01078, H01L2224/16, H01L2924/10253, H05K3/107, H05K2201/0141, H01L2924/01322, H01L2924/01077, H05K3/423, H05K3/388, H01L2924/01079, H05K3/005, H05K2203/0108, H01L2924/3011, H05K3/465|
|European Classification||H05K3/46A4, H01L21/48C4E|
|Mar 19, 2007||AS||Assignment|
Owner name: PETER C. SALMON, LLC, A CALIFORNIA LIMITED LIABILI
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SALMON, PETER C.;REEL/FRAME:019031/0768
Effective date: 20070313
|Sep 6, 2007||AS||Assignment|
Owner name: SALMON TECHNOLOGIES, LLC, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PETER C. SALMON, LLC;REEL/FRAME:019789/0839
Effective date: 20070905
|Jan 4, 2012||FPAY||Fee payment|
Year of fee payment: 4
|Mar 18, 2016||REMI||Maintenance fee reminder mailed|