SANTA CRUZ, Calif. Promising to reduce overall design time by at least 20 percent, startup Silicon Dimensions Inc. is announcing an updated release of Chip2Nite, an IC design tool that provides floorplanning, placement, analysis and optimization for logic designers.
Chip2Nite, initially released in February, aims to provide logic designers with the physical information they need to design nanometer ICs. It provides an early feasibility analysis of designs and lets designers produce a "seed" floorplan for physical design. The tool is now shipping, but Silicon Dimensions has not released customer information.
Chip2Nite 2.0 adds a new design rule checking (DRC) suite, auto-macro placement and block floorplanning, improved statistics reporting, and a claimed 5-10 fold improvement in database load times. The speed improvement facilitates rapid prototyping and "what if" analysis, and helps reduce design iterations, according to the company.
Chip2Nite includes a data preparation module, a Verilog-to-DEF converter, a block planner, a placer, an analyzer and an optimizer. It generates a production-ready standard cell placement and a datasheet of critical statistics for hand-off to physical design. The tool works with existing EDA tool flows.
Pricing starts at $25,000, and the 2.0 version is available now.