|Publication number||US5021983 A|
|Application number||US 07/434,201|
|Publication date||Jun 4, 1991|
|Filing date||Nov 13, 1989|
|Priority date||Nov 13, 1989|
|Publication number||07434201, 434201, US 5021983 A, US 5021983A, US-A-5021983, US5021983 A, US5021983A|
|Inventors||Au H. Nguyen, Aurav R. Gollabinnie|
|Original Assignee||Chips And Technologies, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Referenced by (116), Classifications (5), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to digital computers. More specifically it is a power saving method and apparatus for battery powered computers.
Reducing power consumption in any electrical device is always a desireable goal. In battery powered computers this goal takes on particular urgency. For example, most battery packs can only power a computer for a few hours of continuous use. Without the incorporation of some form of power consumption reduction mechanism, a computer powered by such a battery pack will not be useable for an entire trans-continental flight.
The simplest solution to this problem is to turn the computer off during any period of non-use. Unfortunately, this solution has a high cost in user convenience. Most computers go through a complete "re-booting" process every time power is turned off and on, the length of which process can be very annoying to the user. Additionally, the user is frequently called upon to restart his application and read from a stored file after the re-booting process is complete, all of which requires additional time. The time required for both re-booting and re-starting the programs can range from 30 seconds to several minutes. Such delays discourage the user from turning the computer off except during periods of extended non-use.
To encourage the user to turn off the computer during any period of non-use, some method or apparatus which can shut the computer down and then resume operation without requiring a re-booting process and which can return the user to exactly the same place and condition as preceded the shutdown would be very desirable.
The present invention is a method and apparatus which reduces power consumption in battery powered computers by eliminating the inconvenience of a re-booting operation every time the computer is turned off, thereby encouraging the user of the computer to turn off the computer during even short periods of non-use. The on/off switch used in the preferred embodiment of the present invention is not a mechanical switch but rather an on/off digital signal generator. The activation of the power switch provides a digital `Off` signal to the present invention. The present invention then stores the present state of the computer in random access memory (`RAM`) off power to all devices except the RAM. When the user reactivates the power switch, providing an `On` signal, the stored present state in the RAM is used to place the computer in exactly the same state it was in prior to the triggering of the `Off` command. Only an abbreviated Power On/Self-Test (`POST`) procedure is conducted when the `On` signal is received and no tests are performed on the memory. The operator is thus able to resume operation of the computer at the same point where operations were being conducted when the machine was turned off with a minimum of delay.
The present invention will now be described in conjunction with the following figures, in which
FIG. 1 is a block diagram of the operating environment of the present invention;
FIG. 2 is a high-level flow chart showing the allocation of control between the present invention and the application program; and
FIGS. 3A and 3B are flow charts showing the operation of the present invention.
Appendix A contains the computer software which realizes the present invention. It is written in the 80286 assembly language; and
Appendix B is a brief description of the LeAPset chipset.
FIG. 1 is a block diagram of the operating environment of the present invention. The figure shows the basic elements of a portable computer. Central processing unit (`CPU`) 15 is coupled to Control Logic 20, which in turn is coupled to RAM 25 and to the various peripheral devices represented by block 30. The peripherals listed in block 30, video adapter 32, Direct Memory Access (`DMA`) 34, and Interrupt Controller 36, are used for illustration purposes only. Although a video adapter will almost always be used with the present invention, the addition or elimination of any group of peripherals will not affect the operation of this invention. For example, as indicated in FIG. 1, either a modem 37 or a FAX machine 39 might be included among the peripherals. Video adapter 32 has a related memory 33 which is generally used to store the information being displayed on the video screen (not illustrated). Also not shown is the digital On/Off switch which provides the actuating signals to the Suspend/Resume mechanisms. CMOS RAM 41 is powered by an independent battery and contains system configuration information.
The present invention can only be implemented in a personal computer wherein control logic 20 is realized by using the LeAPset group of integrated 10 circuits described in Appendix B. Additionally, the computer must be an IBM PC AT compatible model. Finally, Shadow RAM 27 in RAM 25 is needed. Shadow RAM 27 occupies the space in RAM 25 from 640K bytes to 1024K bytes. This area in RAM 25 is normally unused in IBM PC AT compatible machines.
FIG. 2 shows the high level operation of the present invention. Hypothetical application program 50 is running on a battery powered computer (not shown in FIG. 2). At point 53 during the use of the application program the On/Off switch is triggered. Machine operation then transfers from application program 50 to Basic Input/Output Software (`BIOS`) 55 which controls the computer's input/output operations. BIOS is a software interface or "layer" that isolates operating systems and application programs from specific hardware devices. In other words, BIOS 55 is the hardware dependent part of the computer's operating system. BIOS 55 knows the specific peripherals which have been coupled to the computer and controls their operation. Although the present invention resides within BIOS, a detailed understanding of the BIOS is not necessary for understanding this invention. All necessary background information on BIOS can be obtained from the "IBM Personal System/2 and Personal Computer BIOS Interface Technical Reference," 2nd Edition, May 1988, which is incorporated herein by reference.
Upon receipt of `Off` signal 53, the Suspend mechanism 100 stores the machine's current state in shadow RAM 27. To those skilled in the art, the term `state` in reference to computer operation means the present contents of all the registers in all the components used by the computer. In the present invention, `state` refers to the contents of the CPU's 10 registers, the DMA registers, the video adapter registers, the Interrupt Controllers registers, and the registers in other supported peripherals. Once the machine's current state is stored in shadow RAM 27, power is cut off to all components except RAM 25. When the power switch is reactivated and `On` signal 57 generated, which indicates that computer operations should be resumed, Resume mechanism 200 restores the contents of shadow RAM 27 to the various component registers and, at step 59, returns program control to application program 50 at the same point where BIOS 55 was originally called.
FIGS. 3A and 3B are detailed flow charts showing the operation of Suspend mechanism 100 and Resume mechanism 200. The software contained in Appendix A realizes both mechanisms and all references to Appendix A will be given as line numbers. References to FIGS. 3A and 3B will use step numbers.
Suspend mechanism 100 cannot be activated without three prerequisites. First, the feature must be enabled. During the original booting up operation the user is given a choice of how to configure the computer. If the user enables the Suspend/Resume mechanisms, one bit in CMOS battery powered back-up RAM 41 is set to indicate that the feature has been selected. This check occurs at step 101 (line 35). Second, the computer must have shadow RAM which test is made at step 103 (lines 37-41) and third, the shadow RAM must be in a specific place (in other words, not relocated) which check occurs at step 105 (lines 37-41). If any of these conditions are not met, a call to Suspend results in either a complete machine `power off` in the case where the function is called from the power switch, or the Suspend request is ignored if the function was called from an application program or keyboard interrupt and control returns to the application program. This is shown at step 106 (lines 48-56).
If Suspend is enabled and shadow RAM is present and unmoved, operation continues at step 107 by pushing all the registers of the CPU onto the applications stack which stack exists in RAM 25 (lines 62-85). Two CPUs are supported--the 80386SX and 80286. The only difference between the operation of the present invention with either of these two CPUs is the number of registers to be saved.
As most registers cannot be saved on the application's stack, shadow RAM 27 must be enabled at step 108 (lines 90-91). Shadow RAM 27 must be separately enabled as it cannot ordinarily be written to or read from.
At step 109 CPU registers SS, SP, and MSW are saved separately in shadow RAM 27 (lines 98-103). Although this is a slight redundancy, as register SP was pushed on the application stack at step 107, these registers must be stored in a location outside the stack so that the stack itself can be found using the information contained in these registers when Resume 200 begins operation.
To prevent any corruption of the data in memory due to interference from other software during the Suspend mechanism's operation, the Non Maskable Interrupt (`NMI`) vector is disabled at step 111 (lines 108-127). This results in disabling any other software operating concurrently.
After the CPU registers have been pushed on the stack, the DMA Page registers are stored in shadow RAM 27 at step 113 (lines 140-147). The DMA Page registers in combination with the DMA registers provide complete address information for direct memory access.
At this point, Suspend-In-Progress flags are set in an unused DMA page register at step 115 (lines 158-161). This flag prevents the computer from going to a complete power shut down during the time the Suspend mechanism is performing its tasks. If the flag was not set, power shut down would occur within seconds after the power On/Off switch was triggered, which might be insufficient time for Suspend to complete its operations.
The interrupt controller registers are stored in shadow RAM 27 at step 117 (lines 170-174). Then Control Logic 20's LeAPset chipset registers are stored
RAM 27 at step 119 (lines 178-188). At step 121 the numeric coprocessor register is stored in shadow RAM 27 (line 197). The DMA registers are then stored in shadow RAM 27 at step 123 (lines 208-243). The VGA registers are saved at step 125 (lines 247-250). With regards to the video RAM, the first 256K therein is stored at step 127 (lines 254-265). The registers controlling memory sizing in the LeAPset chipset are then saved in CMOS RAM 41 at step 129 so that memory can be configured upon Resume without access to DRAM (lines 270-286). If additional peripherals such as a modem or FAX have been coupled to the computer, the registers related thereto are stored at step 131 (lines 291-292). Finally, a small area of RAM is reserved at step 133 for Power On Self-Test (`POST`) after Resume 200 is activated (lines 297-303).
In order to insure that memory is unaffected by the Suspend feature, all the bytes of memory are added together and stored. This occurs at step 135 (lines 307-308) Upon Resume, the same process again adds up all the bytes in memory and compares the sums. If they do not agree, the Resume function fails and re-booting can occur.
After the memory bytes are added, the `Suspend` bit in CMOS RAM 41 is turned on at step 137 (lines 313-317). This tells the machine that the computer is suspended. Next, the Suspend-In-Progress bit is cleared at step 139 (lines 322-323). At step 141, all machine operation is halted and power is cut to all chips and components except the RAM memory (lines 327-331).
The Resume mechanism 200 is essentially Suspend mechanism 100 operated in reverse. First, once the power switch is triggered to provide an "On" signal, an abbreviated POST is performed. Ordinarily in the absence of the Suspend/Resume mechanism, a full POST is performed every time the computer is turned on. Here, when Suspend/Resume are activated, the abbreviated POST tests all components except the memory. The test is necessary as the power surge accompanying Power On can damage components. If the POST is conducted successfully, then the Resume mechanism begins operation.
At step 201 (FIG. 3B) interrupts are disabled while the Resume mechanism operates (line 343). Next, the resume stack is set up in shadow RAM 27 at step 203 (lines 347-350).
Memory checking commences at step 205, where the shadow RAM is enabled for the Checksum operation (line 356). The Checksum addition of memory occurs at step 207 (lines 360-362). At step 209, a comparison is made between the Checksum values stored by Suspend 100 and those obtained by Resume 200 (lines 363-369). If the sums do not agree, the user can either continue Resume, accepting the risk of possible false values stored in memory or do a complete re-boot. The choice is given at step 211 (lines 373-395). Re-booting operations occur at step 213 (lines 387-389).
Resume operations continue at step 215 if either the Checksums agreed or the user chose to continue Resume. Here, the registers of the optional peripherals such MODEMs or FAXes are recalled and restored, if necessary (lines 400-404). The stored 256K of video RAM is restored at step 217 (lines 408-420). At step 219 the interrupt vector table is restored from shadow RAM and placed in segment 0000 (lines 425-436).
Video adapter registers are restored at step 221 (lines 440-445), the numeric coprocessor registers are restored at step 223 (lines 449-450), and the DMA registers and DMA Page registers are restored at steps 225 and 227, respectively (lines 454-521 and lines 525-532, respectively). Finally, the interrupt controller registers are restored at step 229 (lines 536-539).
If necessary, BIOS is copied to shadow RAM at step 231 (lines 543-577). Control logic 20's LeAPset registers are restored from shadow RAM at step 233 (lines 581-592). The last registers recalled from shadow RAM, the SS, SP and MSW registers are restored at step 235 (lines 597-618).
At step 237 any shadow RAM no longer being used is disabled (lines 623-625). The CPU is restored to its pre-Suspend state by popping its registers off the stack at step 239 (lines 629-652). At this point, the return address on the stack is used to return control to the application program at the point where control was transferred to Suspend. This completes the description of the Suspend/Resume mechanisms.
The invention has now been described in relation to a particular embodiment thereof. Although limited at present to battery powered IBM PC AT compatibles wherein the LeAPset chipset is used, the general concept of a Suspend/Restore mechanism would be useful in any computer, even if powered by a conventional A.C. power source. Changes and adaptions to the software of Appendix A would be necessary to enable the invention to operate in these different environments, but the reduction of user waiting time achieved by eliminating the re-booting process would be a significant convenience. As these changes in form and details would be understood by those skilled in the art, they do not depart from the spirit of the invention. It is therefore intended that an exclusive right be granted to the invention as limited only by the metes and bounds of the appended claims. ##SPC1##
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|U.S. Classification||713/321, 714/24|
|Nov 13, 1989||AS||Assignment|
Owner name: CHIPS AND TECHNOLOGIES, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:NGUYEN, AU H.;GOLLABINNIE, AURAV R.;REEL/FRAME:005176/0402
Effective date: 19891110
|Sep 3, 1991||RR||Request for reexamination filed|
Effective date: 19910731
|Jul 11, 1994||FPAY||Fee payment|
Year of fee payment: 4
|May 28, 1996||B1||Reexamination certificate first reexamination|
|Dec 3, 1998||FPAY||Fee payment|
Year of fee payment: 8
|Dec 4, 2000||AS||Assignment|
Owner name: CHIPS AND TECHNOLOGIES, LLC, CALIFORNIA
Free format text: MERGER;ASSIGNOR:CHIPS AND TECHNOLOGIES, INC.;REEL/FRAME:011333/0503
Effective date: 19981030
|Jan 23, 2001||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHIPS AND TECHNOLOGIES, LLC;REEL/FRAME:011449/0081
Effective date: 20010103
|Sep 30, 2002||FPAY||Fee payment|
Year of fee payment: 12