|Publication number||US6078189 A|
|Application number||US 09/162,006|
|Publication date||Jun 20, 2000|
|Filing date||Sep 28, 1998|
|Priority date||Dec 13, 1996|
|Publication number||09162006, 162006, US 6078189 A, US 6078189A, US-A-6078189, US6078189 A, US6078189A|
|Inventors||Leo A. Noel|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Non-Patent Citations (2), Referenced by (41), Classifications (11), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation-in-part of patent application Ser. No. 8/768,000, filed Dec. 13, 1996 abandoned.
This invention generally relates to a method of testing electronic devices. More particularly, it relates to varying a test program dynamically in response to the results of testing. Even more particularly, it relates to dynamically reordering the sequence of tests in a test program in response to test data.
Electronic devices, such as semiconductor chips, are usually tested with a battery of tests before they are shipped to customers. The tests check for the presence of known types of defects that may arise during manufacturing of the electronic device. The tests are usually generated by test engineers but many of them can also be generated automatically according to the design data for a particular electronic device. The tests are performed by an automatic tester that runs a test program. The tester has probes for contacting each electronic device in turn and the test program is run for each device.
A test program may include a series of parametric tests to detect shorts and opens, measure power supply current, and verify that drivers will drive a sufficient current at a specified voltage. The test program may also include a series of functional tests to ensure that the various circuits on the chip are operating as designed. The functional tests can be conducted through test patterns that are supplied by the tester or by one or more built in self-test structures fabricated on the chip itself The test program may also include performance tests to sort passing devices according to their speed. The program may also include tests of the power supply current drawn by the chip after test patterns have been applied to the chip.
In production, the test program is run to completion only on devices that pass all tests. To save test time and money, the test program is usually stopped immediately after the first failing test on a particular device, and that failing device is marked or sorted as a fail.
As experience with test fails and defects on electronic devices becomes available, the test program may be updated, adding or deleting tests or reordering tests in the program to optimize test efficiency. After the updated test program has been generated, it must then be compiled and loaded into the tester. The program must then be qualified for use on subsequent production electronic devices. That is, the test program itself must undergo an evaluation to ensure that it is properly functioning. The updating and reordering steps introduce the possibility of error into the program that could, for example, eliminate important tests and allow failing devices to pass. In addition, these steps of reviewing and analysing test data from failing devices, then using the analysis to update a test program, and then qualifying the new test program for use in production, have been time consuming and costly.
A better solution is needed that provides for rapid and low cost updating of test programs that reduces the risk of error. This solution is provided by the following invention.
It is therefore an object of the present invention to provide a process for dynamically updating a test program to make testing more efficient, lower cost, and less subject to error.
It is a feature of the present invention that tests of a test program are reordered during the testing of a group of electronic devices.
It is a feature of the present invention that human involvement in reviewing or analysing test data and reordering the tests is eliminated.
It is a feature of the present invention that the test program need not be recompiled, reloaded into the tester, or requalified after the order of tests in the test program is changed.
It is a feature of the present invention that a series of tests having a common power supply voltage condition can be reordered independent of the order of tests for a different power supply voltage condition.
It is an advantage of the present invention that a significantly increased efficiency of testing and a reduction in the cost of testing is achieved.
These and other objects, features, and advantages of the invention are accomplished by a method of testing a plurality of electronic devices comprising the steps of (a) providing a plurality of electronic devices to a tester for testing; (b) testing a first electronic device of the plurality of devices with a plurality of tests; (c) obtaining a result of the testing step (b); (d) dynamically modifying the plurality of tests based on the result in step (c); and (e) testing a second electronic device of the plurality of devices with the modified tests.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following detailed description of the invention, as illustrated in the accompanying drawings, in which:
FIG. 1 is a flow chart showing the steps in the process of reordering the test labels of a test program to automatically change the sequence of the tests.
The present invention provides a process for dynamically modifying a test program based on the results of testing. In one embodiment, the sequence of tests in a test program is reordered in response to test results during the testing of a group of electronic devices to significantly improve test efficiency. The reordering of tests is accomplished by reordering labels for each of the tests in a sequence of storage locations that is used by the tester to select tests to be run.
The flow chart in FIG. 1, illustrates steps in the process of the present invention. In step 101, a test program having a plurality of tests is provided to an electronic device, such as one of the chips on a wafer. Each test of the test program has a unique label, and the labels are in a given sequence or order in the test program when the program is presented to the first chip to be tested. In step 102, the labels are stored in sequential storage locations in the tester before testing begins. Slightly more efficiently, the labels can be stored in the storage locations during the running of the test program to test the first chip. In step 103 chips of the wafer are tested with the given test program either until the last chip of the group of wafers is tested with the test program or until a chip is tested that fails. In step 104, if the last chip is tested the testing ends as shown in step 105. Otherwise testing continues with the given test program until a chip is tested that fails.
In step 106, the label of the test that caused the failing chip to fail is stored in a fail test storage register (FTSR) in the tester. In step 107 all labels in the sequential storage locations before the failing test label are shifted down one position. In step 108, the label for the failing test that is in the fail test storage register is loaded into the first storage location of the sequence.
If the chip that failed is not the last chip to be tested (step 108) then more chips are tested using steps 103 to 108. The next device is then tested according to step 103.
TABLE 1______________________________________Using Test Results to Reorder the Sequence of Tests______________________________________(a) Device tested: #1Data in Sequential Storage LocationsStorage Data inLocation storage location1 label 12 label 23 label 34 label 45 label 56 label 6. .. .. .200 label 200Result of test: Fail test of label 4Data to be loaded in FTSR: Label 4(b) Device tested: #2Storage Data inLocation storage location1 label 42 label 13 label 24 label 35 label 56 label 6. .. .. .200 label 200Result of test: Fail test of label 5Data to be loaded in FTSR: Label 5(c) Device tested: #3Storage Data inLocation storage location1 label 52 label 43 label 14 label 25 label 36 label 6. .. .. .200 label 200Result of test: none failData to be loaded in FTSR: Label 5(d) Device tested: #4Storage Data inLocation storage location1 label 52 label 43 label 14 label 25 label 36 label 6. .. .. .200 label 200Result of test: Fail test of label 200Data to be loaded in FTSR: Label 200(e) Device tested: #5Storage Data inLocation storage location1 label 2002 label 53 label 44 label 15 label 26 label 3. .. .. .200 label 199Result of test: Fail test of label 1Data to be loaded in FTSR: Label 1(f) Device tested: #6Storage Data inLocation storage location1 label 12 label 2003 label 54 label 45 label 26 label 3. .. .. .200 label 199Result of test: Fail test of label 2Data to be loaded in FTSR: Label 2______________________________________
A further illustration of the dynamic reordering of tests in a test program provided on a tester is given in Table 1(a-f). As shown in part (a) of Table 1, labels for the initial sequence of tests provided in the original test program are first stored in sequential storage locations in the tester. Thus label 1 for the first test in the original sequence of tests in the test program is stored in storage location 1, label 2 for the second test is stored in storage location 2, and so on up to label 200 for the last test stored in storage location 200. Device #1 is tested in order of that original sequence of labels, and it fails the test for label 4. Label 4 is then stored in the fail test storage register (FTSR).
Before Device #2 is tested a new sequence of tests is generated according to steps 107 and 108 of FIG. 1 which have the result of placing failing label 4 in the first storage location of the sequential storage locations in the tester while shifting labels 1, 2, and 3 to the next three storage locations, that is, to storage locations 2, 3, and 4 as shown in part (b) of Table 1. All labels in storage locations beneath the original position of failing test 4 remain in their original storage locations. As described in the process shown in FIG. 1, the shifting of label 3 to storage location 4, of label 2 to storage location 3, and of label 1 to storage location 2 occurs first to provide space at the beginning of the sequence in storage location 1 for the insertion of label 4 from the fail test storage register.
Device #2 is now tested using this revised sequence of tests. In the example shown in part (b) of Table 1, device #2 passes the tests of labels 4, 1, 2, and 3. It then fails the test of label 5. Label 5 is then stored in the FTSR. As shown in part (c) of Table 1, all labels in storage locations above failing test 5 are shifted down one storage location and failing test label 5 is moved from the FTSR into storage location 1.
Device #3 is now tested using this revised sequence of tests. In the example shown in part (c) of Table 1, device #3 passes the tests of all the labels, including labels 5, 4, 1, 2, . . . 200. It fails none of the tests. Label 5 remains stored in the FTSR. As shown in part (d) of Table 1, since label 5, for failing test 5, is already the first label in the sequence and since there are no labels in storage locations above failing test 5, no labels are shifted down one storage location. Failing test label 5 remains in storage location 1. There is no change in the sequence of tests.
Device #4 is now tested using this sequence of tests. In the example shown in part (d) of Table 1, device #4 passes the tests of labels 5, 4, 1, 2, 3, 6, . . . 199. It then fails the test of label 200. Label 200 is then stored in the FTSR. As shown in part (e) of Table 1, all labels in storage locations above failing test 200 are shifted down one storage location and failing test label 200 is moved from the FTSR into storage location 1.
Device #5 is now tested using this revised sequence of tests. In the example shown in part (e) of Table 1, device #5 passes the tests of labels 1, 200, 5, and 4. It then fails the test of label 1. Label 1 is then stored in the FTSR. As shown in part (f) of Table 1, all labels in storage locations above failing test 1 are shifted down one storage location and failing test label 1 is moved from the FTSR into storage location 1.
The savings in test time is dramatically illustrated by the example in part (e) of Table 1 where the test of label 200 is conducted first. Thus, we have a test that originally was at the end of the test program being run at the beginning of the program in response to the fact that a device failed that test. In subsequent tests the test of label 200 will remain near the beginning of the test program, reflecting the fact that the test of label 200 had a fail.
Device #6 is now tested using this revised sequence of tests. In the example shown in part (f) of Table 1, device #6 passes the tests of labels 200, 5, and 4. It then fails the test of label 2. Label 2 is then stored in the FTSR. Not shown is the shifting of all labels in storage locations above failing test 1 down one storage location while failing test label 2 is moved from the FTSR into storage location 1.
While reordering to put the failing test first in the sequence is preferred, other reordering schemes are possible, such as dynamically reordering so that the tests are in order of the probability of failing. The accumulated test data is used to calculate these probabilities and the labels are dynamically arranged in the sequential storage locations in order of this probability. This data can be processed using computational facilities in the tester or on an auxiliary computer directly linked to the tester that reads the test data and provides statistical information back to the tester. Other information, such as the time it takes to perform each test can also be factored into the ordering scheme. Thus, the labels can be arranged and a device tested with tests ordered according to the probability of causing a fail as weighted by the time for each test to optimize test efficiency.
In addition to reordering based on individual failing test data, it is also possible to reorder including the results of several tests that combine to provide a fail. All the tests involved in the failing condition would then be moved earlier in the test sequence. The process for reordering is accomplished for each failing test sequentially or two or more failing test storage registers could be used to reorder all the tests in one step.
Electronic devices are frequently tested at one voltage condition and then retested at a different voltage condition. In the invention a series of tests performed at the first voltage condition can be reordered independently of the order of tests for the second voltage condition. Thus, the same sequence of tests can be performed at each voltage condition and in a different order based on the test data to improve test efficiency.
The present invention is applicable to a wide range of modifications of a test program in addition to reordering the tests. For example, tests can be deleted from active use or added to active use by adding a label to or deleting a label from the sequential storage locations. The deletion or addition of a label may be based on pass rate statistics accumulated in the tester.
Also, the electronic devices can include a built in self-test (BIST) circuit. A sequence of seed patterns is provided by the tester to provide a sequence of tests run by the BIST circuit. The results of each test is compared with a signature pattern provided by the tester to determine whether the chip has passed each test. The present invention can be used to reorder the sequence of seed patterns and signature patterns so that a seed that causes a fail is provided earlier in the sequence.
The present invention is particularly suitable for scan design testing. Scan design testing is described in a paper, "A Logic Design Structure for LSI Testing," by E. Eichelberger and T. W. Williams, in the Proceedings of the 14th Design Automation Conference, June 1977, p. 462-468. Scan design testing initializes logic on a chip when data is serially loaded into scan chain latches. In the next step, the initialization is accomplished when a clock pulse simultaneously loads data from the latches into the chip logic. This data propagates through the chip logic. Another clock pulse loads logic data that has reached a scan chain latch into that scan chain latch. Data from all the scan latches is serially unloaded and compared to expected data to determine whether the logic is good or bad. This set of steps, scanning-in to scan latches, initializing and propagating through logic, loading of scan latches from the logic, and scanning-out consititute a single functional test using scan design testing. Because the chip is initialized with each scan-in operation, these functional tests can be applied in any order. The present inventor recognized that the scan-in step constitutes an initialization that permits reordering.
By contrast, standard vector testing does not involve an initialization step with every functional test. The state of the chip at the beginning of a functional test is determined by the state of the chip at the end of the last functional test. The validity of the subsequent functional test depends on the the logic being in a state determined by the previous functional test. Thus, reordering of tests would render the tests meaningless. At the least, an initialization step to provide the chip in the proper state would be needed to allow reordering of the functional tests, and the time for this initialization would defeat the value of reordering.
While several embodiments of the invention, together with modifications thereof, have been described in detail herein and illustrated in the accompanying drawings, it will be evident that various further modifications are possible without departing from the scope of the invention. Nothing in the above specification is intended to limit the invention more narrowly than the appended claims. The examples given are intended only to be illustrative rather than exclusive.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3781683 *||Mar 30, 1971||Dec 25, 1973||Ibm||Test circuit configuration for integrated semiconductor circuits and a test system containing said configuration|
|US4728883 *||Mar 15, 1985||Mar 1, 1988||Tektronix, Inc.||Method of testing electronic circuits|
|US4875002 *||Nov 24, 1987||Oct 17, 1989||Sharp Kabushiki Kaisha||Method of testing semiconductor wafers|
|US4994732 *||Oct 5, 1989||Feb 19, 1991||Schlumberger Technologies, Inc.||Automatic test system having a "true tester-per-pin" architecture|
|US5004978 *||Mar 29, 1990||Apr 2, 1991||Hewlett-Packard Company||Method for regenerating in-circuit test sequences for circuit board components|
|US5023557 *||Sep 5, 1990||Jun 11, 1991||At&T Bell Laboratories||Testing process for electronic devices|
|US5654632 *||Jul 30, 1996||Aug 5, 1997||Fujitsu Limited||Method for inspecting semiconductor devices on a wafer|
|1||"A Logic Design Strcuture for LSI Testing" E. Eichelberger & T. W. Williams, 14th Design Automation Conference, Jun. 1977, p. 462-468.|
|2||*||A Logic Design Strcuture for LSI Testing E. Eichelberger & T. W. Williams, 14th Design Automation Conference, Jun. 1977, p. 462 468.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6618682 *||Apr 20, 2001||Sep 9, 2003||International Business Machines Corporation||Method for test optimization using historical and actual fabrication test data|
|US6815961||Mar 8, 2002||Nov 9, 2004||Nanonexus, Inc.||Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies|
|US6857090 *||Oct 9, 2001||Feb 15, 2005||Samsung Electronics Co., Ltd.||System and method for automatically analyzing and managing loss factors in test process of semiconductor integrated circuit devices|
|US6883113||Apr 18, 2002||Apr 19, 2005||Bae Systems Information And Electronic Systems Integration, Inc.||System and method for temporally isolating environmentally sensitive integrated circuit faults|
|US7050922 *||Jan 14, 2005||May 23, 2006||Agilent Technologies, Inc.||Method for optimizing test order, and machine-readable media storing sequences of instructions to perform same|
|US7260744||Mar 31, 2004||Aug 21, 2007||Sap Aktiengesellschaft||Computer system diagnosis with user-developed procedure|
|US7260750 *||Mar 31, 2004||Aug 21, 2007||Sap Aktiengesellschaft||Computer system diagnostic procedures performed in specified order|
|US7263634||Mar 31, 2004||Aug 28, 2007||Sap Aktiengesellschaft||Failures of computer system diagnostic procedures addressed in specified order|
|US7359820||Jan 3, 2007||Apr 15, 2008||International Business Machines Corporation||In-cycle system test adaptation|
|US7359822 *||Aug 3, 2005||Apr 15, 2008||Advantest Corporation||Testing device|
|US7573284 *||Jul 9, 2008||Aug 11, 2009||International Business Machines Corporation||Increase productivity at wafer test using probe retest data analysis|
|US7884634||Feb 8, 2011||Verigy (Singapore) Pte, Ltd||High density interconnect system having rapid fabrication cycle|
|US7952373||Oct 23, 2006||May 31, 2011||Verigy (Singapore) Pte. Ltd.||Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies|
|US8381184||Feb 19, 2013||International Business Machines Corporation||Dynamic test coverage|
|US9310437 *||Mar 25, 2011||Apr 12, 2016||Taiwan Semiconductor Manufacturing Company, Ltd.||Adaptive test sequence for testing integrated circuits|
|US9342424 *||Aug 21, 2013||May 17, 2016||International Business Machines Corporation||Optimal test flow scheduling within automated test equipment for minimized mean time to detect failure|
|US20020155628 *||Apr 20, 2001||Oct 24, 2002||International Business Machines Corporation||Method for test optimization using historical and actual fabrication test data|
|US20030005376 *||Oct 9, 2001||Jan 2, 2003||Lee Kyu Sung||System and method for automatically analyzing and managing loss factors in test process of semiconductor integrated circuit devices|
|US20030200484 *||Apr 18, 2002||Oct 23, 2003||Bae Systems Information And Electronic Systems Integration, Inc.||System and method for temporally isolating environmentally sensitive integrated circuit faults|
|US20040022042 *||Mar 8, 2002||Feb 5, 2004||Sammy Mok||Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies|
|US20040075455 *||Nov 19, 2003||Apr 22, 2004||Sammy Mok||Mosaic decal probe|
|US20050051353 *||Aug 12, 2004||Mar 10, 2005||Chong Fu Chiung||Massively parallel interface for electronic circuit|
|US20050068054 *||Jul 9, 2004||Mar 31, 2005||Sammy Mok||Standardized layout patterns and routing structures for integrated circuit wafer probe card assemblies|
|US20050091003 *||Mar 31, 2004||Apr 28, 2005||Yuh-Cherng Wu||Computer system diagnostic procedures performed in specified order|
|US20050097397 *||Mar 31, 2004||May 5, 2005||Yuh-Cherng Wu||Computer system diagnosis with user-developed procedure|
|US20050097400 *||Mar 31, 2004||May 5, 2005||Yuh-Cherng Wu||Failures of computer system diagnostic procedures addressed in specified order|
|US20050102569 *||Mar 31, 2004||May 12, 2005||Yuh-Cherng Wu||Performing diagnosis in a computer system|
|US20050278599 *||Aug 3, 2005||Dec 15, 2005||Advantest Corporation||Testing device|
|US20070260937 *||Apr 13, 2006||Nov 8, 2007||Carli Connally||Systems and methods for selectively logging test data|
|US20080162995 *||Oct 28, 2007||Jul 3, 2008||International Business Machines Corp.||In-cycle system test adaptation|
|US20080270057 *||Jul 9, 2008||Oct 30, 2008||International Business Machines Corporation||Increase productivity at wafer test using probe retest data analysis|
|US20100058295 *||Sep 2, 2008||Mar 4, 2010||International Business Machines Corporation||Dynamic Test Coverage|
|US20120246514 *||Sep 27, 2012||Taiwan Semiconductor Manufacturing Company, Ltd.||Adaptive Test Sequence for Testing Integrated Circuits|
|US20130054218 *||Aug 24, 2011||Feb 28, 2013||Ameen Ashraf||Method and Software Tool for Automatically Testing a Circuit Design|
|US20150058668 *||Aug 21, 2013||Feb 26, 2015||International Business Machines Corporation||Optimal test flow scheduling within automated test equipment for minimized mean time to detect failure|
|CN102692569A *||Oct 18, 2011||Sep 26, 2012||台湾积体电路制造股份有限公司||Adaptive test sequence for testing integrated circuits|
|CN102692569B *||Oct 18, 2011||Sep 16, 2015||台湾积体电路制造股份有限公司||测试集成电路的自适应测试序列|
|CN102707225A *||Jun 21, 2012||Oct 3, 2012||上海华岭集成电路技术股份有限公司||Integrated circuit testing optimizing method and testing device thereof|
|EP1403651A2 *||Sep 24, 2003||Mar 31, 2004||Agilent Technologies, Inc.||Testing integrated circuits|
|WO2005043392A1 *||Sep 27, 2004||May 12, 2005||Sap Aktiengesellschaft||Computer system diagnostic procedures performed in specified order|
|WO2005043393A1 *||Oct 6, 2004||May 12, 2005||Sap Aktiengesellschaft||Failures of computer system diagnostic procedures addressed in specified order|
|U.S. Classification||324/750.01, 73/865.9, 73/865.5, 324/754.03, 324/762.05, 324/750.3|
|International Classification||G01R31/28, G06F17/40|
|European Classification||G06F17/40, G01R31/28F3|
|Sep 28, 1998||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NOEL, LEO A.;REEL/FRAME:009487/0488
Effective date: 19980928
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