[Beowulf] Teraflop chip hints at the future
James.P.Lux at jpl.nasa.gov
Tue Feb 13 12:25:38 EST 2007
At 09:46 PM 2/12/2007, Mark Hahn wrote:
>>Intel is stacking dram dice above the cpu as an L4 cache, but the article
>stacking seems like a major hack - I'd rather think about how to do
>processor-in-memory (perhaps zram?).
It's a technology thing.. you can't get DRAM densities with processes
used for CPUs and the like. Different fabs, different processes, even
though the feature sizes are similar. There's also some thermal
issues. If you use a CPU process to build ram, it's not very dense
(think cache on current chips... which I think tends to be static ram
at 3 transistors per cell). I don't know that you can even build a
big CPU on a DRAM process. DRAMs are pretty highly optimized (read,
they've spent billions of dollars on tweaking the device models to
within a gnats eyelash of the physics limits).. for instance, because
with DRAM you only read or write one location at time, very few
transistors change state on any given cycle, so the power dissipation
is low. Compare with a CPU where you have thousands of transistors
changing state on a cycle.
I'm not a chip designer, so there's probably a lot of subtleties...
>>explain how they plan to expand the off-chip bw other than by going
>isn't photonics still at the hand-waving stage? I was just noticing how 10G
>XFP's have not gotten much cheaper over the past couple years. is there
>really a prospect for wide and fast photonic links, given that copper links
>are at ~3 Gb pretty easily? have people figured out how to
>mass-produce photonic-chipped systems as efficient as copper PC
>boards and bumped chips?
Not really... there IS some progress on VCSELs and detectors, but the
conventional transmit data with electrons instead of photons folks
are also making progress. 1 Tb/sec isn't unusual.
As always, dealing with propagation uncertainties (electromagnetic,
either way) is challenging. At 1 Tb/sec, a bit is only 30 microns
long in free space.
Go to the IEEE High Speed Digital Interconnect Workshop in Santa Fe
this year... there's amazing stuff that people are doing.
James Lux, P.E.
Spacecraft Radio Frequency Subsystems Group
Flight Communications Systems Section
Jet Propulsion Laboratory, Mail Stop 161-213
4800 Oak Grove Drive
Pasadena CA 91109
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