|Publication number||US6869809 B2|
|Application number||US 10/447,520|
|Publication date||Mar 22, 2005|
|Filing date||May 28, 2003|
|Priority date||Feb 19, 2003|
|Also published as||US7064445, US20040161865, US20040173794|
|Publication number||10447520, 447520, US 6869809 B2, US 6869809B2, US-B2-6869809, US6869809 B2, US6869809B2|
|Inventors||Yu-Lung Yu, Joseph Nee|
|Original Assignee||Via Technologies, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (12), Referenced by (12), Classifications (10), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims the priority benefit of Taiwan application serial no. 92103361, filed Feb. 19, 2003.
1. Field of Invention
The present invention relates to a testing and packaging process. More particularly, the present invention relates to a wafer level testing and bumping process.
2. Description of Related Art
Following the rapid development of semiconductor fabrication techniques, advanced and precise semiconductor devices are now being produced to meet the increased demand in many electronic products. In general, for the fabrication of semiconductors and the subsequent package/test, a front stage fabrication process is carried out after the design of the integrated circuit (IC). The front stage fabrication process includes fabricating integrated circuits on a wafer followed by testing the circuits. After sawing the wafer into individual chips, a wire bonding or a flip-chip bonding process is usually carried out to connect bonding pads on the active surface of the chip with contact pads on a carrier. The carrier is a substrate or a lead frame, for example. Using a flip-chip package as an example, a plurality of bonding pads is formed on the active surface of the chip prior to attaching a bump to each bonding pad. Hence, the bonding pads on the active surface of the chip are electrically and mechanically connected to contact pads on the substrate through the bumps. In other words, electrical signals can be transmitted from the chip to an external electronic device and vice versa through the carrier.
To test the integrated circuits within the wafer 100, the flip-chip bonding pads 108 or the bumps 120 on the active surface 102 are used as testing points after the metallic interconnects 106 inside the wafer 100 are formed as shown in FIG. 1B. Note that a vertical probe card 10 with an array of probe pins 12 that correspond in positions with the top ends of the bumps 120 is used to test the wafer 100 so that any problems within the wafer 100 can be found through a circuit analysis.
After performing a detailed analysis of the internal circuits inside the wafer 100, the malfunctioning portion of the integrated circuit can be repaired by cutting a corresponding fuse line 112 using a laser beam and replacing the defective circuit with a backup circuit as shown in FIG. 1C. Thus, a conventional wafer 100 is usually designed with a few backup circuits and fuse lines 112. The fuse windows 114 is a special design for decreasing the thickness of the section on top of the fuse line 112 so that the cutting of the fuse lines 112 and the replacement of the defective circuit with a backup circuit is facilitated. Note that thickness of the structure on top of the fuse line 112 must be reduced to facilitate the passage of a laser beam to the fuse line 112 and repair the defective circuit. Thus, a portion of the passivation layer 110 can be removed prior to repairing the defective circuit so that the fuse window 114 is exposed and thickness of the structure above the fuse line 112 is reduced. Thereafter, a laser beam is aimed to cut out the fuse line 112 and then another passivation layer 110 a is formed to cover the aforementioned fuse window 114. However, in the process of repairing the defective circuit, holes for exposing the fuse windows 114 must be opened up in the passivation layer 110 a anew so that thickness of the local structure above the fuse line 112 is again reduced. Hence, the process cycle for testing and packaging the wafer 100 is longer.
Furthermore, as shown in
Accordingly, one object of the present invention is to provide a wafer level testing and bumping process having fewer steps, a shorter processing cycle and a lower production cost.
A second object of this invention is to provide a wafer structure having a plurality of test pads thereon. By bringing the tips of probe pins into contact with the test pads on the active surface of a wafer, integrated circuits within the wafer can be tested electrically. Since the probe pins press against the test pads instead of the bonding pads on the wafer, damages to internal circuits due to pressure applied to the probe pins are greatly minimized.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a wafer level testing and bumping process. The wafer comprises at least a fuse line buried within the wafer. The wafer also has an active surface. The wafer level testing and bumping process includes at least the following steps: (a) forming at least a flip-chip bonding pad as well as a test pad on the active surface such that the test pad is located at the periphery of the active surface but is electrically connected to the flip-chip bonding pad; (b) forming at least a fuse window on the active surface such that the fuse window is at a level below the active surface for decreasing the thickness of the section between the fuse line and the active surface; (c) performing an electrical testing of the wafer through the test pad to produce some test results; (d) according to the test results, determining whether to cut the fuse line through the fuse window or not; (e) forming a patterned passivation layer over the active surface of the wafer such that the passivation layer fills up the fuse window and covers the test pad but exposes the flip-chip bonding pad; and (f) attaching a bump to the flip-chip bonding pad.
According to one embodiment of this invention, the aforementioned step (c) furthermore includes at least touching the test pad using the tip of a probe pin mounted on a cantilever probe card so that the probe pin is electrically connected to the circuit within the wafer. In addition, the wafer furthermore has a trace line on the active surface for connecting the test pad with a flip-chip bonding pad and that the patterned passivation layer also covers the trace line in step (e).
This invention also provides a chip structure with a plurality of test pads thereon. The chip structure comprises a chip and a passivation layer. The chip has an active surface, a flip-chip bonding pad and a test pad. Both the flip-chip bonding pad and the test pad are formed on the active surface of the chip. The test pad is positioned at a peripheral section of the active surface and is electrically connected to the flip-chip bonding pad. The passivation layer covers the active surface but exposes the flip-chip bonding pad.
According to one embodiment of this invention, the aforementioned chip furthermore includes at least a fuse line buried within the chip. The chip has at least a fuse window at a level below the active surface for decreasing the thickness of the section between the fuse line and the active surface. The passivation layer fills up the fuse window. In addition, the chip has at least a trace line on the active surface for connecting the test pad to the flip-chip bonding pad electrically. The passivation layer also covers the trace line.
In this invention, both flip-chip bonding pads and test pads are formed on the active surface of a chip so that the tips of probe pins are electrically connected to the test pads for testing the chip electrically. This prevents the tips of probe pins from crushing the integrated circuits embedded inside the chip due to the possible application of excessive pressure. Furthermore, after finding any defective circuits in an electrical test of the chip, the defective circuits can be replaced by cutting the fuse line using a laser beam aiming at the fuse window. After that, a passivation layer and bumps are formed on the chip. Hence, this invention reduces the number of steps required to perform the wafer level testing and to fabricate the bumping process, thereby shortening the production cycle and lowering the production cost.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
As shown in
As shown in
In the wafer level testing and bumping process of this invention, the bumps are formed on the flip-chip bonding pads on the active surface of the wafer in the very last step. Hence, there is no need to form a passivation layer prior to that. Without a passivation layer on the wafer, there is no need to re-open a hole in the passivation layer above a fuse window each time a particular fuse line must be cut by a laser beam. Furthermore, a plurality of test pads electrically connected to respective flip-chip bonding pads are formed on the active surface of the wafer to serve as testing points for testing and detecting any defects in the circuits within the wafer. Moreover, the test pads are formed on the peripheral section of the active surface. Hence, the tip of probe pins dangling from a cantilever probe card can make a direct contact with the test pads and perform an electrical testing to obtain test results for deciding whether any internal circuits need repair.
In summary, the wafer level testing and bumping process according to this invention has at least the following advantages:
1. The passivation layer and the bumps are formed over the active surface of the wafer after the completion of all integrated circuit repair operations. Hence, compared with a convention wafer level testing and packaging process, this invention does not require the re-opening of the passivation layer over a fuse window to decrease the thickness above fuse lines. In other words, the number of processing steps and hence the production cycle time and the production cost are reduced.
2. The test pads are formed on the peripheral section of the active surface of a chip. Since the test pads instead of the flip-chip bonding pads are used as contact points with the tips of probe pins dangling from a cantilever probe card for performing a wafer test, only the surface of the test pads may sustain some scratch marks or damages. In other words, the process of attaching bumps to the flip-chip bonding pads is little affected by the wafer testing operation.
3. With the test pad lying in the peripheral section of the active surface, a lower cost cantilever probe card can be used to carry out the wafer testing operation. The bumps are formed on the wafer only after the wafer test is complete.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
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|U.S. Classification||438/14, 257/E21.526, 438/131, 438/612|
|Cooperative Classification||H01L22/22, H01L22/32, H01L2224/13|
|European Classification||H01L22/22, H01L22/32|
|May 28, 2003||AS||Assignment|
Owner name: VIA TECHNOLOGIES, INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YU, YU-LUNG;NEE, JOSEPH;REEL/FRAME:014130/0236
Effective date: 20030414
|Sep 22, 2008||FPAY||Fee payment|
Year of fee payment: 4
|Sep 24, 2012||FPAY||Fee payment|
Year of fee payment: 8