If you've been following any of the industry discussion about double-patterning, you know that words such as coloring, colorless, cutting, stitching, and anchoring are now part of the vocabulary for 20nm design...
Whether you are migrating to 20nm processes, considering the migration, or just watching the fireworks, you no doubt understand that there are profound issues to consider for physical design and implementation. Double-patterning (DP) is driving new design requirements, and if you’ve been following any of the industry discussion, you know that words such as “coloring,” “colorless,” “cutting,” “stitching,” and “anchoring” are now part of the vocabulary for 20nm design. With 20nm and DP, we have geometries on the same layer being produced by different masks. This shift in silicon manufacturing changes the requirements for physical design—which means design methodologies, design tools, and verification tools must evolve to ensure we can continue producing robust designs within these new constraints.
Much of the discussion so far has addressed the physical impact of DP, but what will be the electrical impact? Consider the dilemma for the circuit designer implementing a differential pair at 20nm. Even at older technologies, the designer adheres to strict methodologies to ensure symmetrical electrical performance—wire lengths and widths must be matched, and device widths and lengths must be identical. At 28nm, poly-to-poly spacing, proximity of the device to the well, and the lengths of diffusion must also match up for the circuit to perform correctly. At 20nm, wires placed on different masks could experience slightly different process variations, resulting in a slightly different proximity to their neighbors. Designers will not only have to be diligent about keeping symmetric wires on the same mask, but will also have to pay close attention to the orientation of those geometries to which that circuit has coupling capacitance.
Let’s discuss the electrical impact of 20nm processes, and some of the techniques that can be used to mitigate performance issues.
Local interconnect: it’s back!
For starters, one of the first new innovations for 20nm is not really new at all. Local Interconnect has been absent from most of the last two process nodes (40nm and 28nm), but has returned for 20nm. The motivation is similar to that of previous incarnations—by performing local routing with this layer, standard cells and certain analog blocks can realize an area savings. Instead of going to metal layers for connections, designers can make diffusion and poly connections with local interconnect, and achieve smaller footprints for their small cell designs.
However, at 20nm, local interconnect plays the role of both contact and interconnect (Figure 1). To calculate its capacitance contribution effectively, new models must be developed that accurately characterize the coupling from local interconnect to poly, diffusion, vias, metal1 and above, as well as the coupling between local interconnect for different nets. Although these calculations will be done on very small geometries, accuracy is incredibly important if we are to achieve accurate device-level circuit simulations.
Figure 1: Local Interconnect at 20nmDouble patterning: now for something completely different!
The industry is abuzz with comments and concerns about DP. Some of the concerns are warranted, some not so much. Obviously, designers, foundries, and tool developers must develop strategies that efficiently address a possible paradigm shift driven by new manufacturing requirements.
Figure 2 illustrates the electrical phenomenon introduced by DP. Due to lithography restrictions, single layers are now split into multiple masks. To manufacture a design at 20nm, silicon manufacturers decompose IC layouts into two masks, using coloring assignments to annotate which polygons reside on which mask. During processing, each mask may shift in the x, y, or z direction, incurring additional variability that was not a factor at older process nodes. That shifting will certainly impact capacitance calculations. Depending on the type of shift, certain coupling capacitances will increase, while other coupling capacitances will decrease. Designers cannot control the process variability, but depending on the foundry, they may be able to control which polygons or nets are susceptible to the variability, by ensuring that critical nets reside on a single mask. The designer creating a differential pair, or another circuit where explicit control regarding mask assignment is needed, can assign polygons to the same color to ensure they reside on the same mask. This technique is known as anchoring, and can be used to maintain consistency and symmetry.
Figure 2: Double patterning and mask shift impacts
Anchoring works well on a small scale, for the designer who is meticulous and has the time and/or need to perform these explicit assignments, such as analog, standard cell, and embedded memory designers. Because SoC and digital designers will simply not have the bandwidth to perform these same tasks manually, they will have to rely on post-layout processes to perform the decomposition.
Regardless of the DP method used, the fundamental question remains—how to accommodate the parasitic variation incurred by the mask shift. In short, the answer is to use corner methodologies that were previously used for interlayer shifting, and apply them to intralayer shifting. For 20nm, new interconnect corners will be introduced to accommodate mask shifts. The good news is that the nanometer shifts in masks will be captured in parasitic extraction tools to accurately characterize how the circuit will perform across the entire process window. The downside is that new corners mean more extraction runs, more netlists, and more simulation.
Naturally, just because there is more work required to characterize a 20nm design does not mean that time to market windows are more relaxed. If anything, they are tighter, so the ability to efficiently handle corners in extraction, transistor-level simulation, and static timing analysis will be necessary.
The question therefore, is how can we handle additional corners more efficiently? Fortunately, for this problem, there is a solution. Different interconnect corners are essentially different versions of the process, and EDA tools have traditionally addressed multiple corners by doing a separate run for every corner. While the obvious implication is that 10 corners would incur 10X the runtime versus a single corner, that certainly is not scalable. However, despite the corner definitions, each corner is still an interconnect depiction using the same drawn input (i.e., the same design representation). Most of the computation time results from geometry processing of the design—only a small portion is the actual computation of the parasitics. Given that, there is really no reason to execute geometry processing for every corner. New techniques allow us to calculate multiple interconnect corners while performing geometric decomposition only once. This will greatly improve turn-around-time—instead of incurring the full runtime for every additional corner, we can limit the runtime increase to just 4-5% per additional corner.
In summary, there is much to consider in the way of modeling and methodologies for interconnect extraction at 20nm. Custom designers will have access to more information to help mitigate the additional variation incurred, while digital designers will need to factor in additional corners to reach design closure. However, for both audiences, EDA tools have evolved to meet those needs from both an accuracy and methodology perspective.About the author
Carey Robertson is a director of product marketing at Mentor Graphics Corp., overseeing the marketing activities for Calibre PERC, LVS and extraction products. He has been with the company for 14 years in various product and technical marketing roles. Prior to Mentor Graphics, Carey was a design engineer at Digital Equipment Corp., working on microprocessor design. Carey holds a BS from Stanford University and an MS from UC Berkeley. He may be contacted at email@example.com.
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