Plasma Technology for Advanced Devices
IMEC shows potential of FUSI for low-power applications and its extendibility to high performance - Device performance meets ITRS for 45nm
PRESENTED AT THE 2006 SYMPOSIUM ON VLSI CIRCUITS
15-06-2006 - Leuven, Belgium -- IMEC, Europe's leading independent nanoelectronics and nanotechnology research institute, reports several breakthroughs on Ni-based FUSI making it a manufacturable and reliable process for the 45nm node. Excellent low-power, high-performance specifications were achieved. The process window has been improved and work function can be modulated in a practical way.
IMEC has demonstrated the potential of fully-silicided (FUSI) gates meeting the 45nm node ITRS specifications. A ring oscillator using low-power CMOS transistors with Ni-based FUSI gates on HfSiON achieved a record unloaded delay of 17ps at an Ioff of 20pA/µm and VDD of 1.1V. The use of metal gates realized with FUSI process enabled further gate length reduction to 7nm for NMOS and 14nm for PMOS over poly-Si/SiON. In addition, IMEC demonstrated that metal gate on HfSiON devices can outperform optimized conventional Poly-Si/SiON 65nm devices by up to 25%.
By using a novel sacrificial SiGe cap at gate level, the process window, manufacturability and reliability have been improved. In a standard flow, poly-Si and spacer heights are not well controlled before FUSI due to non-uniformity in the CMP process and the need for over-etch at oxide etch-back. The SiGe cap is deposited on the poly-Si film to absorb the process variability resulting in an opening of the process window from ~5°C to ~20°C, meeting manufacturing requirements. In addition, a Vt control with o~19mV for NMOS and o~21mV for PMOS has been achieved, including wafer to wafer variation. For a 10 years lifetime, operating voltages of up to 1V were extrapolated for NMOS and up to 1.2V for PMOS devices with controlled NiSi and Ni31Si12 or Ni2Si FUSI gates making it a reliable process.
Up to now, modulating the work function covering low-Vt to high-Vt in Ni-FUSI devices was a challenging task. IMEC developed a practical method to incorporate Ytterbium (Yb) into the gate which enables modulation of the Vt for NFETs. The Yb is pre-doped into poly-Si through ion implementation. The Vt of PFETs is reduced using a Pt alloy into Ni2Si FUSI and by applying a strained Si0.8Ge0.2 channel. Vt’s down to 0.25V for NFET (NiSi:Yb) and PFET (Ni2Si:Pt + SiGe channel) were achieved on SiON without degradation of the dielectric integrity and long channel mobility.
To eliminate the gate depletion effect and enhance transistor performance, metal gates are being introduced as a replacement of conventional poly-Si gates. Ni-based FUSI has received a growing attention for sub-45nm CMOS applications since it eliminates poly depletion, it is compatible with high-k dielectrics, it’s a known material in industry and can be integrated in a conventional CMOS flow. The achieved results make FUSI a potential candidate for low-power and high-performance applications for the 45nm node.
Current research at IMEC focuses on the implementation of strain and on SiON. The extendibility towards 32nm node dimensions is also under evaluation.
These results were obtained within IMEC's core program on sub-45nm CMOS, which joins forces from eight of the world's leading IC manufacturers or foundries.