|Publication number||US7752250 B2|
|Application number||US 11/330,692|
|Publication date||Jul 6, 2010|
|Filing date||Jan 12, 2006|
|Priority date||Jan 12, 2006|
|Also published as||US20070162535|
|Publication number||11330692, 330692, US 7752250 B2, US 7752250B2, US-B2-7752250, US7752250 B2, US7752250B2|
|Inventors||Charles David Wait|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Non-Patent Citations (2), Referenced by (2), Classifications (12), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates generally to the field of computer processing and more particularly relates to a method of rounding in a floating point processing unit to obtain a more accurate answer.
A real number is represented by a whole number and a fractional part; the fractional part of the number is called the mantissa. The term floating point means that there is no fixed number of digits before and after the decimal point of mantissa; the decimal point can float in contrast to fixed-point numbers in which the number of digits before and after the decimal point is set. Computers represent most floating-point numbers as approximations using complex codes so calculations of floating-point numbers are generally slower and less accurate than fixed-point representations, but can represent a larger range of numbers. In fact, one of the challenges in developing computers with floating-point values is ensuring that the approximations lead to reasonable results. If the programmer is not careful, small discrepancies in the approximations can snowball to the point where the final results are absurd.
Calculating floating-point numbers requires a great deal of computing power and most microprocessors come with a chip, called a floating point unit (FPU), specialized for performing floating-point arithmetic. FPUs are also called math coprocessors and numeric coprocessors. The most popular code for representing real numbers is called the IEEE Floating-Point Standard. An IEEE-754 floating point number, also just called a “float”, has three components: a sign bit telling whether the number is positive or negative, an exponent giving its order of magnitude, and a mantissa specifying the actual digits of the number; there is also an analogous 96-bit extended-precision format under IEEE-854. Using single-precision floats as an example, here is the layout of the 32 bits of a four byte word:
sxxxxxxxxmmmmmmmmmmmmmmmmmmmmmmm 31 0
where s=sign bit, x=exponent, m=mantissa. The IEEE long real or double precision has one bit for the sign, eleven bits for the exponent, and 52 bits for the mantissa. The value of the number is the mantissa times 2x, where x is the exponent. There is a potential problem with storing both a mantissa and an exponent because, recall, with a floating point number, the decimal place can float so the number 0.2 can be represented as 2×10−1=0.2×100=0.02×101, etc. In the IEEE standard, the problem is circumvented by normalizing the whole mantissa as being to the right of the decimal point, with an implied “1” always present to the left of the decimal. For example, decimal 1234.567 is normalized as 1.234567×103 by moving the decimal point so that only one digit appears before the decimal. A special case exists when the number is zero; then every bit is zero and the sign bit is irrelevant. Zero is not the only “special case,” there are also representations for positive and negative infinity, and for a not-a-number (NaN) value for results that do not make sense such as the result of a divide-by-zero or an infinity-times-zero operation. A number is infinite if every bit of the exponent is set and is NaN if every bit of the exponent is set plus any mantissa bits are set. The sign bit still distinguishes +/−infinity and +/−NaN. The table below presents certain characteristics of both single- and double-precision IEEE floating point numbers:
Value for float
Value for double
Largest representable number
Smallest number w/ precision
Smallest representable number
Epsilon is the smallest x such that
1 + x > 1; It is the place value of
the least significant bit when the exponent
Floating point arithmetic uses sophisticated numerical algorithms. Because of the number of bits used to represent a floating point number, it is difficult to ascertain when two floating point numbers are equal, i.e., it is relatively rate for the numbers match bit for bit, especially when some of bits might be approximations and/or incorrect. For example, in the table above, epsilon represents how to determine if two numbers are/are not equal. The precision of a floating point number is measured in significant digits and determined by the number of correct bits. Although a 32-bit integer can represent any nine-digit decimal number, a 32-bit floating point number offers only about seven digits of precision.
Uncertain equality is only the tip of the iceberg of problems caused by limited accuracy and precision. Loss of significance refers to a class of situations wherein precision and information have been inadvertently lost with the potential of ending up with laughably bad results. To simplify things, one way to consider the problem of loss of precision is that a float gradually gets “corrupted” as more and more operations are performed. For example, a fraction such as ⅕ or 0.2 must be represented by a sum of fractions whose denominators are powers of 2. Below is the output from a program that subtracts each successive fraction from 0.2 and shows each remainder. As can be seen below, an exact value is not realized even after creating the 23 mantissa bits. The result, however, is accurate to only seven digits.
remainder = 0.075000000000
remainder = 0.012500000000
remainder = 0.004687500000
remainder = 0.000781250000
remainder = 0.000292968750
remainder = 0.000048828125
remainder = 0.000018310547
remainder = 0.000003051758
remainder = 0.000001144409
remainder = 0.000000190735
remainder = 0.000000071526
In some computer hardware architectures, such as the P
Hardware implementations for computer hardware floating point divide and square root instructions may use a Newton-Raphson algorithm or a power series approximation in a fused multiply-add arithmetic pipeline. A series of multiply-add instructions implement the algorithms and the result is rounded up or down in order to conform to the IEEE-754 floating point standard. Correctly rounding usually requires extra precision in the arithmetic dataflow mandating extra hardware, e.g., increased gate counts, power, and logic delay. For instance, one method that ensures that the confidence level of floating point calculations is good enough has been to make the whole hardware pipeline one bit wider and then to calculate the remainder. There is thus a need for a more efficient means to accomplish the required rounding.
This efficient means to accomplish and satisfy the IEEE-754 and IEEE-854 standards for floating point numbers is given by a method of rounding floating point numbers in a floating point processing pipeline, comprising the steps of: calculating an intermediate quotient of two floating point numbers, A and B; determining the unit of least precision of the intermediate quotient; calculating a first remainder using the two floating point numbers and the unit of least precision; calculating a second remainder using the two floating point numbers and the unit of least precision plus one; comparing the magnitudes of the first and second remainders; based on the magnitudes of the remainders, selecting a final intermediate quotient from one of the following: the intermediate quotient, the intermediate quotient minus the unit of least precision, or the intermediate quotient plus the unit of least precision; based on a rounding mode, selecting the correct guard and sticky bits of the final intermediate quotient; and forwarding the final intermediate quotient and the selected correct guard and sticky bits for correct rounding. The input guard bit is the unit of least precision of the normalized intermediate quotient, and the sticky bit is the logical OR of the bits following the unit of least precision of the normalized intermediate quotient.
Calculating and comparing the magnitudes of the first and second remainders determines if an infinitely precise result of a division or square root algorithm is closer to and less than the intermediate quotient; or if the infinitely precise result is closer to the intermediate quotient; or if the infinitely precise result is closer to the intermediate quotient plus the unit of least precision.
The method to round floating point numbers basically comprises determining whether an infinitely precise result of a divide or square root floating point algorithm is closer to an intermediate result, or the intermediate result less a unit of least precision, or the intermediate result plus a unit of least precision. It accomplishes this by considering the unit of least precision and all other bits of the intermediate result following the unit of least precision, such as a sticky OR bit that is the logical OR of the all other bits lower than the unit of least precision.
When the infinitely precise result is closer to the intermediate result less a unit of least precision, the intermediate result less the unit of least precision becomes a final quotient and a guard bit is zero and a sticky bit is one when the rounding modes are round-to-zero or round-to +/−infinity.
When the infinitely precise result is closer to the intermediate result less a unit of least precision, the intermediate result less the unit of least precision becomes a final quotient and a guard bit is one and a sticky bit is one when the rounding mode is round-to-nearest.
When the infinitely precise result is closer to the intermediate result plus a unit of least precision, the intermediate result plus the unit of least precision becomes a final quotient and a guard bit is zero and a sticky bit in any rounding mode.
When the infinitely precise result is closer to the intermediate result but less than the intermediate result, the intermediate result becomes a final quotient and a guard bit is zero and a sticky bit is one when the rounding mode is round-to-nearest.
When the infinitely precise result is closer to the intermediate result but greater than the intermediate result, the intermediate result becomes a final quotient and a guard bit is one and a sticky bit is one when the rounding mode is round-to-nearest.
The invention may further be considered a computer program product stored in a computer-readable medium to program a floating point processor to round floating point numbers, comprising instructions to implement the rounding method as described above.
With reference to
With reference to
Presented below is an example of a divide algorithm that might be implemented in a floating point fused multiply-add hardware pipeline. One of skill in the art will understand that the algorithm is one of many floating point algorithms that can be implemented either in software or hardware of a floating point processor; for instance, the Newton-Raphson convergence algorithm can also be used to divide floating point numbers and other algorithms are implemented for other floating point operations. The method of rounding herein is preferably implemented in floating point processor's hardware divide and square root algorithms. In order to conform to IEEE-754, different rounding modes are programmed within the computer architecture. A particular rounding mode is dependent upon the particular floating point operation. Examples of rounding modes are whether to round-to-nearest, round-to-zero, round-to +/−infinity. What this means is that given the operation, a rounding mode has been determined by the program and an intermediate result may be rounded to the nearest number. For other operations having the round-to-zero rounding mode, the next bits of an intermediate result may be rounded to zero, or may be rounded to positive or negative infinity. For example, if an intermediate result was +1.8 and needed rounding to an integer, then round-to-nearest, round-to-+infinity, round-to-infinity, round-to zero would give 2, 2, 1, 1, respectively. The +1.8 could be the intermediate result of any or many arithmetic operations. Thus, any digital arithmetic operation can have its intermediate result rounded by one of these four modes.
It is instructive to view the steps of the algorithm below while looking at
y0 − TableLookUp(B)
e = 1 − |B| (y0)
q0 = |A| (y0)
y1 = (y0)(y0) + e
e2 = |A| − q0|B|
t1 = (e) (e) + 0.5
t3 = (e2) (y1)
t2 = (t1) (t1) + 0.75
q1 = (t2)(t3) + q0
q1 + ulp = (t2)(t3) + q0
Force ulp increment,
q1R = |A| − (q1)|B|
q1ulpR = |A| − (q1 + ulp)|B|
q1 − ulp = (q1)(1 − 1/2ulp)
q1 = (q1)(1.0)
q1 + ulp = (q1 + ulp)(1.0)
In cycles 24 and 25 (see
The normalized result, i.e., the last instruction of the divide algorithm, from block 346 is also input into the divide result selection and round control block 370 which determines which guard and sticky bits will be presented to the round control block 350 and used to round the final quotient. The Write Enable (WRE) output from the divide result selection and round control block 370 presents the final intermediate divide result to the rounding procedure occurring in the rounding block 350 during stage five, and as explained with reference to
R(i + 1) >
R(i + 1)
FA > FB
q1 + ulp
q1 − ulp
q1 + ulp
Round-to +/− ∞
q1 − ulp
A brief description of the process by which the correct guard and sticky bits and the correct intermediate divide result is generated for a particular rounding mode is presented in the flow chart of
If, however, the remainder of the intermediate divide result plus the unit of least precision is not greater than zero as in step 526, then the process determines at step 528 if the infinitely precise result is closer to the intermediate divide result q1 or is closer to the intermediate divide result plus the unit of least precision. If the remainder q1ulpR is greater than q1R, then the appropriate intermediate result is q1 with both the guard and sticky bits being one, as in block 544. If, however, the remainder q1ulpR is less than q1R, then the appropriate final intermediate result is still q1 but the guard bit is zero and the sticky bit is one, as in block 550. This is the correct intermediate result to forward for final rounding in other rounding modes too, as in block 570, when the remainder q1ulpR is less than zero at step 526.
Recall that hardware divide/square root algorithms of the prior art typically expand the width of the fused multiply-add logic to gain the extra precision needed to determine the guard and sticky bit. This is shown in
It will be appreciated that variations of some elements are possible to adapt the invention for specific conditions or functions. The concepts of the present invention can be further extended to a variety of other applications that are clearly within the scope of this invention. Having thus described the present invention with respect to preferred embodiments as implemented, it will be apparent to those skilled in the art that many modifications and enhancements are possible to the present invention without departing from the basic concepts as described in the preferred embodiment of the present invention. Therefore, what is intended to be protected by way of letters patent should be limited only by the scope of the following claims.
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|US8452987 *||May 28, 2013||Broadcom Corporation||Method and system for disaster recovery in a secure reprogrammable system|
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|U.S. Classification||708/504, 708/653, 708/497|
|International Classification||G06F7/52, G06F7/38, G06F7/44|
|Cooperative Classification||G06F7/49942, G06F7/4873, G06F7/49952|
|European Classification||G06F7/487B, G06F7/499R, G06F7/499R2A|
|Feb 2, 2006||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WAIT, CHARLES DAVID;REEL/FRAME:017232/0838
Effective date: 20060105
|Jan 16, 2014||AS||Assignment|
Owner name: TWITTER, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:032075/0404
Effective date: 20131230
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