|Publication number||US4796243 A|
|Application number||US 07/166,729|
|Publication date||Jan 3, 1989|
|Filing date||Mar 1, 1988|
|Priority date||Jun 21, 1985|
|Publication number||07166729, 166729, US 4796243 A, US 4796243A, US-A-4796243, US4796243 A, US4796243A|
|Original Assignee||Nec Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Non-Patent Citations (2), Referenced by (6), Classifications (11), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation of application Ser. No. 876,482 filed on June 20, 1986, now abandoned.
The present invention relates to a time base correcting circuit for removing a time base error contained in a memory stored signal which signal is read out from the memory and, more particularly, to a time base correcting circuit for a digital video tape recorder.
In a digital video tape recorder ("VTR"), a video signal is converted into a digital video signal. The digital signal is in the form of a data train, divided into data blocks each containing about 200 to 1,000 bits of data A synchronizing signal having a predetermined bit pattern and a synchronizing address for identifying each block are added to each data block. A predetermined number of blocks are combined to form one sector. As a result, a periodic signal format in which the sector is repeated is formed. The sectored digital signal is recorded on a magnetic tape.
An error detection code may be added to the synchronising address. Generally, in recording and reproducing in a VTR, a time base fluctuation occurs which can produce a time base error in a reproduced signal. Such time base error is removed by a time base correcting circuit ("TBC"). In a digital VTR, an output signal of the TBC is supplied to an error correction process in which an error of data is corrected by using an added error correction signal such as a CRC code, and a D/A converting process to obtain an analog video signal.
The operational characteristics of the TBC are such that, as is well known in the art, a reproduced signal from the VTR is written in a memory in a write-in address synchronized with a clock which is extracted from the reproduced signal and which contains the time base fluctuation. Next, the stored signal is read out from the memory on the basis of a read-out address which is synchronized to a reference clock which is free from the time base fluctuation. In the TBC of the digital VTR, the write-in address is produced on the basis of the respective synchronizing address of each block, which synchronized address is extracted from the reproduced signal. Therefore, if the synchronizing address extracted from the reproduced signal is erroneous or an error is introduced in the extracting process, the respective block data linked to the erroneous synchronizing address will not be written in the correct memory locations and incorrect images are reproduced.
In the prior art, therefore, an error detection code is added to the synchronizing address to verify the correctness of the synchronizing address. When the synchronizing address is erroneous, the writing operation of the block data is inhibited. The TBC described above is disclosed, for example, in U.S. Pat. No. 4,398,224 entitled "Time Base Correcting Apparatus" issued Aug. 9, 1983.
If the writing operation is inhibited in the TBC because of the detection of the erroneous synchronizing address, the video data error correction process which follows the TBC, causes a data block from one of the preceding periods to be read out instead. Or a block data corresponding to the block inhibited from being written is not obtained. Thus, a characteristic of the error correction in the error correcting process becomes lower. This results in degradation of the quality of the reproduced video signal.
It is, therefore, an object of the present invention to provide a time base correcting circuit which minimizes the undesirable influences on the error correction process which follows the TBC circuit even if an erroneous synchronizing address is extracted.
Another object of the present invention is to provide a time base correcting circuit which can transmit correct block data to the subsequent error correction process even when the extracted synchronizing address is erroneous.
According to the present invention, there is provided a time base correcting apparatus which comprises: a memory circuit for temporarily storing an input reproduced signal of the type having data blocks, a synchronizing signal and synchronizing address in each respective data block; a write-in address generating circuit synchronized with the input reproduced signal for generating write-in addresses for writing the input reproduced signal in the memory circuit; and a read-out address generating circuit synchronized with a reference signal for generating read-out addresses for reading out a written signal from the memory circuit.
The write-in address generating circuit includes: a synchronizing signal detector for detecting the synchronizing signal from the input reproduced signal; a synchronizing address extracting circuit for extracting the synchronizing address from the input reproduced signal; an address counter which is responsive to a control signal for generating write-in addresses on the basis of either the synchronizing address extracted by the synchronizing address extracting circuit or a calculated address obtained by calculating a present synchronizing address from the address of the preceding block; and control means for comparing the synchronizing address extracted by the synchronizing address extracting circuit to the calculated address to generate a control signal which selects the calculated address when an inconsistency which is within a period having a predetermined number of blocks is present.
FIG. 1 is a block diagram showing one embodiment of the present invention.
FIGS. 2(a) and 2(b) are diagrams showing one example of a signal format that is recorded in a digital VTR.
FIG. 3 is a diagram for explaining the operation of a time base correction circuit according to the prior art.
FIG. 4 is a diagram for explaining an operation of the embodiment shown in FIG. 1.
FIG. 5 is a detailed circuit for the a counter circuit and controller of FIG. 3.
FIG. 6 is a timing chart for explaining the operation of the counter circuit shown in FIG. 5.
FIG. 1 shows one embodiment of the present invention in which digital, an input signal fed to a terminal 1, is reproduced from a recording medium, for example, a digital video signal of a digital VTR. The input signal at terminal 1 is written in a memory 3 at a write-in address containing time base fluctuation which is generated by write-in address generating circuit 2. Controlled by a reference signal supplied from terminal 4, read-out address is generated by a read-out address generating circuit 5. Thus, the stored signal is read out in accordance with the read-out address. The output signal from which a time base error is removed is supplied to a subsequent (or downstream) error correction circuit and a D/A converter (not shown).
It is assumed that the input signal at terminal 1 has a signal format as shown in FIGS. 2(a) and 2(b). In FIG. 2(a), a sector includes six video data blocks D0 to D5 and two correction code blocks R0 and R1. Further, and as shown in FIG. 2(b), each block contains a synchronizing signal having a predetermined Sync bit pattern, a synchronizing address having a bit pattern which identifies each block, video data and a correction code.
Reverting to FIG. 1, write-in address generating circuit 2 includes a synchronizing signal detector 6, a synchronizing address extractor 7 which extracts the synchronizing address contained in the input signal in response to the synchronizing signal detected by the synchronizing signal detector 6 and a counting circuit 8 which generates the write-in address in response to the synchronizing signal and the synchronizing address. A clock reproducer 9 reproduces a clock pulse from the input signal and feeds it to the respective circuits 6, 7 and 8. In the instant embodiment, memory 3 includes at least two sets of memory areas, for write-in and read-out operations which are complementarily switched.
In the prior art, counting circuit 8 is operated in response to the synchronizing address extracted by synchronizing address extractor 7 to generate write-in addresses for the block designated by that synchronizing address to store the input signal into the memory circuit 3. The operation of the prior art is described with reference to FIG. 3. FIG. 3 shows the relationship between the synchronizing address (a part of the write-in address) and part of the read-out address when the time difference between the write-in and read-out operations is about four blocks. In FIG. 3, the synchronizing addresses "0" to "7" correspond to eight blocks contained in one sector, which sectors are periodically repeated. Now, if the synchronizing address, which should be "5" at point P in sector S2, is erroneously read as "3", the block data corresponding to this synchronizing address is written in the memory 3 designated by the erroneous synchronizing address "3". As a result, the block data, which are intrinsically read out at the address "5", are read out at the read-out address "3" so that the wrong data block is sent to the subsequent error correction process. Moreover, the block data to be read out at read-out address "5" are that which have been written eight blocks before, i.e., written in the one-preceding sector S1 so that the read-out data block become erroneous. On the other hand, even if the writing operation of the block data is inhibitted when an error of the synchronizing address is detected, correct block data cannot be delivered from address "5" at the memory 3. Therefore, the reproduced video signal finally obtained is degraded in quality.
According to the present invention, a substitute calculated synchronizing address is generated on the basis of a preceding synchronizing address if the correctly continuity sequence of the synchronizing address is erroneously lost for a short time. The block data accompanying the erroneous synchronizing address is written into the memory by using the substitute or calculated synchronizing address. In other words, when the synchronizing address is erroneous for a short time, for example, one block period, it is assumed that the other data, for example, the video data in the block data is still correct. Therefore, the other data is written in the memory at a location of the substitute synchronizing address. The still correct other data, which is otherwise lost in the prior art, is fed to the subsequent error correction process so that the quality of the reproduced video signal is maintained. By using the substitute synchronizing address, moreover, it is possible to eliminate the problem of losing the data block stored in the memory area corresponding to another synchronizing address, i.e., the address "3" in the case of FIG. 3.
In the present embodiment, counting circuit 8 generates a write-in address signal of 10 bits, A0 to A9. The three most significant bits A7 to A9 identify data blocks. They are generated by loading the synchronizing address extracted by synchronizing address extractor 7 in a normal operation or, by using a substitute synchronizing address if the synchronizing address is discontinuous for a predetermined short period (e.g., one-block period in the embodiment). Controller 10 checks for and detects any discontinuity in the synchronizing address and selects which synchronizing address source will be used.
FIG. 4 diagrammatically aids in explaining the operation of the present invention. For the case where the synchronizing address is erroneously "3" at a point P1 in sector S1 the substitute synchronizing address "5" which is derived or calculated from the previous address "4" is used. Further, when the sequence of the synchronizing address is switched at a point P2 in sector S2, the substitute synchronizing address "5" is used instead of address "3" in the subsequent block. But a following synchronizing address "4" in the newly switched sequence is loaded and is used as the write-in address in the further subsequent block. Control of the aforementioned selection is provided by controller 10.
FIG. 5 is a circuit diagram of counting circuit 8 and controller 10 for the embodiment of FIG. 1. Counting circuit 8 includes counters 11 and 12 which generate least significant bits A0 to A6 of write-in addresses A0 to A9, counter 13 which generates the three most significant bits A7 to A9 which identify the blocks. The operation of counters 11, 12 and 13 is as follows. If the synchronizing address is correct, the synchronizing signal pulse Sync delivered from synchronizing signal detector 6 (FIG. 1) is fed through gate 14 in controller 10 to the load control terminals of counters 11, 12 and 13. Thus counters 11 and 12 are loaded with a zero whereas counter 13 is loaded with the synchronizing address SA delivered from synchronizing address extractor 7. Thereafter, in response to the clock pulse CL generated by clock reproducer 9, counters 11 and 12 generate the seven least significant bits A0 to A6 of the write-in address. As shown in FIG. 2(b), each block contains a 16 bit synchronizing signal, a 32 bit synchronizing address, 480 bits of the video data and a 32 bit correction code for a total of 560 bits. Therefore, when writing and reading is carried out at 8 bits at a time, addresses "0" to "69" (a total of 70 addresses) are used for one block i.e. 8 bits×70 addresses equals 560 bits. Seven bits A0 to A6 are necessary for generating the 70 addresses.
In the present embodiment, the synchronizing address contains 32 bits. Rather redundant, since only three bits for identifying eight blocks are utilized for the present invention. Read only memory (ROM) 15 is operative to feed an output when the address A0 to A6 reaches "68". As a result, a reset signal Sr for counters 11 and 12 is outputted from a subsequent latch circuit 16 when the address reaches "69". At that time, counters 11 and 12 are reset to provide an initial count value of zero. An enable signal En is fed from latch circuit 16 to counter 13 to increment the value of A7 to A9 of counter 13 by one. Immediately thereafter, a subsequent synchronizing signal pulse Sync is fed so that the value of A7 to A9 of counter 13 is loaded with the value of the synchronizing address SA. As a result, the synchronizing address SA is used for the write-in address. Then, when the synchronizing address is not erroneous, the least significant address bits A0 to A6 repeatedly take the values "0" to "69" and the value of the most significant address bits A7 to A9 assume the value "0" to "7" for respective blocks.
Controller 10 operates as follows. The value of most significant address bits A7 to A9 of counter 13 in counting circuit 8 is fed to a ROM 17, in which the value of bits A7 to A9 is updated by being incremented by one. The resultant value is sent through a latch circuit 18 to comparator 19. Comparator 19 receives the synchronizing address SA as its other input. As a result, when the synchronizing address SA is extracted by synchronizing address extractor 7 (FIG. 1), comparator 19 compares the synchronizing address SA with the updated synchronizing address to check the continuity of the synchronizing address. If the comparison result confirms continuity, i.e., equality, the comparator delivers an output CR which could be a low logic level, for example. Comparison output CR is sequentially fed to two-stage D-type flip-flops (hereinafter "D-F.F.") 20 and 21. A NAND gate 22 outputs a logical product of the output of the D-F.F. 20 and the inverted output of D-F.F. 21. If the comparison output CR of the comparator 19 remains at the low level, the output gate 22 is a high logical level and NAND gate 14 passes the synchronizing signal pulse Sync to the load control signal of counters 11, 12 and 13.
If the synchronizing address has lost the continuity for the one-block period, the comparator output CR will be high for the one-block period. In this case, the output of NAND gate 22 becomes low and gate 14 inhibits the synchronizing signal pulse Sync. Accordingly, since the load control signal is not fed to counters 11 to 13, counter 13 is not loaded with the synchronizing address SA. As a result, counter 13 holds the instead substituted synchronizing address which has been incremented by one from the preceding synchronizing address in response to the enable signal En delivered from latch circuit 16. The synchronizing signal pulse Sync is not supplied as a load control signal to counters 11 and 12. But reset signal Sr at latch circuit 16 is applied to counters 11 and 12 to clear them.
When the discontinuity of the synchronizing address extends over the two-block period, comparator 19 delivers a high logical level for the two-block period. In this case, the output of the gate 22 becomes high at the second block so that gate 14 passes the synchronizing signal pulse Sync as the load control signal to counters 11, 12 and 13. As a result, the counter 13 is loaded with the new synchronizing address SA to generate the most significant bits A7, A8 and A9 of the write-in address. FIG. 6 is a timing chart for explaining the operation of the circuit of FIG. 5.
As described above data blocks are written into a memory by assuming the continuity even if there is discontinuity of the synchronizing address for the predetermined short period. As a result, when only the synchronizing address is erroneous but the other data, for example, video data are correct, the video data can be fed without losing to the subsequent error correction process. Further, it is possible to prevent loss of other block data by writing under the erroneous synchronizing address. As a result, a higher quality of video signal is obtained.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3873920 *||Dec 12, 1973||Mar 25, 1975||Bell Telephone Labor Inc||Variable block length synchronization system|
|US4027283 *||Sep 22, 1975||May 31, 1977||International Business Machines Corporation||Resynchronizable bubble memory|
|US4208650 *||Jan 30, 1978||Jun 17, 1980||Forney Engineering Company||Data transmission system|
|US4357702 *||Nov 28, 1980||Nov 2, 1982||C.N.R., Inc.||Error correcting apparatus|
|US4375100 *||Oct 23, 1980||Feb 22, 1983||Matsushita Electric Industrial Company, Limited||Method and apparatus for encoding low redundancy check words from source data|
|US4377863 *||Sep 8, 1980||Mar 22, 1983||Burroughs Corporation||Synchronization loss tolerant cyclic error checking method and apparatus|
|US4437125 *||Oct 27, 1981||Mar 13, 1984||Sony Corporation||Digital signal processing method and apparatus|
|US4446490 *||Nov 17, 1981||May 1, 1984||Sony Corporation||PCM Signal processing circuit|
|US4461002 *||Jan 19, 1982||Jul 17, 1984||Sanyo Electric Co., Ltd.||Digital signal receiver|
|US4486780 *||Jan 21, 1981||Dec 4, 1984||Sony Corporation||Sequential data block address processing circuits|
|US4525840 *||Dec 6, 1982||Jun 25, 1985||Robert Bosch Gmbh||Method and apparatus for maintaining word synchronization after a synchronizing word dropout in reproduction of recorded digitally encoded signals|
|US4542351 *||Sep 8, 1982||Sep 17, 1985||Fujitsu Limited||PLL for regenerating a synchronizing signal from magnetic storage|
|US4680658 *||May 23, 1985||Jul 14, 1987||Sony Corporation||Apparatus for correcting a time base error and for compensating dropouts included in a reproduced video signal|
|US4904675 *||Feb 10, 1988||Feb 27, 1990||Zyma Sa||Phamacologically active 5-carboxy-2-(5-tetrazolyl) pyridines|
|GB2082825A *||Title not available|
|GB2120423A *||Title not available|
|JPS5994300A *||Title not available|
|1||*||Smpte Journal, No. 3, vol. 89, Mar. 1980, pp. 173 180, An Experimental Digital Video Tape Recorder ; Yokoyama et al.|
|2||Smpte Journal, No. 3, vol. 89, Mar. 1980, pp. 173-180, "An Experimental Digital Video Tape Recorder"; Yokoyama et al.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4953034 *||Dec 20, 1988||Aug 28, 1990||Pioneer Electronic Corporation||Signal regeneration processor with function of dropout correction|
|US5043830 *||Mar 21, 1989||Aug 27, 1991||Sony Corporation||System for recording and reproducing digital audio signal|
|US6006352 *||Jun 26, 1997||Dec 21, 1999||Nec Corporation||Bitstream decoding apparatus with reduced error correction processing and decoding method|
|US6029208 *||Oct 9, 1997||Feb 22, 2000||Samsung Electronics Co., Ltd.||System for generating block address by replacing second count with second valid block address whenever sync is detected or symbol count is reached in one complete block|
|US7576771 *||Mar 8, 2005||Aug 18, 2009||Advanced Micro Devices, Inc.||Method and apparatus of providing video synchronization|
|EP0817503A1 *||Jun 26, 1997||Jan 7, 1998||Nec Corporation||Decoding apparatus and decoding method|
|U.S. Classification||386/201, 714/747, 386/E05.039, 386/E05.032, 386/264|
|International Classification||H04N5/935, H04N5/956|
|Cooperative Classification||H04N5/956, H04N5/935|
|European Classification||H04N5/935, H04N5/956|
|Jun 8, 1992||FPAY||Fee payment|
Year of fee payment: 4
|Jun 19, 1996||FPAY||Fee payment|
Year of fee payment: 8
|Jun 26, 2000||FPAY||Fee payment|
Year of fee payment: 12