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|Author(s):||Nanying Yang; Jose M. Ortiz; Tam H. Duong; Allen R. Hefner Jr.; Kathleen Meehan;|
|Title:||Modeling the Inter-Electrode Capacitances of Si CoolMOSTM Transistors for Circuit Simulation in High Efficiency Power Systems|
|Published:||September 12, 2010|
|Abstract:||The CoolMOSTM transistor is a novel power MOSFET type device that utilizes a super-junction embedded within its drift region in order to improve the trade-off between on-resistance and breakdown voltage. The super-junction results in unique inter-electrode capacitance characteristics that require an advanced modeling approach to accurately represent switching performance. This paper describes a new compact circuit simulator model for the CoolMOSTM transistor and demonstrates the model performance using the Saber simulator for a 650 V, 60 A device. The new model is the first compact model suitable for implementation in the Saber simulator that accurately describes all three inter-electrode capacitances (i.e., gate-drain, gate-source, and drain-source capacitances) for the full operating range of the device. The model is derived using the actual charge distribution within the device rather than assuming a lumped charge or one-dimensional charge distribution. Simulation results are in excellent agreement with measurement results for the new model in contrast to previous modeling approaches used for this device. The compact model developed in this work is also being utilized in the design of a high efficiency soft-switching inverter for electric vehicle motor drives and a high efficiency bidirectional DC-DC converter at ZVS operation.|
|Conference:||IEEE ECCE 2010|
|Proceedings:||Proceedings of the IEEE Energy Conversion Congress and Exposition (ECCE) Conference 2010|
|Pages:||pp. 370 - 377|
|Dates:||September 12-16, 2010|
|Keywords:||CoolMOSTM, power MOSFET, superjunction, compact model, inter-electrode capacitance.|
|Research Areas:||Electric Power Metrology|
|PDF version:||Click here to retrieve PDF version of paper (733KB)|