Deconvolution is a computationally intensive digital signal processing (DSP) function widely used in applications such as imaging, wireless communication, and seismology. In this paper deconvolution of two finite length sequences (NXM), is implemented using direct method to reduce deconvolution processing time. Vedic multiplier is used to achieve high speed. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. For division operation non-restoring algorithm is modified and used. The efficiency of the proposed convolution circuit is tested by embedding it on Spartan 3E FPGA. Simulation shows that ,the circuit has a delay of 79.595 ns from input to output using 90nm process library. It also provides the necessary modularity, expandability, and regularity to form different deconvolutions for any number of bits.