|Publication number||US7119601 B2|
|Application number||US 10/911,023|
|Publication date||Oct 10, 2006|
|Filing date||Aug 4, 2004|
|Priority date||Aug 4, 2004|
|Also published as||US20060028262|
|Publication number||10911023, 911023, US 7119601 B2, US 7119601B2, US-B2-7119601, US7119601 B2, US7119601B2|
|Inventors||Leo J. Grimone, III|
|Original Assignee||Texas Instruments Incorporated|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (10), Classifications (7), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to electronic circuitry and, in particular, to a backgate pull-up for PMOS pass-gates.
A back-gate pull-up is used to reduce switch off current and powered down leakage current (Ioff) in solid state switches. In switches where power down leakage is a concern, the path from the PMOS back-gate to supply voltage needs to be blocked. Placing a diode between the back-gate and supply meets the need, but allows the back-gate voltage to drift due to substrate leakages. Lower back-gate voltages will reduce the potential between the back-gate and the drain and source of the transistor. This lower potential results in higher leakage.
A pass-gate circuit with backgate pull-up includes: a pass-gate transistor coupled between a first port and a second port; a backgate pull-up transistor coupled between a back gate of the pass-gate transistor and a gate of the pass-gate transistor; a first MOS transistor coupled between a first port and the gate of the pass-gate transistor; and a second MOS transistor coupled between a second port and the gate of the pass-gate transistor.
In the drawings:
Supplying the largest voltage possible to the PMOS back-gate will increase the potential from back-gate to source and drain and reduce the leakage of the PMOS transistor.
During power down situations, again transistor P7 connects the gate and back-gate of transistor P1 together and to the highest potential from external sources that may be connected to port A or port B. The gate and back-gate node voltage will follow the higher of the two sources connected to port A and port B through transistor P2 and diode SD1 or transistor P3 and diode SD2, respectively.
When transistors N1 and P1 are conducting during normal operation, transistor P7 is non-conducting and is a non factor.
The present invention not only produces a high potential at the back-gate of the PMOS transistor during power down situations, but it maintains it during normal operation. This eliminates a possible drift in voltages that can create additional leakage conditions. The present invention is small, simple, straight forward, and eliminates the variance in the back-gate voltage.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7372301 *||Jul 19, 2002||May 13, 2008||Kabushiki Kaisha Toshiba||Bus switch circuit and interactive level shifter|
|US7514983 *||Mar 23, 2007||Apr 7, 2009||Fairchild Semiconductor Corporation||Over-voltage tolerant pass-gate|
|US7679424 *||Mar 16, 2010||Fujitsu Microelectronics Limited||Semiconductor device with pad switch|
|US8144501||Dec 29, 2008||Mar 27, 2012||Taiwan Semiconductor Manufacturing Co., Ltd.||Read/write margin improvement in SRAM design using dual-gate transistors|
|US8467233||Jun 6, 2011||Jun 18, 2013||Texas Instruments Incorporated||Asymmetric static random access memory cell with dual stress liner|
|US20040052249 *||Jul 19, 2002||Mar 18, 2004||Kabushiki Kaisha Toshiba||Bus switch circuit and interactive level shifter|
|US20070268061 *||May 11, 2007||Nov 22, 2007||Fujitsu Limited||Semiconductor device with pad switch|
|US20080231341 *||Mar 23, 2007||Sep 25, 2008||Miske Myron J||Over-voltage tolerant pass-gate|
|US20090058496 *||Feb 13, 2007||Mar 5, 2009||Nxp B.V.||Circuit arrangement and corresponding method for controlling and/or preventing injection current|
|US20100165707 *||Dec 29, 2008||Jul 1, 2010||Yen-Huei Chen||Read/Write Margin Improvement in SRAM Design Using Dual-Gate Transistors|
|U.S. Classification||327/404, 327/537|
|Cooperative Classification||H03K17/162, H03K17/6872|
|European Classification||H03K17/16B2, H03K17/687B2|
|Nov 5, 2004||AS||Assignment|
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GRIMONE, LEO J., III;REEL/FRAME:015964/0960
Effective date: 20040826
|Mar 23, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Mar 26, 2014||FPAY||Fee payment|
Year of fee payment: 8