A VLSI architecture for Rijndael, the advanced encryption standard [electronic resource] / by Naga M. Kosaraju.
ABSTRACT: The increasing application of cryptographic algorithms to ensure secure communications across virtual networks has led to an ever-growing demand for high performance hardware implementations of the encryption/decryption methods. The inevitable inclusion of the cryptographic algorithms in network communications has led to the development of several encryption standards, one of the prominent ones among which, is the Rijndael, the Advanced Encryption Standard. Rijndael was chosen as the Advanced Encryption Standard (AES) by the National Institute of Standard and Technology (NIST), in October 2000, as a replacement for the Data Encryption Standard (DES). This thesis presents the architecture for the VLSI implementation of the Rijndael, the Advanced Encryption Standard algorithm. Rijndael is an iterated, symmetric block cipher with a variable key length and block length. The block length is fixed at 128 bits by the AES standard .
School:University of South Florida
School Location:USA - Florida
Source Type:Master's Thesis
Keywords:cryptography aes hardware architecture real time key scheduling dissertations academic usf computer engineering masters
Date of Publication:01/01/2003