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Posted: May 04, 2008
Self-perfection in nanomanufacturing
(Nanowerk Spotlight) In the past, random defects caused by particle contamination were the dominant reason for yield loss in the semiconductor industry - defects occur in the patterning process (so-called process defects) when contaminants become lodged in or on the wafer surface. Another problem are mask defects, where particle contamination on the photomask used in the lithography process end up on the wafer as defects or pattern distortions. Trying to prevent such fabrication defects, chip manufacturers have spent much effort and money to improve the fabrication process, for instance by installing ultra-clean fabrication facilities. 'Class One' cleanrooms, the cleanest of all, keep the number of particles that are larger than 500 nanometers to less than 3000 per cubic meter. It takes an incredible amount of technology to achieve and maintain such cleanliness and that's what makes these facilities so expensive to build and maintain.
With the semiconductor industry's move to advanced nanometer nodes, and feature sizes approaches the limitation of the fabrication method used, particles are no longer the only problem for chip manufacturers. In a nanoscale feature-size fabrication environment, systematic variations, such as metal width and thickness variations or mask misalignment, are also major contributors to yield loss.
Rather than perfecting a nanostructure by improving its original fabrication method, researchers at Princeton University have demonstrated a new method, known as self-perfection by liquefaction (SPEL), which removes nanostructure fabrication defects and improves nanostructures after fabrication.
SEM images of nanoscale silicon lines before (left) and after (right) treatment with open-SPEL with a single excimer laser pulse. (Reprinted with permission from Nature Publishing Group)
"When feature sizes in a device are small enough, the fabrication defects in many nanofabrication methods can become a dominant factor that determines the actual shape of the nanostructure" Dr. Stephen Y. Chou explains to Nanowerk. "Although extrinsic defects can be removed by improving the process, intrinsic defects caused by the fundamental statistical nature of a fabrication process – for example, noise in photon, electron or ion generation, scattering, and variations in chemical reaction – cannot be removed within the process regardless of improvements to it. The minimum line width and line height are often determined by the fundamental working principle of a fabrication, and are fixed once a fabrication method is selected."
"Our process removes defects after fabrication rather than in the fabrication. As structures become very small, conventional fabrications will be limited by intrinsic noise, and improving the fabrication technology becomes fruitless."
Chou, the Joseph C. Elgin Professor of Engineering at Princeton University and head of the university's Nanostructures Laboratory, developed the method along with graduate student Qiangfei Xia. Chou's lab has previously pioneered a number of innovative chip making techniques, including a revolutionary method for imprinting of nanopatterns on wafers. The scientists published their method in the May 4 online issue of Nature Nanotechnology ("Improved nanofabrication through guided transient liquefaction"), showing a technique that could lead to more precise shaping of microchip components beyond the current technology limits, potentially allowing them to be smaller, better and more powerful computers and other devices.
"SPEL is a paradigm shift in nanofabrication," says Chou. "We are able achieve a precision far beyond what was previously thought possible (e.g. ITRS – The International Technology Roadmap for Semiconductors). Using this method we reduced the line-edge roughness of 70-nm-wide chromium grating lines from 8.4 nm to less than 1.5 nm, which is well below the 'red-zone limit' of 3 nm discussed in ITRS. We also reduced the width of a silicon line from 285 nm to 175 nm, while increasing its height from 50 nm to 90 nm."
Rather than struggle to improve fabrication methods, Chou's solution would fix the defects after fabrication. Even more, the fixing is a 'self-perfection' – it automatically corrects the defects. The process is not only capable of removing both intrinsic and extrinsic defects but also of forming new shapes that may not be achievable using conventional fabrication techniques.
Chou's SPEL method achieves this by selectively melting the structures on a chip momentarily (hundreds of nanoseconds) while guiding the liquid flow into a desired shape before re-solidification. Natural forces acting on the molten structures, such as surface tension – the force that allows some insects to walk on water – smooth the structures into geometrically more accurate shapes. Lines, for instance, become straighter, and dots become rounder. The method has three basic forms: open-SPEL, capped-SPEL and guided SPEL:
Working principle of three forms of self-perfection by liquefaction (SPEL). a–c, Open-SPEL (a), capped-SPEL (b) and guided-SPEL (c) for lines and squares (or dots). SPEL selectively melts nanostructures (for example, silicon or chromium) for a short period of time (hundreds of nanoseconds) while applying a set of boundary conditions (for example, one or more plates placed in contact or a gap above) to guide the flow of the molten material into a desired geometry before solidification. SPEL can significantly reduce the LER, can increase the sidewall slope and flatten the top surface (capped- and guided-SPEL), and, moreover, narrow the width while increasing the height (guided-SPEL). (Reprinted with permission from Nature Publishing Group)
A simple straight melting was tried to smooth out the defects in plastic previously, but cannot apply to nanostructures on a chip, because of two obstacles. First, the key structures on chips are not made of plastic which can be melt at temperature close to boiling water, but rather the materials with a high melting temperature that will melt nearly everything, including other parts of the chip. Secondly, melting itself will widen the structures and round their top and side surfaces – all detrimental to the chip's integrity.
Chou overcame the first obstacle by using a light pulse from an excimer laser which melts only semiconductors and metals and only the tiny surface layer, in a similar fashion to laser eye surgery. Only 10 millionth of a second of melting is sufficient for this process since molten metal and semiconductors can flow as easily as water and have high surface tension, which allows them to smooth out even during that extremely short time frame.
The researchers overcame the second obstacle by adding a guiding to direct the flow. They placed a plate on top of the melting structure, which prevents widening of the molten structure and keeps the structure top flat and side surface straight. In one experiment, it made the edges of 70 nanometer-wide chromium lines more than five times smoother. The resulting line smoothness was far more precise than what semiconductor researchers believe to be attainable with existing technology.
Chou points out that the working principle behind SPEL is fundamentally different from conventional fabrication methods. "SPEL puts a structure into liquid phase and uses surface tensions and other guiding to change its existing shape to a desired one – this process involves different physics from conventional nanofabrication and it opens up new directions in nanomanufacturing approaches and sciences."
While SPEL can be scaled to large-area wafers (more than 8 inch diameter), Chou points out that the process does have limitations: "For example, it cannot be applied when the dimensions of the defect are comparable with the dimensions of the nanostructure, and it cannot fix defects where the total materials are insufficient" he says.
Nevertheless, several leading semiconductor manufacturers have expressed keen interest in the technique, according to Chou.