Design techniques for low-noise, high-speed fractional-N
Doctoral thesis, UCL (University College London).
This thesis presents techniques for designing fractional-N synthesisers which achieve both low phase noise and high loop bandwidth simultaneously. The objective is to provide a single-loop synthesiser solution that satisfies the requirements on both the phase noise level and frequency switching speed specified by wireless standards. The GSM 900 standard is used as the bench- mark in this work but these techniques can also be applied to synthesisers for other wireless applications. A linearised synthesiser phase noise model is proposed for evaluating the proposed techniques. The model is constructed by characterising the major sources of synthesiser phase noise and integrating them with the loop transfer function. The accuracy of the model is validated by experimental results. As quantisation noise is one major source contributing to synthesiser phase noise, a number of novel noise reduction techniques are proposed. These techniques are based on \Sigma\Delta modulation and implemented with the stored-sequence method. A streamlined procedure for designing the \Sigma\Delta sequences is proposed. A prototype hardware synthesiser is developed with the proposed techniques. The synthesiser is designed for the GSM 900 standard with an output frequency range between 890 MHz and 960 MHz. The loop bandwidth is 250 kHz. Results obtained from measurements show that the synthesiser has a phase noise performance that meets GSM 900 phase noise specifications. Results also confirm the effectiveness of the proposed quantisation noise reduction technique. A new mechanism responsible for intermodulation effects in fractional-N synthesisers is described. It is found that fractional-N synthesisers are vulnerable to VCO-to-PFD coupling, which generates a family of spurious components in the synthesiser spectrum. Analytical and numerical models are developed to predict the magnitude and distribution of these spurs. The predictions are confirmed by results from hardware synthesiser experiments.
|Title:||Design techniques for low-noise, high-speed fractional-N frequency synthesisers|
|Additional information:||Abstract contains LaTeX text. Authorisation for digitisation not received|
|UCL classification:||UCL > School of BEAMS > Faculty of Engineering Science > Electronic and Electrical Engineering|
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