|Publication number||US6327685 B1|
|Application number||US 09/310,444|
|Publication date||Dec 4, 2001|
|Filing date||May 12, 1999|
|Priority date||May 12, 1999|
|Publication number||09310444, 310444, US 6327685 B1, US 6327685B1, US-B1-6327685, US6327685 B1, US6327685B1|
|Inventors||Timothy J. Koprowski, Franco Motika|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Non-Patent Citations (5), Referenced by (113), Classifications (10), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to an improved logic built in self test (LBIST) system and more particularly to a LBIST with distributed SRSG and MISR functions, which facilitate scan vector loading and signature generation.
Trademarks: S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. and Lotus is a registered trademark of its subsidiary Lotus Development Corporation, an independent subsidiary of International Business Machines Corporation, Armonk, N.Y. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
“Built-In Test for Complex Digital Integrated Circuits”, B. Könemann, J. Mucha, G. Zwiehoff, IEEE Journal of Solid State Circuits, Vol. SC-15 No. 3, pp. 315-319, June 1980.
“Circular Self-Test Path: A Low-Cost Bist Technique”, Andrzej Krasniewski, presented Jul. 7, 1987 at Princeton Univesity.
U.S. Pat. No. 4,071,902 to E. Eichelberger et al.
U.S. Pat. No. 5,150,366 to P. Bardell et al.
As will be appreciated by those skilled in the art, as the design of electronic integrated circuit chips and devices has progressed, more and more circuitry is being disposed in increasingly dense patterns and it is becoming correspondingly more difficult to test such circuits. One methodology for performing chip test is described in U.S. Pat. No. 4,071,902 issued to Edward Eichelberger, et al. on Jan. 31, 1978 and assigned to the same assignee as the present invention and incorporated herein by reference. This patent describes the basic features of a level sensitive scan design (LSSD), which is used to facilitate circuit test. The circuits generally considered in LSSD include digital circuits having logic and memory functions used in the design and construction of digital signal processing and information handling systems and machines. Similarly, integrated circuit devices of interest typically possess blocks of combinatorial logic whose inputs and outputs are supplied to certain memory elements. In particular, in an LSSD system the memory elements or circuits comprise shift register latches (SRLs).
A prior art method referred to as self-test using MISR/Parallel SRSG (STUMPS) is used to test integrated circuit chips and devices. The acronym SRSG stands for the Shift Register Sequence Generator. Such devices are typically implemented as linear feedback shift registers. These registers generally comprise a chain of shift register elements in which Exclusive-OR elements in a feedback loop are provided so as to combine several intermediate latch output signals which are returned to the shift register input. The feedback paths are configured to result in the generation of a pseudo-random sequence of binary digits which are employed as test sequences for the above mentioned combinational circuits. The design and construction of pseudo-random pattern generators in the form of linear feedback shift registers is well known in the art. Output signals from the SRSG are fed through channels to a plurality of different scan paths. Each scan path comprises a plurality of shift register latches. The combinational logic output signals captured in the latch strings are supplied to a multiple input signature register or MISR. It will be appreciated by those skilled in the art, that the shift register latch elements also function in normal operation as, for example, sequential circuit memory elements in conjunction with combinatorial logic networks on, for example, a chip. During operation of the circuit in normal system environment, the shift register latches function as memory elements passing signals to be processed from one combinatorial block to another and at the same time typically receive input signals for subsequent application to combinatorial logic blocks in subsequent clock cycles. Thus the shift register latches play a significant role in establishing and defining stable logic outputs at appropriate points in a machine cycle. It is useful to keep in mind that the SRSG and the MISR are properly considered to be dedicated test elements. However, shift register latches serve a dual purpose which is more particularly apparent when considering the actual signal supplied to the shift register latches in normal operation.
This methodology has evolved mainly in support of LSSD logic and structural testing. The STUMPS structure shown in FIG. 1 illustrates a typical system and chip design that incorporates these concepts. See, for example, U.S. Pat. No. 5,150,366 assigned to the assignee of this patent.
Two basic components of this LBIST structure are a Linear Feedback Shift Register (LFSR) and a Multiple Input Signature Register (MISR). The LFSR serves as a pseudo random pattern generator that provides the stimuli for the logic being tested, while the MISR is utilized to generate a unique signature representing the responses from the logic. Ideally the signature for each failing device is different from the signature of a good device after a predefined number of test cycles.
The configuration of the scan chain in the LBIST test mode is partitioned into several sub-chains of approximately the same length. These chains are loaded and unloaded serially for each LBIST pattern. The pseudo random data loaded in parallel into each sub-chain is supplied by the LFSR and used as test stimuli. Similarly and simultaneously, the state of all latches in the sub-chains are unloaded serially into the MISR forming a signature representing the compressed data.
Each LBIST test pattern, in addition to the loading and unloading of the sub-chains, requires timed application of system clocks to launch the test vector from these latches through the combinational logic and capture the resulting response in the receiving latches. Since a typical system design may consist of several system clocks and various path delays, the clock test sequence and timing set-up may be applied multiple times with different clock combinations and timings. Typically, this is accomplished by an on-product clock generation (OPCG) function and LBIST control.
An LBIST test interval, in turn, consists of a relatively large number of these load/unload sequences followed each by the system clock cycles. At the end of the interval the MISR contents or signature is unloaded and compared to an expected signature. Several signature intervals may be applied to achieve the desired test coverage.
This LBIST methodology is an effective Design for Test (DFT) strategy that can support structural test from the chip level, various package levels, up to the system level. Some of the benefits associated with this approach include relatively low test data volumes, minimal VLSI test system requirements, at-speed test rates, and extendability to system test.
Alternatively, a disadvantage with this methodology is the lengthy test time required in loading and unloading a large number of pseudo random test patterns.
An object of this invention is the provision of a method to significantly reduce LBIST test time.
Briefly, this invention contemplates a method that modifies the scan chain path and scan clocks to allow for distributed LBIST test In this distributed LBIST concept, the Linear Feedback Shift Register (LFSR) and the Multiple Input Signature Register (MISR) are combined as an integral part of the scan chain, and each scan cycle is utilized as a test cycle.
The concept is further based on design and test ground rules that minimize the impact to system performance, circuit overhead, and maintain compatibility to existing structural scan configurations with:
Minimal impact to system functional paths.
No modification to system clocks.
Transitional fault coverage support.
Compatibility with OPCG & LBIST control.
These scan design modification and new test functions in conjunction with existing LBIST controls provide a compact and effective DFT methodology.
The novel concept at the root of this test methodology is a two phase LBIST sequence that allows alternate SRLs to be configured in either of two test configurations. Depending on the configuration, each SRL can function as a LFSR/MISR element or as a MISR input staging element. Additionally, all SRLs, independent of phase configuration, can launch system data.
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention, in which:
FIG. 1 is block diagram of a typical prior art, STUMPS architecture.
FIG. 2 is a diagram of the typical, prior art, LSSD scan chain configuration of FIG. 1, further illustrating the associated combinational logic.
FIG. 3 is a block diagram of a distributed Logic Built In Self Test (LBIST) latch pair, which is the building block of the distributed LBIST in accordance with this invention.
FIG. 4 is a block diagram of a distributed LBIST configuration in accordance with the invention.
FIG. 5 illustrates phase 1 and a phase 2 LBIST test mode status or systems shown in FIG. 4.
FIG. 6 is a timing diagram illustrating a distributed LBIST timing sequence in accordance with the invention.
As illustrated in FIGS. 1 and 2, a typical prior art LBIST design consists of chains of serially connected SRLs. In this typical prior art embodiment, each SRL is a master-slave combination of interconnected bi-stable latches L1 and L2 (e.g. D flip-flops). This typical prior art scan design consists of one or more scan chains of serially connected SRLs, with a system data port, and associated system clocks and scan clocks. An input SRI is connected to an input of the L1 latch at the top of the chain and an output SRO is coupled from the L2 latch at the end of the chain. An output of each L2 latch is coupled as an input to the next succeeding L1 latch in the chain. As illustrated in FIG. 2, the L1 latches also receive inputs from combinational logic elements, which comprise the combinational logic of the device under test, and the L2 latches provide an output to another stage of combinational logic. Clock inputs designated A clock and C1 clock are coupled to clock inputs to the L1 latch and a C2/B clock is coupled to a clock input of the L2 latch. FIG. 2 depicts a master-slave latch LSSD scan chain configuration, which is a typical example of a prior art implementation.
Referring now to FIGS. 3 and 4, in accordance with the teachings of this invention, a scan chain connects and clocks consecutive SRLs 12 and 14 in the chain as a pair. One or more chains are configured by concatenating pairs of these latches. Specifically, an L1 latch input for each SRL is XORed with the output of the preceding L2 latch in the chain and the L2 output of the corresponding L2 output of the SRL in the next preceding pairs of SRLs in the chain. Phase 1 and phase 2 clocks gate the inputs from the preceding input pair. A single concatenated chain is shown in FIG. 4 to which reference is now made.
In a first phase, in response to the phase 1 clock, each even SRL (designated in the drawing by the reference numbers 20, 22, and 24) functions as LFSR/MISR latch, while each odd SRL (21, 23, and 25) functions as a MISR input staging element. In a second phase, in response to the phase 2 clock, even and odd SRL swap functionality. This two phase operation allows all system data to be captured while ensuring proper MISR/LFSR cycling.
It will be appreciated that the prior art scan design of FIGS. 2 and 3 has been modified to support the distributed LBIST functions of this invention by making the modifications shown in FIG. 4, namely:
XOR of the previous two stages (L2s) to the scan-in. Allow phase 1 & 2 configuration gating.
Splitting the B-clock into B1 and B2 clocks.
Provide desired LFSR/MISR feedback.
Incorporating these above changes to the typical scan chain design one can obtain the full configuration for a distributed LBIST chain as shown in FIG. 4, while still maintaining full compatibility to the basic scan design and minimal system performance impact.
Each SRL in this example consists of a master (L1) and a slave (L2) D-type flip-flop or latch. The L1 system data port and associated system clock (C1-clk) perform the same function as in a typical prior art scan design. The L1 scan data port and associated scan clock (A-clk) are also the same except that the input scan data can be an XOR function of the data in the two previous L2 latches in the chain and optional feedback, as shown for SRL (22, 23) in FIG. 4.
The L2 slave latch for each SRL is fed from its associated master L1 latch and is clocked by the C2 system clock (C2-clk) or by the B scan clock (B1 or B2 clks). Note here that the B scan clock has been split into the B1-clk for the even SRL L2s and the B2-clk for the odd SRL L2s.
The integrated LFSR/MISR function is only active in either phase 1 or phase 2 configurations. The last SRL L2 output is connected back to the first L1 input of the corresponding phase configuration, thereby providing a feedback necessary to generate pseudo random patterns as does the LFSR of the prior art. Additionally, one can provide intermediate feedback between latches L2 and L1 of the same phase in the chain, in order to extend configurability FB1 and FB2.
FIG. 5 depicts the two phase configurations. On the left the phase 1 control state is set to “1”, the phase 2 is “0” and the SRI is “0” in order to enable the phase 1 LBIST mode. The shaded SRLs function as LFSR/MISR in this case. Conversely, the right side of the figure depicts the phase 2 LBIST mode. Note that holding a “0” to one of the XOR inputs is equivalent to a pass through function.
A full LBIST test sequence would consist of first initializing the scan chain via a normal scan load operation. This would be normally the default mode with the chip in stability state. Then one would set-up LBIST phase 1 by loading the appropriate test mode registers and by controlling the corresponding primary inputs. Once phase 1 is loaded and activated, the LBIST engine can be started for a predefined number of test cycles. At the completion of the LBIST test one can revert to the basic scan mode and unload and compare the phase 1 signature. This same process can be repeated for LBIST phase 2. This sequence is shown at the bottom of FIG. 6.
The top half of the same figure shows the associated clocks and relative timings for the basic scan cycle, the LBIST test cycle, and the LFSR/MISR shift cycle. Observe that both B1-clk and B2-clk are pulsed during the scan cycle, but only B1-clk is pulsed during the phase 1 LFSR/MISR cycle and only B2-clk is pulsed in phase 2 LFSR/MISR cycle.
Distributed LBIST in accordance with the invention would be implemented as part of the logic synthesis process. The LFSR/MISR connections would be generated during the same process where the scan chains are created. Additional self-test signals would be required for global chip controls. The implementation would be straightforward for “flat” designs, but would require more complex algorithms when applied to a hierarchical macro structured design.
In operation, it should be noted that the logic added to form SRL pairs in the chain with the outputs of one pair as inputs to the next pair with a feedback loop and the added clocks provide an ability to load simultaneously a new test pattern for all the SRLs each scan cycle. This distributed LFSR function can greatly reduce test time. The data in the SRLs at the completion of a test loop is stepped through serially to generate a compressed signature, thus functioning as a distributed MISR.
Although we have concentrated on the implementation of distributed LBIST structures, the concept can be extended to embedded memories with ABIST design methodologies. The highly structured configuration of arrays and many test methods provides us with diverse test methods that are in many instances more effective than signature analysis techniques, but the proposed method complements these techniques and offers further DFT options.
Although we have been discussing the use of this concept for VLSI chips with LBIST structures, the concept can be extended to fully integrated test sub systems. At this level of integration, the sub system would be capable of self test and self diagnosis leading to dynamic self repair. This could result in significant yield improvements at the uP test level by utilizing redundancy enabling techniques.
Similarly, at the system level the benefit of self diagnosis and self repair would be realized by dynamically reconfiguring the system and thereby minimizing system down time. A further extension of this concept in a large system environment would be to generate and store the expected signatures at system bring-up time and then invoke them for system diagnosis when required.
Alternate designs and extensions of this distributed LBIST concept can be designed to allow sophisticated LBIST sequences and functions, but these are beyond the intent of this disclosure.
While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4071902||Jun 30, 1976||Jan 31, 1978||International Business Machines Corporation||Reduced overhead for clock testing in a level system scan design (LSSD) system|
|US4688222||Dec 17, 1985||Aug 18, 1987||International Business Machines Corp.||Built-in parallel testing circuit for use in a processor|
|US4841485||Nov 5, 1987||Jun 20, 1989||International Business Machines Corporation||Read/write memory device with an embedded read-only pattern and method for providing same|
|US5150366 *||Aug 1, 1990||Sep 22, 1992||International Business Machines Corp.||Reduced delay circuits for shift register latch scan strings|
|US5239262||Feb 21, 1992||Aug 24, 1993||International Business Machines Corporation||Integrated circuit chip with built-in self-test for logic fault detection|
|US5278842||Feb 4, 1991||Jan 11, 1994||International Business Machines Corporation||Delay test coverage enhancement for logic circuitry employing level sensitive scan design|
|US5313424||Mar 17, 1992||May 17, 1994||International Business Machines Corporation||Module level electronic redundancy|
|US5488612||Oct 4, 1993||Jan 30, 1996||International Business Machines, Corporation||Method and apparatus for field testing field programmable logic arrays|
|US5535164||Mar 3, 1995||Jul 9, 1996||International Business Machines Corporation||BIST tester for multiple memories|
|US5553082 *||May 1, 1995||Sep 3, 1996||International Business Machines Corporation||Built-in self-test for logic circuitry at memory array output|
|US5557619 *||Apr 4, 1994||Sep 17, 1996||International Business Machines Corporation||Integrated circuits with a processor-based array built-in self test circuit|
|US5633877 *||May 31, 1995||May 27, 1997||International Business Machines Corporation||Programmable built-in self test method and controller for arrays|
|US5659551||Dec 14, 1995||Aug 19, 1997||International Business Machines Corporation||Programmable computer system element with built-in self test method and apparatus for repair during power-on|
|US5661732||Dec 14, 1995||Aug 26, 1997||International Business Machines Corporation||Programmable ABIST microprocessor for testing arrays with two logical views|
|US5790564||Jun 7, 1995||Aug 4, 1998||International Business Machines Corporation||Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor|
|1||"Built-In Test for Complex Integrated Circuits", B. Chinaman, J. Much, G. Zwiehoff, IEEE Journal of solid State Circuits, vol. SC-15, pp. 315-318, Jun. 1980.|
|2||"Circular Self-Test Path: A Low-Cost Bist Technique", Andrzej Krasniewski, Technical University of Warsaw, Oct. 2, 1986.|
|3||E. M. Barna, "Self-Test Diagnosis Using Parallel Superposition" Jul. 1985, IBM Technical Disclosure Bulletin vol. 28 No. 2, pp. 609-614.|
|4||W. H. McAnney et al., "Improving the Diagnostic Resolution of Built-In Test" Jan. 1988, IBM Technical Disclosure Bulletin vol. 30, No. 8, pp. 478-480.|
|5||W. H. McAnney, "Diagnosis of Self-Test Failures" Feb. 1984, IBM Technical Disclosure Bulletin vol. 26, No. 9, pp. 4483-4488.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6424926 *||Mar 31, 2000||Jul 23, 2002||Intel Corporation||Bus signature analyzer and behavioral functional test method|
|US6442722 *||Oct 29, 1999||Aug 27, 2002||Logicvision, Inc.||Method and apparatus for testing circuits with multiple clocks|
|US6453436 *||Dec 28, 1999||Sep 17, 2002||International Business Machines Corporation||Method and apparatus for improving transition fault testability of semiconductor chips|
|US6510534 *||Jun 29, 2000||Jan 21, 2003||Logicvision, Inc.||Method and apparatus for testing high performance circuits|
|US6516432 *||Dec 22, 1999||Feb 4, 2003||International Business Machines Corporation||AC scan diagnostic method|
|US6625767 *||Apr 26, 2000||Sep 23, 2003||Stmicroelectronics Sa||Method and device for collecting output logic values from a logic unit in an electronic circuit|
|US6654905 *||Apr 19, 2000||Nov 25, 2003||Lucas Industries Limited||Method and apparatus for detecting a fault condition in a computer processor|
|US6662324 *||Aug 21, 2000||Dec 9, 2003||International Business Machines Corporation||Global transition scan based AC method|
|US6671838 *||Sep 27, 2000||Dec 30, 2003||International Business Machines Corporation||Method and apparatus for programmable LBIST channel weighting|
|US6687218 *||Sep 30, 1999||Feb 3, 2004||Agilent Technologies, Inc.||Configurable communication output redundancy|
|US6694466 *||Oct 27, 1999||Feb 17, 2004||Agere Systems Inc.||Method and system for improving the test quality for scan-based BIST using a general test application scheme|
|US6708305 *||Oct 18, 2000||Mar 16, 2004||International Business Machines Corporation||Deterministic random LBIST|
|US6763488 *||Mar 9, 2001||Jul 13, 2004||Texas Instruments Incorporated||Generator/compactor scan circuit low power adapter with counter|
|US6769080 *||Mar 9, 2001||Jul 27, 2004||Texas Instruments Incorporated||Scan circuit low power adapter with counter|
|US6795945 *||Jul 9, 2001||Sep 21, 2004||Robert Bosch Gmbh||Method and arrangement for testing digital circuits|
|US6904554 *||Jun 26, 2002||Jun 7, 2005||Lsi Logic Corporation||Logic built-in self test (BIST)|
|US7039843 *||Nov 13, 2001||May 2, 2006||Sun Microsystems, Inc.||Modeling custom scan flops in level sensitive scan design|
|US7051252||Feb 15, 2002||May 23, 2006||Sun Microsystems, Inc.||Ibist identification loopback scheme|
|US7051257 *||Jul 6, 2004||May 23, 2006||Texas Instruments Incorporated||Means scanning scan path parts sequentially and capturing response simultaneously|
|US7055077 *||Dec 23, 2003||May 30, 2006||Kabushiki Kaisha Toshiba||Systems and methods for circuit testing|
|US7082559 *||Mar 7, 2002||Jul 25, 2006||Kabushiki Kaisha Toshiba||Semiconductor integrated circuit device and test method thereof|
|US7131044 *||Jul 6, 2004||Oct 31, 2006||Texas Instruments Incorporated||Means scanning scan path parts sequentially and capturing response simultaneously|
|US7131046||Dec 3, 2002||Oct 31, 2006||Verigy Ipco||System and method for testing circuitry using an externally generated signature|
|US7146587||Jan 8, 2004||Dec 5, 2006||International Business Machines Corporation||Scalable logic self-test configuration for multiple chips|
|US7162673||Sep 3, 2004||Jan 9, 2007||Integrated Device Technology, Inc.||Scan chain registers that utilize feedback paths within latch units to support toggling of latch unit outputs during enhanced delay fault testing|
|US7194669||Dec 19, 2003||Mar 20, 2007||Logicvision, Inc.||Method and circuit for at-speed testing of scan circuits|
|US7272761||Nov 4, 2004||Sep 18, 2007||International Business Machines Corporation||Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit|
|US7272764||Nov 4, 2004||Sep 18, 2007||International Business Machines Corporation||Method, system, and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit|
|US7346823||Jun 24, 2004||Mar 18, 2008||Cypress Semiconductor Corporation||Automatic built-in self-test of logic with seeding from on-chip memory|
|US7409613||Jan 8, 2004||Aug 5, 2008||International Business Machines Corporation||Simultaneous AC logic self-test of multiple clock domains|
|US7409614||Jun 18, 2007||Aug 5, 2008||International Business Machines Corporation||Method, system and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit|
|US7412637||Feb 7, 2006||Aug 12, 2008||Syntest Technologies, Inc.||Method and apparatus for broadcasting test patterns in a scan based integrated circuit|
|US7412638||Jun 14, 2007||Aug 12, 2008||International Business Machines Corporation||Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit|
|US7412672||Apr 13, 2005||Aug 12, 2008||Syntest Technologies, Inc.||Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit|
|US7447958||May 4, 2006||Nov 4, 2008||Cypress Semiconductor Corporation||Parallel input/output self-test circuit and method|
|US7493538 *||Sep 27, 2006||Feb 17, 2009||Texas Instruments Incorporated||Low power scan process with connected stimulus and scan paths|
|US7493539 *||Nov 15, 2006||Feb 17, 2009||Texas Instruments Incorporated||Separately controlled scan paths of functional registers providing stimulus/response data|
|US7502143 *||Mar 15, 2005||Mar 10, 2009||Sharp Kabushiki Kaisha||Signal processing method, signal output apparatus, signal processing apparatus, image processing apparatus, and image forming apparatus|
|US7519927||Jul 2, 2008||Apr 14, 2009||International Business Machines Corporation||Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations|
|US7552373||Jan 10, 2003||Jun 23, 2009||Syntest Technologies, Inc.||Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit|
|US7644330 *||Jan 5, 2010||Texas Instruments Incorporated||Adapting scan architectures for low power operation|
|US7653851 *||Jan 26, 2010||Janusz Rajski||Phase shifter with reduced linear dependency|
|US7657811 *||Feb 2, 2010||Texas Instruments Incorporated||Low power testing of very large circuits|
|US7721172||Jul 9, 2008||May 18, 2010||Syntest Technologies, Inc.||Method and apparatus for broadcasting test patterns in a scan-based integrated circuit|
|US7721173||May 20, 2009||May 18, 2010||Syntest Technologies, Inc.||Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit|
|US7797599 *||Sep 14, 2010||Verigy (Singapore) Pte. Ltd.||Diagnostic information capture from logic devices with built-in self test|
|US7805649||Sep 28, 2010||Mentor Graphics Corporation||Method and apparatus for selectively compacting test responses|
|US7805651||Dec 8, 2009||Sep 28, 2010||Mentor Graphics Corporation||Phase shifter with reduced linear dependency|
|US7823036 *||Dec 15, 2009||Oct 26, 2010||Texas Instruments Incorporated||Low power testing of very large circuits|
|US7853847||Sep 12, 2006||Dec 14, 2010||Synopsys, Inc.||Methods and apparatuses for external voltage test of input-output circuits|
|US7856581 *||Sep 12, 2006||Dec 21, 2010||Synopsys, Inc.||Methods and apparatuses for external test methodology and initialization of input-output circuits|
|US7865794||Mar 12, 2009||Jan 4, 2011||Mentor Graphics Corporation||Decompressor/PRPG for applying pseudo-random and deterministic test patterns|
|US7877655||Jan 25, 2011||International Business Machines Corporation||Method for performing a test case with a LBIST engine on an integrated circuit, integrated circuit and method for specifying an integrated circuit|
|US7877656||Jan 13, 2009||Jan 25, 2011||Mentor Graphics Corporation||Continuous application and decompression of test patterns to a circuit-under-test|
|US7900104||Mar 17, 2009||Mar 1, 2011||Mentor Graphics Corporation||Test pattern compression for an integrated circuit test environment|
|US7908532||Mar 15, 2011||International Business Machines Corporation||Automated system and processing for expedient diagnosis of broken shift registers latch chains|
|US7908534||Mar 15, 2011||International Business Machines Corporation||Diagnosable general purpose test registers scan chain design|
|US7996740 *||Aug 9, 2011||Texas Instruments Incorporated||Adaptor With Clocks For Like Parts of Different Scan Paths|
|US8024387||Sep 20, 2011||Mentor Graphics Corporation||Method for synthesizing linear finite state machines|
|US8032805||Sep 12, 2006||Oct 4, 2011||Synopsys, Inc.||Input-output device testing including voltage tests|
|US8032806||Sep 12, 2006||Oct 4, 2011||Synopsys, Inc.||Input-output device testing including initializing and leakage testing input-output devices|
|US8108743||Sep 27, 2010||Jan 31, 2012||Mentor Graphics Corporation||Method and apparatus for selectively compacting test responses|
|US8225156||Nov 24, 2010||Jul 17, 2012||Synopsys, Inc.||Methods and apparatuses for external voltage test methodology of input-output circuits|
|US8515727||Mar 19, 2008||Aug 20, 2013||International Business Machines Corporation||Automatic logic model build process with autonomous quality checking|
|US8533547||Jan 25, 2011||Sep 10, 2013||Mentor Graphics Corporation||Continuous application and decompression of test patterns and selective compaction of test responses|
|US8627161 *||Feb 1, 2013||Jan 7, 2014||Texas Instruments Incorporated||Low power divided scan paths with adapter and scan controller|
|US8943377||Aug 15, 2012||Jan 27, 2015||International Business Machines Corporation||On-chip detection of types of operations tested by an LBIST|
|US9128150||Oct 22, 2013||Sep 8, 2015||International Business Machines Corporation||On-chip detection of types of operations tested by an LBIST|
|US9134370||Sep 9, 2013||Sep 15, 2015||Mentor Graphics Corporation||Continuous application and decompression of test patterns and selective compaction of test responses|
|US20010047498 *||Mar 9, 2001||Nov 29, 2001||Whetsel Lee D.||Adapting scan architectures for low power operation|
|US20020083388 *||Jul 9, 2001||Jun 27, 2002||Volker Lueck||Method and arrangement for testing digital circuits|
|US20020112199 *||Mar 9, 2001||Aug 15, 2002||Whetsel Lee D.||Adapting scan-bist architectures for low power operation|
|US20020176288 *||Mar 7, 2002||Nov 28, 2002||Kabushiki Kaisha Toshiba||Semiconductor integrated circuit device and test method thereof|
|US20030093733 *||Nov 13, 2001||May 15, 2003||Sun Microsystems, Inc.||Modeling custom scan flops in level sensitive scan design|
|US20030159094 *||Feb 15, 2002||Aug 21, 2003||Smith Brian L.||IBIST identification loopback scheme|
|US20040003330 *||Jun 26, 2002||Jan 1, 2004||Lsi Logic Corporation||Logic built-in self-test (BIST)|
|US20040107395 *||Dec 3, 2002||Jun 3, 2004||Volkerink Erik H.||System and method for testing circuitry using an externally generated signature|
|US20040163021 *||Dec 19, 2003||Aug 19, 2004||Benoit Nadeau-Dostie||Method and circuit for at-speed testing of scan circuits|
|US20040243337 *||Jul 6, 2004||Dec 2, 2004||Whetsel Lee D.||Adapting scan architectures for low power operation|
|US20050005219 *||Jul 6, 2004||Jan 6, 2005||Whetsel Lee D.||Adapting scan-bist architectures for low power opertation|
|US20050108604 *||Sep 3, 2004||May 19, 2005||Wong Tak K.||Scan chain registers that utilize feedback paths within latch units to support toggling of latch unit outputs during enhanced delay fault testing|
|US20050138509 *||Dec 23, 2003||Jun 23, 2005||Naoki Kiryu||Systems and methods for circuit testing|
|US20050155003 *||Jan 8, 2004||Jul 14, 2005||International Business Machines Corportion||Scalable logic self-test configuration for multiple chips|
|US20050166104 *||Jan 8, 2004||Jul 28, 2005||International Business Machines Corporation||Simultaneous AC logic self-test of multiple clock domains|
|US20050213158 *||Mar 15, 2005||Sep 29, 2005||Sharp Kabushiki Kaisha||Signal processing method, signal output apparatus, signal processing apparatus, image processing apparatus, and image forming apparatus|
|US20060095820 *||Nov 4, 2004||May 4, 2006||International Business Machines Corporation||Method, system, and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit|
|US20060107149 *||Nov 4, 2004||May 18, 2006||International Business Machines Corporation||Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit|
|US20060242502 *||Feb 7, 2006||Oct 26, 2006||Wang Laung-Terng L-T||Method and apparatus for broadcasting scan patterns in a random access scan based integrated circuit|
|US20060253752 *||May 4, 2006||Nov 9, 2006||Krishnan Gopalakrishnan P||Parallel input/output self-test circuit and method|
|US20070113130 *||Nov 15, 2006||May 17, 2007||Texas Instruments Incorporated||Low power testing of very large circuits|
|US20070168801 *||Sep 27, 2006||Jul 19, 2007||Texas Instrument Incorporated||Adapting scan architectures for low power operation|
|US20070240025 *||Jun 14, 2007||Oct 11, 2007||International Business Machines Corporation|
|US20070245195 *||Jun 18, 2007||Oct 18, 2007||International Business Machines Corporation||Method, system and program product for boundary i/o testing employing a logic built-in self-test of an integrated circuit|
|US20080022051 *||Jul 24, 2006||Jan 24, 2008||Takeki Osanai||Systems and Methods for Providing Fixed-Latency Data Access in a Memory System Having Multi-Level Caches|
|US20080072111 *||Sep 14, 2007||Mar 20, 2008||International Business Machines Corporation||Method for performing a test case with a LBIST engine on an integrated circuit, integrated circuit and method for specifying an integrated circuit|
|US20080092003 *||Sep 27, 2006||Apr 17, 2008||Ajay Khoche||Diagnostic Information Capture from Logic Devices with Built-in Self Test|
|US20080141087 *||Feb 19, 2008||Jun 12, 2008||Texas Instruments Incorporated||core circuit test architecture|
|US20080276143 *||Jul 9, 2008||Nov 6, 2008||Syntest Technologies, Inc.||Method and apparatus for broadcasting scan patterns in a random access based integrated circuit|
|US20090119560 *||Jan 9, 2009||May 7, 2009||Texas Instruments Incorporated||Low power testing of very large circuits|
|US20090119562 *||Jan 8, 2009||May 7, 2009||Texas Instruments Incorporated||Adapting scan architectures for low power operation|
|US20090187800 *||Mar 26, 2009||Jul 23, 2009||Janusz Rajski||Phase shifter with reduced linear dependency|
|US20090210763 *||Feb 16, 2008||Aug 20, 2009||International Business Machines Corporation||Automated System and Processing for Expedient Diagnosis of Broken Shift Registers Latch Chains Using JTAG|
|US20090217116 *||Feb 25, 2008||Aug 27, 2009||International Business Machines Corporation||Diagnosable general purpose test registers scan chain design|
|US20090228749 *||Mar 2, 2009||Sep 10, 2009||Janusz Rajski||Method and apparatus for selectively compacting test responses|
|US20090235132 *||May 20, 2009||Sep 17, 2009||Syntest Technologies, Inc.||Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit|
|US20090240483 *||Mar 19, 2008||Sep 24, 2009||International Business Machines Corporation||System and computer program product for automatic logic model build process with autonomous quality checking|
|US20100095172 *||Dec 15, 2009||Apr 15, 2010||Texas Instruments Incorporated||Low power testing of very large circuits|
|US20110145666 *||Jun 16, 2011||Texas Instruments Incorporated||Adapting scan architectures for low power operation|
|US20150355276 *||Aug 10, 2015||Dec 10, 2015||Texas Instruments Incorporated||Adapting scan architectures for low power operation|
|CN102495362B||Jan 16, 2003||Mar 26, 2014||美国华腾科技股份有限公司||Method for testing a scan-based integrated circuit by synthetic broadcaster and compact tool|
|WO2003067272A1 *||Jan 16, 2003||Aug 14, 2003||Syntest Technologies, Inc.||Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit|
|WO2004074852A2 *||Feb 10, 2004||Sep 2, 2004||Logicvision, Inc.||Method and circuit for at-speed testing of scan circuits|
|WO2004074852A3 *||Feb 10, 2004||Oct 14, 2004||Logicvision Inc||Method and circuit for at-speed testing of scan circuits|
|U.S. Classification||714/733, 714/725, 714/726, 714/739, 365/201, 714/732, 714/734|
|May 12, 1999||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KOPROWSKI, TIMOTHY J.;MOTIKA, FRANCO;REEL/FRAME:009959/0987
Effective date: 19990510
|Dec 26, 2002||AS||Assignment|
Owner name: CADENCE DESIGN SYSTEMS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES;REEL/FRAME:013634/0022
Effective date: 20021219
|Mar 29, 2005||FPAY||Fee payment|
Year of fee payment: 4
|Jun 4, 2009||FPAY||Fee payment|
Year of fee payment: 8
|Jun 4, 2013||FPAY||Fee payment|
Year of fee payment: 12