Abstract : Memory cells and digital circuits mainly occupy silicon area in smart-cards, so strong density technologies are used, but associated supply voltage Vdd becomes lower than 1 volt. Besides, smard-cards are dedicated to portable application, so their consumption is limited, whereas required functionnalities increase, then elementary function consumption must be reduced. Thus, designer sizes analog cells working with nanowatt specifications (low voltage supply - no more 1 volt- and low consumption- few tens at few hundreds nano-amper). This study deals with a nanowatt analog circuit design methodology and its application to smart-card area. Self-biased and fixed bias architectures were designed with the developped methodology. Circuits sized for nanowatt specifications were simulated with Spectre and BSIM3v3 parameters of ATMEL 0.15µm CMOS technology. Transistors used in circuits are high voltage devices (HV thick oxide) Simulation results and methodology prediction are similar. Measures confirmed methodology capability to circuit sizing with nanowatt specifications.