|Publication number||US6732348 B1|
|Application number||US 09/949,253|
|Publication date||4 May 2004|
|Filing date||7 Sep 2001|
|Priority date||7 Sep 2001|
|Publication number||09949253, 949253, US 6732348 B1, US 6732348B1, US-B1-6732348, US6732348 B1, US6732348B1|
|Inventors||Mehdi Baradaran Tahoori, Shahin Toutounchi|
|Original Assignee||Xilinx, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (25), Non-Patent Citations (9), Referenced by (8), Classifications (6), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to faults in integrated circuits, and more specifically to a method for locating faults in programmable logic devices.
An important tool for semiconductor yield enhancement is fault localization. Conventional techniques of fault localization are applicable mainly to memory elements because they rely on a direct correspondence of memory address to a specific cell. It should be noted that using memory elements for failure analysis purpose is not limited to stand alone memory devices because many microprocessor or ASIC logic parts have some kind of on chip embedded or cache memory.
The memory cells in most semiconductor devices are built using two to three levels of metal. On the other hand, modern process technologies have more than eight layers of metals. Thus, memory yields are relatively insensitive to defects in higher level metals, thus cannot be relied on for yield enhancement for those levels.
One type of memory rich devices that use many levels of metal is field programmable gate arrays (FPGAs). A FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by programmable line segments (such as single length, intermediate length and long interconnect lines) that are controlled by a plurality of programmable interconnection points (PIPs). The CLBs, IOBs, and the PIPs are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and PIPs are configured. The configuration data is typically organized into frames. The configuration bitstream may be read from an external memory (e.g., an external PROM). The collective states of the individual memory cells then determine the function of the FPGA. In addition to configuration memory, many FPGAs also have embedded memories (e.g., LUT RAMs and BLOCK RAMs).
In FPGA, the interconnect resources use all layers of metal. Unlike memories where fault localization is a matter of translating the faulty logical address to its corresponding physical location, interconnect faults do not have such direct correspondence. Thus, it is important to develop a new fault localization technique that can locate faults in multiple metal layers.
The present invention involves a method for locating faults in a programmable logic device. The programmable logic device contains a plurality of nets, and each net contains a plurality of line segments connected by PIPs. A faulty net (among the plurality of nets) is first identified using conventional methods. In order to locate a fault in a net, a new design is constructed by replacing one of the plurality of line segments or PIPs with an alternative line segment/PIP. The new design is tested to determine if the fault has been removed as a result of the replacement. If the fault is not removed, the previous line segment/PIP is restored, and another line segment/PIP is replaced. This process is repeated until a design without fault is found. The location of the fault should correspond to this line segment/PIP.
This method can be used to locate both open and short faults. In one embodiment of locating short faults, the line segments of two suspected nets may be shorted to each other. The above mentioned new designs are constructed and tested for each net. This allows the faulty line segment of each net to be individually located.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.
FIG. 1A shows an example of a simple design of the present invention containing logic blocks and nets.
FIG. 1B shows another example of a simple design of the present invention.
FIG. 1C shows an example of one of the nets in FIG. 1A.
FIG. 1D shows one embodiment of a PIP and line segment of FIG. 1C.
FIG. 2 is a flow chart showing an operation of the present invention.
FIG. 3A shows a design of the present invention that can be used to locate open faults in a net.
FIG. 3B shows another design of the present invention that can be used to locate open faults in a net.
FIG. 4 is a flow chart showing a fault locating method of the present invention.
FIG. 5A is a diagram showing two nets of the present invention that may be shorted.
FIG. 5B shows a design of the present invention in which one of the PIPs is replaced.
FIG. 5C shows another design of the present invention in which one of the line segments is replaced.
The present invention relates to fault localization of programmable logic devices. In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known features have not been described in detail in order to avoid obscuring the present invention.
Digital designs that are implemented in a FPGA are typically synchronous designs. Signals are transferred at each clock tick from one stage of registered logic to the next stage. FIG. 1A shows an example of a simple design 100 that can be implemented in a FPGA. Design 100 comprises a plurality of logic blocks 102-104 connected to each other by nets, such as nets 105 and 106. Each logic block contains an input and an output port. Each logic block is connected to a clock signal line 108. A reset signal line 112 may also be included in design 100.
It should be noted that a design can be more complex than the linear design shown in FIG. 1A. FIG. 1B shows a slightly more complex design 110. It contains a plurality of logic blocks 112-116 connected to each other by a plurality of nets 122-127. In this design, each logic may have several input ports and several output ports. Even more complex designs can be built on a FPGA. The method of the present invention is applicable to both complex and simple designs.
FIG. 1C shows an example 130 of one of the nets in FIGS. 1A and 1B. It contains a plurality of line segments, such as line segments 132-135 linked by a plurality of PIPs, such as PIPs 136-139. In the drawings of the present invention, thick lines are used to show line segments. Note that it is possible for two PIPs to be connected one after another (called “bouncing”). FIG. 1D shows one example of a physical implementation 140 of two line segments (142 and 143) connected by a pass transistor 147. A memory cell 146 is used to turn on or turn off pass transistor 147, thereby connecting or separating line segments 142 and 143. Line segments 142 and 143 may correspond to line segments 132 and 133 of FIG. 1C. Pass transistor 147 and memory cell 146 may correspond to PIP 136 of FIG. 1C.
A flow chart showing an operation 150 of the present invention is shown in FIG. 2. In step 152, operation 150 identifies various net/logic pairs that contain faults. Various well known methods can be used. As an example, an integrated logic analyzer tool named ChipScope, marketed by Xilinx, Inc., can be used to identify faulty net/logic pairs. After the faulty net/logic pairs are identified, these pairs are analyzed one at a time (step 154). In step 156, operation 150 determines whether the fault is in the logic or the interconnect portion of the fault pair. One way to perform this step is to use a readback test. If a faulty pair passes the readback test, the fault is likely to be in the interconnect portion. If the fault is indeed in the interconnect portion, an open fault test is performed (step 158). In step 160, a short fault test is also performed, if there are suspected pairs that contain short faults. The details of these steps will be described below. In step 162, it is determined whether all faulty net/logic pairs have been considered. If all pairs have been considered, operation 150 terminates. If not all pairs have been considered, operation 150 routes back to step 154.
If a faulty pair does not pass the readback test, the fault is in the logic portion, step 156 will then jump to step 162 (i.e., bypassing the open fault and short fault tests). This is because the method of the present invention is not designed to test logic faults.
An open fault testing method is now described. This method is performed after it is determined that a fault may occur at the PIPs in a net or the line segments between those PIPs (based on the result of step 156). In one embodiment, a PIP or a line segment is replaced, one at a time, with an alternative PIP or line segment. This involves many simple designs that are similar to the one illustrated in FIGS. 3A and 3B.
FIG. 3A shows a net 170 that is a slight modification of net 130 of FIG. 1C. Elements that are common in FIGS. 1C and 3A have the same reference numerals. In FIG. 3A, a PIP 136 is replaced with two PIPs (174 a and 174 b) and a line segment 176. PIP 136 is shown as dashed line because it is not connected in net 170. Lines 172 a and 172 b are also shown as dashed because they are not real line segments; they are shown in FIG. 3A to pictorially separating PIPs 136, 174 a and 174 b so as not to cluster the drawings. In this new design, the original PIP 136 is replaced by an alternative path involving line segment 176 and PIPs 174 a, 174 b. It should be noted that there are many ways to construct the alternative path (e.g., more than two line segments and more than two PIPs). This replacement can be easily performed by configuring a FPGA. If PIP 136 is the faulty component, the fault will be removed by the replacement.
FIG. 3B shows a net 180 that is a slight modification of net 130 of FIG. 1C. Elements that are common in FIGS. 1C and 3B have the same reference numerals. In FIG. 3B, the intention is to replace line segment 133. One way to do so is to turn off sufficient number of PIPs connected to line segment 133 so that a router will not route any signals through line segment 133. In FIG. 3B, line segment 133 and the two PIPs adjacent thereto (136 and 137) are replaced with two PIPs (184 a and 184 b) and a line segment 186. PIPs 136, 137 and line segment 133 are shown as dashed line because they is not connected in net 180. Lines 182 a and 182 b are also shown as dashed because they are not real line segments; they are shown in FIG. 3B to pictorially separating PIPs 136, 137, 174 a and 174 b so as not to cluster the drawings. It should be noted that there are many ways to construct an alternative path. The replacement shown in FIG. 3B can be easily performed by configuring a FPGA. It is assumed that PIPs 136 and 137 are found to be good using the designs shown in FIG. 3A. If line 133 is the faulty component, the fault will be removed by the replacement.
Designs similar to that shown in FIGS. 3A and 3B are configured so that all the PIPs and line segments in a net are replaced (one new design per replacement). Each configuration is separately tested. By determining failing and non-failing designs, it is easy to deduce the location of the fault.
FIG. 4 is a flow chart showing an open fault testing method 180 of the present invention. In step 182, a faulty net is identified. In step 184, one of the wire segments or PIPs of the faulty stage is replaced with an alternative path. In step 186, the modified net is tested to determine if it now functions properly. If the net is not functioning properly, the replaced wire segment or PIP of step 184 is first restored (step 188). Another wire segment or PIP is then replaced with an alternative path (step 182). If the net is functioning properly in response to the testing under step 186, this wire segment or PIP is the source of the fault. Method 180 now terminates because the fault has been identified.
A short fault testing method is now described. A short involves two nets, and occurs between a routing resource (PIP or line segment) in a first net and one or more routing resources in a second net. The method of locating short faults comprises two steps: in the first step a failing resource in the first pair is located, and in the second step the failing resource in the second pair is located.
FIG. 5A is a diagram showing two nets that may be shorted. The first net 210 contains a plurality of line segments 212-215 and PIPs 216-219. The second net 230 contains a plurality of line segments 232-235 and PIPs 236-239. FIG. 5A also shows a dashed line 220 connecting PIP 217 and line segment 233 to indicate that there is a short between these two nets. Note that a short can occur between two line segments, two PIPs, and a line segment and a PIP.
As part of the process to examine first net 210, a PIP or a line segment of this stage is replaced, one at a time, with another PIP or line segment. FIG. 5B shows a design in which PIP 216 is replaced with two PIPs 252 a, 252 b, and a line segment 256. The new net is labeled 250. Elements that are common in FIGS. 5A and 5B share the same reference numerals. Thus, in this new design, the original PIP 216 is replaced by an alternative path. This replacement can be easily performed by configuring a FPGA. The meaning of the dashed lines in FIG. 5B is the same as that in FIG. 3A. If there is a short fault in PIP 216, the fault will be removed. Thus, by replacing PIPs or line segments one at a time, it is possible to locate the faulty segment or PIP in stage 210.
In order to complete the analysis of the short faults, the location of the faulty segment or PIP in stage 230 is performed. Similar to the case of stage 210, a PIP or a line segment of this stage is replaced, one at a time, with another PIP or line segment. FIG. 5C shows a design in which the faulty segment 233 is replaced with a good segment 276. Elements that are common in FIGS. 5A and 5C share the same reference numerals. As explained above, it may be necessary to also replace PIPs 236 and 237 with PIPs 272 a and 272 b. The replaced net is labeled as 270. This replacement can be easily performed by configuring a FPGA. If there is a short fault in line segment 233, the fault will be removed by replacing it with a good line segment 276. Thus, by replacing PIPs or line segments one at a time, it is possible to locate the faulty segment or PIP in stage 230.
If only one of the suspected nets contains fault, the faulty line segment may be shorted to a different net. In this case, another net may need to be investigated.
One advantage of the present invention is that it is possible to focus on faults on a specific metal layer by building FPGA test configuration designs that use interconnects of a specific type. For example, HEX lines in VirtexII architecture, used in some of the FPGAs marketed by Xilinx, Inc., are mostly in METAL-4. Thus designs that use HEX lines are sensitive to METAL-4 related manufacturing defects. By focusing on designs that use HEX lines, manufacturing defects on METAL-4 can be detected. Consequently, the method of the present invention may serve as a diagnosis tools for specific manufacturing metal layers.
It can be seen from the above description that a novel fault location method has been disclosed. Those having skill in the relevant arts of the invention will now perceive various modifications and additions which may be made as a result of the disclosure herein. Accordingly, all such modifications and additions are deemed to be within the scope of the invention, which is to be limited only by the appended claims and their equivalents.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5050091 *||21 Aug 1990||17 Sep 1991||Electric Editor, Inc.||Integrated electric design system with automatic constraint satisfaction|
|US5105425 *||29 Dec 1989||14 Apr 1992||Westinghouse Electric Corp.||Adaptive or fault tolerant full wafer nonvolatile memory|
|US5161157 *||27 Nov 1991||3 Nov 1992||Xicor, Inc.||Field-programmable redundancy apparatus for memory arrays|
|US5349248 *||3 Sep 1992||20 Sep 1994||Xilinx, Inc.||Adaptive programming method for antifuse technology|
|US5498979 *||20 Sep 1994||12 Mar 1996||Xilinx, Inc.||Adaptive programming method for antifuse technology|
|US5508636 *||20 May 1994||16 Apr 1996||Csem Centre Suisse D'electronique Et De Microtechnique Sa||Electronic system organised as an array of cells|
|US5777887 *||12 May 1995||7 Jul 1998||Crosspoint Solutions, Inc.||FPGA redundancy|
|US6003150 *||20 Nov 1997||14 Dec 1999||Lucent Technologies Inc.||Method for testing field programmable gate arrays|
|US6108806 *||13 Apr 1998||22 Aug 2000||Lucent Technologies Inc.||Method of testing and diagnosing field programmable gate arrays|
|US6167558 *||20 Feb 1998||26 Dec 2000||Xilinx, Inc.||Method for tolerating defective logic blocks in programmable logic devices|
|US6181614 *||12 Nov 1999||30 Jan 2001||International Business Machines Corporation||Dynamic repair of redundant memory array|
|US6209118 *||21 Jan 1998||27 Mar 2001||Micron Technology, Inc.||Method for modifying an integrated circuit|
|US6237131 *||28 Apr 1999||22 May 2001||Quicklogic Corporation||Techniques and circuits for high yield improvements in programmable devices using redundant routing resources|
|US6344755 *||18 Oct 2000||5 Feb 2002||Altera Corporation||Programmable logic device with redundant circuitry|
|US6408402 *||4 Oct 2000||18 Jun 2002||Hyperchip Inc.||Efficient direct replacement cell fault tolerant architecture|
|US6470485 *||18 Oct 2000||22 Oct 2002||Lattice Semiconductor Corporation||Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device|
|US6512708 *||16 Oct 2001||28 Jan 2003||United Microelectronic Corporation||Placement and routing for wafer scale memory|
|US6530071 *||28 Sep 2000||4 Mar 2003||Xilinx, Inc.||Method and apparatus for tolerating defects in a programmable logic device using runtime parameterizable cores|
|US6532579 *||11 Apr 2001||11 Mar 2003||Hitachi, Ltd.||Semiconductor integrated circuit and design method and manufacturing method of the same|
|US6539497 *||22 Aug 2001||25 Mar 2003||Texas Instruments Incorporated||IC with selectively applied functional and test clocks|
|US6564367 *||19 Jul 2000||13 May 2003||Hitachi, Ltd.||Logic dividing method, logic dividing system and recording medium for storing logic dividing program|
|US20020157071 *||13 Apr 2001||24 Oct 2002||Schiefele Walter P.||Method for creating circuit redundancy in programmable logic devices|
|US20020166104 *||14 Dec 2001||7 Nov 2002||Yu-Liang Wu||System and method for alternative wiring using pre-analyzed patterns|
|GB2300950A *||Title not available|
|JPH10233677A *||Title not available|
|1||*||Chapman, "FPGA design for decimeter scale integration (DMSI)", 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 2, 1998, pp. 64-72.*|
|2||*||Feng et al., "Reconfiguration of one-time programmable FPGAs with faulty logic resources", International Symposium on Defect and Falt Tolerance in VLSI Systems, Nov. 1, 1999, pp. 368-376.*|
|3||*||Hanchek et al., "Design methodologies for tolerating cell interconnect faults in FPGAs", 1996 IEEE International Conference on Computer Design: VLSI in Computers and Process, Oct. 7, 1996, pp. 326-331.*|
|4||*||Howard et al., "The Yield Enhancement of Field-Programmable Gate Arrays", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, No. 1, Mar. 1994, pp. 115-123.*|
|5||*||Kelly et al., "Defect tolerant SRAM based FPGAs", Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Process, Oct. 10, 1994, pp. 479-482.*|
|6||*||Lach et al., "Algorithms for efficient runtime fault recovery on diverse FPGA architectures", International Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 1, 1999, pp. 386-394.|
|7||*||Lach et al., "Enhanced FPGA Reliability Through Efficient Run-Time Fault Reconfiguration", IEEE Transactions on Reliability, vol. 49, No. 3, Sep. 2000, pp. 296-304.*|
|8||*||Mathur et al., "Timing driven placement reconfiguration for fault tolerance and yield enhancement in FPGAs", Proceedings of European Design and Test Conference, Mar. 11, 1996, pp. 165-169.*|
|9||*||Roy et al., "On Routability for FPGAs under Faulty Conditions", IEEE Transactions on Computers, vol. 44, No. 11, Nov. 1995, pp. 1296-1305.*|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7219287||29 Sep 2004||15 May 2007||Xilinx, Inc.||Automated fault diagnosis in a programmable device|
|US7219314 *||1 Apr 2004||15 May 2007||Xilinx, Inc.||Application-specific methods for testing molectronic or nanoscale devices|
|US7394708||18 Mar 2005||1 Jul 2008||Xilinx, Inc.||Adjustable global tap voltage to improve memory cell yield|
|US7493585 *||13 Jul 2006||17 Feb 2009||Altera Corporation||Methods of packing user logical RAM into dedicated RAM blocks and dual-use logic/RAM blocks|
|US7672738||2 Mar 2010||Derek Ward||Programmable controller for use with monitoring device|
|US20020099455 *||9 Nov 2001||25 Jul 2002||Derek Ward||Programmable controller|
|US20060079970 *||6 Sep 2005||13 Apr 2006||Derek Ward||Programmable logic controller and related electronic devices|
|US20080058962 *||5 Sep 2007||6 Mar 2008||Derek Ward||Programmable logic controller and related electronic devices|
|U.S. Classification||716/112, 716/126, 716/117|
|7 Sep 2001||AS||Assignment|
Owner name: XILINX, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TAHOORI, MEHDI BARADARAN;TOUTOUNCHI, SHAHIN;REEL/FRAME:012168/0624
Effective date: 20010906
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