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|Title: ||A novel low power multilevel current mode interconnect system|
|Authors: ||JOSHI, S|
|Keywords: ||readout circuit|
|Issue Date: ||2006|
|Publisher: ||IEEE COMPUTER SOC|
|Citation: ||IEEE Computer Society Annual Symposium on VLSI, Proceedings: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES,122-127|
|Abstract: ||We propose circuits for low power high throughput multilevel current mode signaling using 2 bit simultaneous data transfer A novel design of the receiver for very low line voltage swings is discussed. The technique involves matching the receiver impedance to the line impedance thereby reducing the ringing on the wire. Simulation results show upto 50% reduction in latency and upto 100 times reduction in power over voltage mode buffer insertion techniques. We also show that the delays through this system are largely independent of the interconnect lengths. Data rates of upto 1Gb/s have been obtained. A power consumption model is derived for the system which matches the simulation results to within 5%.|
|Appears in Collections:||Proceedings papers|
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