|Número de publicación||US8028186 B2|
|Tipo de publicación||Concesión|
|Número de solicitud||US 11/975,269|
|Fecha de publicación||27 Sep 2011|
|Fecha de prioridad||23 Oct 2006|
|También publicado como||CN101611452A, EP2076903A1, EP2076903B1, EP2498257A1, EP2498257B1, US8090973, US8806262, US20090043933, US20110060857, US20120079163, WO2008051467A1|
|Número de publicación||11975269, 975269, US 8028186 B2, US 8028186B2, US-B2-8028186, US8028186 B2, US8028186B2|
|Inventores||Jon C. R. Bennett|
|Cesionario original||Violin Memory, Inc.|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citas de patentes (185), Otras citas (67), Citada por (3), Clasificaciones (19), Eventos legales (8)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
This application claims the benefit of U.S. provisional application Ser. No. 60/853,852, “Skew Management in an Interconnection System,” filed on Oct. 23, 2006, the application being incorporated herein in its entirety by reference.
Generally, the evolution of computer and communications products has been governed by such principles as “Moore's Law”, where both the density of the components increases, and the cost of such a component decreases with time. This has also often been accompanied by increases in transfer and computation speed. These trends have often increased the power dissipation density and required new solutions to either dissipate the heat or operate in the high temperature environment. In high speed circuits, both signal propagation delay and the design and manufacturing tolerances may place limitations on the realizable speeds attained in practice.
Contemporary memory system architectures may demonstrate tradeoffs between cost, performance and the ability to upgrade, for example; the total memory capacity of the system. Memory capacity is commonly upgraded via memory modules or cards having a connector/socket interface. Often these memory modules are connected to a bus or interconnecting wiring disposed on a backplane to utilize system resources efficiently. In addition to upgradeability, many of these contemporary memory systems also require high throughput for bandwidth intensive applications, such as graphics.
One popular type of memory module is a Dual In-line Memory Module (DIMM). The DIMM is a rectangular low-profile circuit board that has electrical contact points arranged on both sides along one long edge. The contact points form electrical connections to the main board memory bus when the DIMM is inserted into a DIMM memory socket.
Memories used in computing and communications systems include, but are not limited to, random access memory (RAM) of all types (e.g., S-RAM, D-RAM); programmable read only memory (PROM); electronically alterable read only memory (EPROM); flash memory, magnetic memories of all types including Magnetoresistive Random Access Memory (MRAM), Ferroelectric RAM (FRAM or FeRAM) as well as NRAM (Nanotube-based/Nonvolatile RAM) and Phase-change memory (PRAM), and magnetic disk storage media. Other memories which may become suitable for use in the future include quantum devices and the like.
At present, the size and performance of memory systems may be limited by power consumption, by cooling capacity associated with the power consumption and device density, by response time due to, for example, data skew, by the complexity of the circuit boards needed to interconnect the memory elements, and by the economic costs of these considerations.
This application is related to U.S. Ser. No. 11/405,083 “Interconnection System” by the same inventor, filed on Apr. 17, 2006, the application being incorporated herein in its entirety by reference.
An interconnection system is disclosed, including a bus having a plurality of signal lines, each line capable of transmitting or receiving a signal comprising a data bit. A data bit on a first line and a data bit on a second line and are exchanged between signal lines an interval along the bus. In an aspect, the data is transmitted on three or more signal lines, and the data bits are exchanged such that the data bit having a first time delay is exchanged with the data bit having a second time delay. In another aspect, an exchange pattern of a first exchange pattern is used for each subsequent exchange.
An interconnection system is disclosed including a plurality of nodes, the nodes forming a network connected by links having a plurality of lines, and motherboard having a connector for interfacing with a node of the plurality of nodes. A first node is a source of data, and a second node is a destination of data, and at least one of the first node or the second node is configurable to change the assignment of data between lines. In an aspect, the data is transmitted on three or more signal lines, and data bits of the data are exchanged such that a data bit on a line having a larger cumulative time delay is exchanged with a data bit on a line having a smaller cumulative time delay.
A node of an interconnection system includes a switch, an input port and an output port, each port having first, second, third and fourth lines. The first line of the input port is connected to the second line of the output port, and the third line of the input port is connectable to one of the first, third or fourth lines of the output port. In an aspect the second line of the input port is connected to the first line of the output port. In another aspect, the third line of the input port is connectable to one of the third or fourth lines of the output port.
A module includes a connectorized circuit card, having a connector with multiple connectable elements and an electronic circuit module having input connections and output connections communicating with connectable elements of the connector. An input connection and an output connection are disposed so that the difference in transmission delay between pairs of input connectable elements and output connectable elements is reduced.
A method of compensating for data skew in an interconnection includes providing a signal bus having a plurality of lines, connecting a plurality of nodes to the signal bus; determining differential time delays for signal transmission between adjacent connected nodes on the bus; and interchanging data lanes between lines so as to change a time delay difference for data between at least a pair of the lines of the bus when measured at a destination mode.
A method for compensating for data skew in an interconnection system includes providing a node connectable to a signal bus, the node comprising at least a switch and configuring the switch such that at least a first input line is connected to other than a first output line. In an aspect, at least one path is provided as a fixed connection between the first input line and other than the first output line.
A software program product, stored on a machine readable medium, includes instructions configuring an electronic device to determine a differential time delay for signal transmission between connected nodes on a bus; and to configure the assignment of data lanes between lines of the bus so as to change a time delay difference for data between at least a pair of lines of the bus when measured at a subsequent node.
Exemplary embodiments may be better understood with reference to the drawings, but these embodiments are not intended to be of a limiting nature. Like numbered elements in the same or different drawings perform equivalent functions. Elements may be either numbered or designated by acronyms, or both, and the choice between the representation is made merely for clarity, so that an element designated by a numeral, and the same element designated by an acronym or alphanumeric indicator should not be distinguished on that basis.
It will be appreciated that the methods described and the apparatus shown in the figures may be configured or embodied in machine-executable instructions and electronic components; e.g., software, hardware, or in a combination of both. The instructions can be used to cause a general-purpose computer, a special-purpose processor, such as a DSP or array processor, or the like, that is programmed with the instructions to perform the operations described. Alternatively, the operations might be performed by specific hardware components that contain hardwired logic or firmware instructions for performing the operations described, or which may be configured to so, or by any combination of programmed computer components and custom hardware components, which may include analog circuits.
The methods may be provided, at least in part, as a computer program product that may include a machine-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices, such as a field programmable gate array (FPGA), or the like) to perform the methods. For the purposes of this specification, the terms “machine-readable medium” shall be taken to include any medium that is capable of storing or encoding a sequence of instructions or data for execution by a computing machine or special-purpose hardware and that cause the machine or special purpose hardware to perform any one of the methodologies or functions of the present invention. The term “machine-readable medium” shall accordingly be taken include, but not be limited to, solid-state memories, optical and magnetic disks, magnetic memories, optical memories, and carrier wave signals. The software may be stored or distributed on one medium and transferred or re-stored on another medium for use.
For example, but not by way of limitation, a machine readable medium may include read-only memory (ROM); random access memory (RAM) of all types (e.g., S-RAM, D-RAM); programmable read only memory (PROM); electronically alterable read only memory (EPROM); magnetic random access memory; magnetic disk storage media; flash memory; electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, or digital signals).
Furthermore, it is common in the art to speak of software, in one form or another (e.g., program, procedure, process, application, module, algorithm or logic), as taking an action or causing a result. Such expressions are merely a convenient way of saying that execution of the software by a computer or equivalent device, such as a FPGA, causes or configures the processor of the computer or the equivalent device to perform an action or a produce a result, as is well known by persons skilled in the art.
When describing a particular example, the example may include a particular feature, structure, or characteristic, but every example may not necessarily include the particular feature, structure or characteristic. This should not be taken as a suggestion or implication that the features, structure or characteristics of two or more examples should not or could not be combined, except when such a combination is explicitly excluded. When a particular feature, structure, or characteristic is described in connection with an example, such feature, structure, or characteristic may be used in connection with other examples, whether or not explicitly described.
A connector or connector interface as described herein, such as a memory module connector interface, is not limited to physically separable interfaces where a male connector or interface engages a female connector or interface. A connector interface also includes any type of physical interface or connection, such as an interface where leads, solder balls or connections from a memory module, a switch or the like, are soldered to a circuit board. For example, in a stacked die approach, a number of integrated circuit die (e.g., memory devices and buffer devices) may be stacked on top of one another with a substrate forming the base and interface to a memory controller or processor through, for example, a ball grid array type of connector interface. As another example, a memory, switch or buffer device may be interconnected via a flexible tape interconnect and interface to a memory controller through one of a ball grid array type connector interface or a physically separable socket type connector interface. Connection types may include the interface between integrated circuit chips, interconnection conductors on a substrate, between substrates, or on printed circuit boards, or the like.
A node may include memory and may also have a controller for the memory, a configurable switching element (CSE) and other circuitry for processing, transmitting or receiving signals. However a module may include the memory, and one or more of the other elements may be separately mounted. Alternatively, the module may include the CSE and one or more of the other elements may be separately mounted. Except as specifically mentioned herein, the allocation of the functions to specific modules is intended for convenience in discussion, as a person of skill in the art will appreciate that the actual physical aspects and computational aspects may be arranged in a variety of equivalent ways.
“Bus” or “link” means a signal line or a plurality of signal lines, each having one or more connection points for “transceiving” (i.e., either transmitting, receiving or both). Each connection point may connect to couple to, or to communicate with a transceiver (i.e., a transmitter-receiver) or one of a single transmitter or receiver circuit. A connection or coupling is provided electrically, optically, magnetically, by way of quantum entanglement or equivalents thereof. Other electrical connections, by the same or similar means are used to provide for satisfaction of such additional system requirements as power, ground, auxiliary signaling and control, or the like. Such additional connections are occasionally described so as to clarify the description, however such additional connections are well known to persons skilled in the art, and the lack of description of these connections in any example should not be taken to exclude their inclusion.
A link carries signals on a signal lines. Signals fall generally into any of several categories including clock and control signals, address signals, command signals, and data signals. Data signals carry data that may be stored in, or retrieved from, a memory device or interface. Address signals specify the location or range of locations within a memory device or system where data is to be read from or written to, and may also select which of one or a plurality of memory devices or interfaces is to be accessed. Command signals instruct a memory device or interface as to what type of operation is to be performed, e.g., read, write, refresh, or access mode (such as a burst or broadcast mode) should be used for a data transfer. Clock and control signals synchronize the other signals passing between controller and the memory devices. Although a link may use a separate signal line for each signal (e.g., 32 address lines to transfer a 32-bit-wide address in one clock cycle and 32 data lines to transfer a 32-bit-wide data word in one clock cycle), various schemes also exist to re-use one or more signal lines for different signals, various schemes also exist to re-use one or more signal lines for command signals, control signals, address signals, or data signals during different clock cycles of a memory transaction.
It should be appreciated that when lines are discussed as being connected to an interface or to a port, it is convenient to describe the lines as being active, being powered on or powered off, being in standby mode, or the like. This is meant to be interpreted as referring to the status of the connection at an interface with a port at a node, and may include other node functions. The lines themselves may be merely metallic traces on a circuit board, or the like, serving to provide connections between nodes.
The use of the term “line” herein to refer to a physical line, which may have data logically assigned thereto, differs somewhat from the pervious usage in U.S. Ser. No. 11/405,083, where the terms line and lane were often used interchangeably. Whether the term lane was meant to be interpreted as being a physical object, now called a line, or, alternatively, a logical construct associated with a data word or data bit, was understandable from the contextual usage of that specification. Herein, and for future use, but not retrospectively, the term lane will connote a logical concept associated with data. A lane of data may be associated with the physical line on which the data travels as signals between nodes or other electronic components, which may be both active and passive components. As such, the lane may be said to be bound to a line when the data of a lane is transmitted as a signal on a line. The binding of the lane to a line may change so that the lane may be reassigned to another line. Similarly, the term bus or link may now be called a channel, and whether the terms refer to a collection of logical lanes or to a collection of the lines will be apparent from the context.
The terms lane and line, as now used, may be understood with reference to
A “breadth-first” convention is often used in numbering the nodes in a tree; that is, to start at a root of the tree and work across all the elements at a given level before moving on to the next level. This numbering is for convenience only. For implementation purposes many different numbering schemes might be used, including two or more numbering schemes simultaneously. For signaling purposes the convention “port 0”, “port 1”, or “port A” or “port B” may refer to relative rather than absolute ports. By convention, “southbound”, “downstream” or “secondary” refers to the direction heading away from a module controller or root while “northbound”, “upstream” or “primary” refers to the direction heading towards the module controller or root. There may be more that one root or module controller, and each of them may be operable contemporaneously.
An additional consideration is the time dispersal of the data bits in each data word, packet or frame. In many links, the bits of the data may be sent on in parallel on lines. It should be understood that this may a simplification of the actual situation, as the data may be sent over parallel lines with more than one bit of a data word transmitted on each line in a serial fashion, as an example. Due to differential delays of the signals on the lines, the differential delays being associated with, amongst other factors, line length, impedance, electronic bandwidth, and the like, the signals representing data bits may not arrive with sufficient simultaneity for immediate processing and it may be necessary to wait or buffer the data for one or more clock cycles or data frames, until all of the bits have been received by a module or node in order to proceed with decoding or other data processing. This delay further increases the time necessary at each node before the address, or other information, can be acted upon. In such a circumstance, and where it may be desired to turn on the lines of links only as they are required for data transmission (where transmission is generally understood to include reception), the address information may have to be sent a period of time in advance of the associated command or data. This may have the effect of reducing the system transfer capacity or bandwidth.
The effective physical lengths of the individual lines in a link may generally be different, and there may be a time difference in the time of arrival of bits sent on different transmission lines. This may be termed data “skew”. One method of accommodating data skew is to perform de-skew at each hop such that the header of a data packet may be interpreted and the packet transmitted on the next hop. However, this may add significant latency time to the re-transmission, as the de-skew process may require at least as much time as the longest differential delay between lines between each node. Other approaches attempt to avoid this additional delay by not performing de-skew at each node, but to perform the de-skew at the receiver of the addressed module or node, while allowing the skew to build up along the path. But, the cumulative delay can also add significant total delay, as the differential delay accumulated from the source (e.g., a memory controller) to the destination node may need to be accommodated, even though part of the data packet may have arrived earlier.
In the FB-DIMM technology as being developed by INTEL, devices are believed to be required to be able to correct for a skew of up to six UI per hop. The term “UI” or “Unit Interval”, which is the average time interval between transitions of a signal, may be used at high clock rates in place of a clock period, as the clock period may not be completely stable or free of jitter. If six UI of skew per hop is expected, and a memory system has 8 hops, the total skew is 48 UI.
In the case of a link running at a clock speed of nominally 2 GHz with a data rate of 4 Gbps, 1 UI=250 picoseconds (ps) so a delay skew of 48 UI is the equivalent of 12 nanoseconds (ns) of skew. That is, it is assumed that 12 ns is needed between the first arriving bit on one line and the last arriving bit on one of the other lines. The first arriving bits may need to be stored in memories, latches or shift registers, or the like, until such time as the later arriving bits arrive, and then the bits are presented to the device which is to de-skew and read the data.
Among the causes of skew is the situation shown in
For illustrative purposes, a standard size DIMM module is used as a reference. Such modules are about 140 mm in width, and therefore, the distance to lane 0 from the center, where the switch is located, is about 70 mm. Attributing a length of 20 mm to the length of line 4 between the AMB and a corresponding pin on the connector, the maximum differential length, in this example, between the shortest and longest traces is about 50 mm, which corresponds to an approximate difference in propagation time of about 250-350 ps. This represents the estimated situation with an existing DIMM. Where the data rate is nominally 4 GB/s, this may result in one or two clock periods of skew from this effect alone.
While several standardized DIMM or memory modules exist, the term DIMM or memory module as used herein should be understood to refer to any of the memory types which may be used as mounted to a circuit board having a connector interface for connection to other modules circuits and the like. The number of pins or traces, the dimensions of the circuit board, and the capacity and type or types of memory on the DIMM or memory modules are not restricted to such pin counts, interconnect counts, dimensions, types and capacities as are now being produced or used.
For this example, where the delay between modules is presumed to range from 1-6 (arbitrary units) for illustrative purposes, and the input and the output lines from each module have the same data assigned or bound at the output of a given line number as that which arrived on the input, the output data pattern associated with each module is the same as the input data pattern: A, B, C, D, and E associated with lines 0-4 respectively. By following the progression of the tables from module-to-module in the downstream direction, the total delay for each line is seen to be the sum of the delays for that line between the MC and the module which is associated with the table. For example, the total delay experienced between the MC and the 5th module (M4) is 30 units for line 0, but only 5 units for lane 4. The other lines, in this example, experience intermediate amounts of time delay. If the delay units were associated with clock cycles, then the data on line 0 would arrive 25 clock cycles behind that for line 4.
The delay time values are given as integer values and which are the same in a given line between each of the modules are for illustrative purposes only. The delays need not be integer valued nor must they be the same at each hop between modules.
In this example, if the total length of the command, or data packet, or frame, being sent was, for example, 10 clock cycles, then about 2.5 commands would be in the process of being received at any time by module M4. Thus the last module may need to buffer more than two complete commands at any time before it could process the first command, as all of the bits of the first command will take this long to be received as a complete group. In this example, the second command and part of the third command will have begun to have been received at module M4 before all of the bits of the first command will have been received.
For example, at the first module (M0), the data lane A that came in on line 0 is output on line 4; the data lane B that came in on line 1 is output on line 3; the data lane D that came in on line 3 is output on line 1; the data lane E that came in on lane 4 is output on line 0; and, the data lane C that came in on line 2 is output on line 2.
At the output of module M1, the differential delay situation is the same as shown for module M1 in
Following the reassignment or exchanging of the data lanes A-E to lines 0-4 at each module, the difference in delay between the various data lane assignments A-E is seen to accumulate monotonically, as in the previous example. The data lanes may continue to be exchanged to an appropriate line at each module. At the last module (in this example M4), the associated table shows that the range of delays associated with the various data lanes elements ranges from 15 units to 18 units, for a total delay spread of 3. This may be compared with the example of
The bit assignment strategy used in the example was to select the data which had experienced the highest accumulated time delay and assign it as an output to the line having the lowest accumulated time delay. Similarly, the data with the lowest accumulated time delay is assigned to the line with the highest accumulated time delay. Other strategies may also be used, where the differential skew may be increased, decreased, or remain the same when measured at a particular location in the system.
In the description, the delays are given integer values for simplicity of presentation; however non-integer values are also possible as the time delay is stated in arbitrary units representing some multiple of the clock rate. Alternatively, the time delay and differential time delay may be expressed in integer and fractional clock durations.
The time delays are shown as having been previously determined, as the basis for the setting strategy and configuration of the lane-to-line-swapping switches. Such a determination may be made at the time of system design or prototyping, the time of manufacture, the time of assembly of the modules into a system, system start up, each system start up, or by measurements made during the operation of the system. The selection of the time or times to perform this determination may be associated with the desired performance and the complexity of the system, and may take into account manufacturing variability and temperature effects, as well as active or passive component failure or degradation.
The function of interchanging exchanging, swapping, re-assigning, or binding of lanes to lines may be performed by a switch, however the use of the term “switch” does not serve to limit the specific implementation of the function to a discrete device; any mechanism that achieves the interchanging, exchanging, re-assignment, swapping, or binding of the lanes may be used. For convenience, the term “switch” when applied to this aspect of the system, apparatus, or method is meant to encompass the range of techniques which are available to perform the function. Such techniques may use memory storage locations, operation of a state machine or a stored program computer, and dedicated electronic logic circuits and the like, either alone on in combination. Such switching may be performed on a static or a dynamic basis, depending on the design requirements of a specific product. The term switch may also include the swapping of lines using fixed connections or traces, which may include fusible links or other techniques which have an equivalent result.
The situations illustrated are directed to a MC to module transfer, but may be effectively used for other paths, such as DMA transfers between modules, and for different channels or branches of a tree. While the discussion has addressed the path from a MC, for example to a module, these operations may be equally performed in the reverse direction. That is, for example, while the discussion has addressed a southbound direction, the northbound direction may be similarly described.
In some arrangements, it may be found that one or more patterns of lane interchange are frequently encountered.
For some applications, the fixed exchange of lines may be sufficient to result in an acceptable total delay and differential skew. If the lines were not exchanged in this example, then the total delay of line 1 would be 30, and the total delay of line 4 would be 5, for a differential delay of 25. However, from
The input data representation at the MC, ABCDE, is replicated at the input M4. This results means that the bus length may be extended indefinitely and while the total delay will increase such that the total delay is doubled for double the bus length, and the maximum differential delay experienced at any periodic point along the bus may also double, and the pattern repeats.
The effect of time delays within a semiconductor device such as a AMB or CSE, or the like, are not shown in these examples, and a person of ordinary skill the art would consider the effect of such time delays, and any variability in time delay in the design of a system, node, or module. The use of physical connections or fixed switch connections to realize fixed permutations may reduce any additional time delays. The physical connections may be traces, be fusible links, or be any other technique of construction that achieves the same aim.
Another of the lane-to-line exchange permutations which may be employed is shown in
While a fixed pattern of exchanges has been shown in
One method of performing the permutation exchanges is by arranging the wiring of a module.
Using the same input configuration as
Although the line exchanges have been described using a node or module with one input port and one output port, this is not a restriction.
Port A input lines and port B and C output lines are shown disposed on the top layer of the board, connecting the pins or balls of the chip to an edge of the module.
Exchanges may be performed either partially or wholly on a mother board having connectors for receiving modules.
A light grey line surrounds groups of components which may operate within a local clock domain. Operation in differing clock domains may result from internal signal propagation delays, or even when the same clock domain may be buffered prior to use with each of the areas within a local clock domain. A signal crossing a box edge may be experience a greater delay than a signal entirely within a box.
A signal arriving at input 0 may be output through output 4 with less delay than routing the signal to output 0, and even less delay than to send the input signal to outputs 1, 2 or 3. Inputs 1 and 3 may be routed either outputs 1 or 3 with an equal delay, but to outputs 0, 2 or 4 with a higher delay.
When using local switching near the I/O pads, for example, the multiplexers shown for the direct routing of input line 0 to output line 4, the central switch shown connecting all inputs to all outputs may retain full switch in functionality, or a subset thereof. For example, the central switch might omit the capability to route input line 0 to output line 4, as that capability would be redundant with the switching function near the I/O pad. This is similar to the arrangement shown in
The description herein has used modules, which may be connectorized, a mother board, and the like as examples. However the apparatus and method may be used in conjunction with devices mounted on a substrate, as integrated circuits, as multi-chip modules, or the like. As the density of electronic modules continues to increase, such construction may be convenient to use.
Although the present invention has been explained by way of the examples described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the examples, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention.
|Patente citada||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US3728679 *||21 Oct 1971||17 Abr 1973||Weston Instruments Inc||Skew device|
|US3970798||21 Abr 1975||20 Jul 1976||International Business Machines Corporation||Time division multiplex data transmission system|
|US4128882||19 Ago 1976||5 Dic 1978||Massachusetts Institute Of Technology||Packet memory system with hierarchical structure|
|US4240143||22 Dic 1978||16 Dic 1980||Burroughs Corporation||Hierarchical multi-processor network for memory sharing|
|US4263651 *||21 May 1979||21 Abr 1981||International Business Machines Corporation||Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks|
|US4322849||14 Abr 1980||30 Mar 1982||Calabrese Frank A||Data relay system|
|US4323849||11 Ene 1980||6 Abr 1982||Hybricon, Inc.||Coulometer|
|US4363094||4 Jun 1980||7 Dic 1982||M/A-COM DDC, Inc.||Communications processor|
|US4383314||12 Ene 1981||10 May 1983||Burroughs Corporation||Circular access linkage loop configuration for system communication|
|US4386323||23 Ene 1981||31 May 1983||U.S. Philips Corporation||Arrangement for synchronizing the phase of a local clock signal with an input signal|
|US4543630||19 Abr 1984||24 Sep 1985||Teradata Corporation||Data processing systems and methods|
|US4558455||23 Sep 1983||10 Dic 1985||International Business Machines Corporation||Data transmission system|
|US4701756||10 Sep 1985||20 Oct 1987||Burr William E||Fault-tolerant hierarchical network|
|US4703451||6 Ago 1986||27 Oct 1987||Calabrese Frank A||Data relay system|
|US4756011||24 Dic 1986||5 Jul 1988||Bell Communications Research, Inc.||Digital phase aligner|
|US4805195 *||10 Dic 1986||14 Feb 1989||Amdahl Corporation||Selectable timing delay circuit|
|US4820944 *||28 Oct 1986||11 Abr 1989||Schlumberger Systems & Services, Inc.||Method and apparatus for dynamically controlling the timing of signals in automatic test systems|
|US4845709||13 May 1987||4 Jul 1989||Mitsubishi Denki K.K.||Data transfer control system|
|US4860201||2 Sep 1986||22 Ago 1989||The Trustees Of Columbia University In The City Of New York||Binary tree parallel processor|
|US4881165||1 Abr 1988||14 Nov 1989||Digital Equipment Corporation||Method and apparatus for high speed data transmission between two systems operating under the same clock with unknown and non constant skew in the clock between the two systems|
|US4910669||3 Abr 1987||20 Mar 1990||At&T Bell Laboratories||Binary tree multiprocessor|
|US4922409||22 Oct 1987||1 May 1990||Bull S.A.||Bus control device comprising a plurality of isolatable segments|
|US5041964||28 Sep 1989||20 Ago 1991||Grid Systems Corporation||Low-power, standby mode computer|
|US5053942||1 Nov 1988||1 Oct 1991||The Regents Of The University Of California||Bit-sliced cross-connect chip having a tree topology of arbitration cells for connecting memory modules to processors in a multiprocessor system|
|US5175640 *||25 Abr 1990||29 Dic 1992||At&T Bell Laboratories||Interleaved receivers|
|US5200746 *||5 Ago 1991||6 Abr 1993||Nec Corporation||Switching module for digital cross-connect systems|
|US5283877||17 Jul 1990||1 Feb 1994||Sun Microsystems, Inc.||Single in-line DRAM memory module including a memory controller and cross bar switches|
|US5285441 *||17 Mar 1992||8 Feb 1994||At&T Bell Laboratories||Errorless line protection switching in asynchronous transer mode (ATM) communications systems|
|US5313501 *||15 Jun 1992||17 May 1994||Digital Equipment Corporation||Method and apparatus for deskewing digital data|
|US5365487||24 Mar 1992||15 Nov 1994||Texas Instruments Incorporated||DRAM power management with self-refresh|
|US5379262||1 Jul 1993||3 Ene 1995||Kabushiki Kaisha Toshiba||Nonvolatile semiconductor memory device|
|US5467040||28 Jul 1993||14 Nov 1995||Cray Research, Inc.||Method for adjusting clock skew|
|US5507029 *||11 Ene 1995||9 Abr 1996||International Business Machines Corporation||Method for minimizing the time skew of electrical signals in very large scale integrated circuits|
|US5513377 *||17 Jun 1994||30 Abr 1996||International Business Machines Corporation||Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus|
|US5621774 *||28 Nov 1994||15 Abr 1997||Hitachi, Ltd.||Method and apparatus for synchronizing parallel data transfer|
|US5828253||25 Mar 1997||27 Oct 1998||Nec Corporation||Phase synchronization system which reduces power consumption and high frequency noise|
|US5872959 *||10 Sep 1996||16 Feb 1999||Lsi Logic Corporation||Method and apparatus for parallel high speed data transfer|
|US5889714||3 Nov 1997||30 Mar 1999||Digital Equipment Corporation||Adaptive precharge management for synchronous DRAM|
|US5920704 *||17 Sep 1992||6 Jul 1999||International Business Machines Corporation||Dynamic routing switch apparatus with clocked signal regeneration|
|US5923830||7 May 1997||13 Jul 1999||General Dynamics Information Systems, Inc.||Non-interrupting power control for fault tolerant computer systems|
|US5960034||1 Dic 1995||28 Sep 1999||Advanced Micro Devices, Inc.||Expandable repeater with built-in tree structure arbitration logic|
|US5974503||5 May 1997||26 Oct 1999||Emc Corporation||Storage and access of continuous media files indexed as lists of raid stripe sets associated with file names|
|US6009547||3 Dic 1997||28 Dic 1999||International Business Machines Corporation||ECC in memory arrays having subsequent insertion of content|
|US6031847 *||1 Jul 1997||29 Feb 2000||Silicon Graphics, Inc||Method and system for deskewing parallel bus channels|
|US6105144 *||2 Mar 1998||15 Ago 2000||International Business Machines Corporation||System and method for alleviating skew in a bus|
|US6134167||4 Jun 1998||17 Oct 2000||Compaq Computer Corporation||Reducing power consumption in computer memory|
|US6138185 *||29 Oct 1998||24 Oct 2000||Mcdata Corporation||High performance crossbar switch|
|US6157229 *||25 Sep 1998||5 Dic 2000||Matsushita Electric Industrial Co., Ltd.||Skew compensation device|
|US6185654||17 Jul 1998||6 Feb 2001||Compaq Computer Corporation||Phantom resource memory address mapping system|
|US6208667 *||18 May 1999||27 Mar 2001||Fujitsu Network Communications||Constant phase crossbar switch|
|US6237052||1 Oct 1999||22 May 2001||Netcell Corporation||On-the-fly redundancy operation for forming redundant drive data and reconstructing missing data as data transferred between buffer memory and disk drives during write and read operation respectively|
|US6301244 *||11 Dic 1998||9 Oct 2001||Nortel Networks Limited||QoS-oriented one-to-all route selection method for communication networks|
|US6310814||8 Ago 2000||30 Oct 2001||Rambus, Inc.||Rambus DRAM (RDRAM) apparatus and method for performing refresh operations|
|US6317352||18 Sep 2000||13 Nov 2001||Intel Corporation||Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules|
|US6334167||31 Ago 1998||25 Dic 2001||International Business Machines Corporation||System and method for memory self-timed refresh for reduced power consumption|
|US6335647 *||23 Mar 2001||1 Ene 2002||Mitsubishi Denki Kabushiki Kaisha||Skew adjusting circuit|
|US6335930 *||26 May 1998||1 Ene 2002||Samsung Electronics Co., Ltd.||Multi-stage interconnection network for high speed packet switching|
|US6345321||24 May 2000||5 Feb 2002||Busless Computers Sarl||Multiple-mode memory component|
|US6356610||23 Jun 1998||12 Mar 2002||Vlsi Technology, Inc.||System to avoid unstable data transfer between digital systems|
|US6359815 *||12 Mar 1998||19 Mar 2002||Hitachi, Ltd.||Data transmitter|
|US6369605||18 Sep 2000||9 Abr 2002||Intel Corporation||Self-terminated driver to prevent signal reflections of transmissions between electronic devices|
|US6370200 *||3 Ago 1998||9 Abr 2002||Matsushita Electric Industrial Co., Ltd.||Delay adjusting device and method for plural transmission lines|
|US6417713 *||30 Dic 1999||9 Jul 2002||Silicon Graphics, Inc.||Programmable differential delay circuit with fine delay adjustment|
|US6425114 *||31 Ene 2000||23 Jul 2002||Lsi Logic Corporation||Systematic skew reduction through buffer resizing|
|US6442644||10 Ago 1998||27 Ago 2002||Advanced Memory International, Inc.||Memory system having synchronous-link DRAM (SLDRAM) devices and controller|
|US6445719||27 Ago 1999||3 Sep 2002||Adtran Inc.||Method, system and apparatus for reducing synchronization and resynchronization times for systems with pulse stuffing|
|US6446174||11 Jul 2000||3 Sep 2002||Intel Corporation||Computer system with dram bus|
|US6449667||16 Jul 1999||10 Sep 2002||T. M. Patents, L.P.||Tree network including arrangement for establishing sub-tree having a logical root below the network's physical root|
|US6473827 *||22 Dic 1998||29 Oct 2002||Ncr Corporation||Distributed multi-fabric interconnect|
|US6493205||25 Abr 2001||10 Dic 2002||Institute Franco-Allemand De Recherches De Saint-Louis||Process for polarizing a ferroelectric material in the shape of a cylinder|
|US6493250||28 Dic 2000||10 Dic 2002||Intel Corporation||Multi-tier point-to-point buffered memory interface|
|US6502161||5 Ene 2000||31 Dic 2002||Rambus Inc.||Memory system including a point-to-point linked memory subsystem|
|US6518812 *||20 Jul 2000||11 Feb 2003||Silicon Graphics, Inc.||Discrete delay line system and method|
|US6553450||18 Sep 2000||22 Abr 2003||Intel Corporation||Buffer to multiply memory interface|
|US6557110 *||9 Nov 2001||29 Abr 2003||Nippon Telegraph And Telephone Corporation||Channel-to-channel skew compensation apparatus|
|US6591339||8 Sep 1999||8 Jul 2003||3Ware, Inc.||Methods and systems for selecting block sizes for use with disk arrays|
|US6611518 *||18 Sep 1998||26 Ago 2003||Samsung Electronics Co., Ltd.||Methods and apparatus for flexible device interface port assignment in a data communications switching system|
|US6625687||18 Sep 2000||23 Sep 2003||Intel Corporation||Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing|
|US6636932 *||27 May 1999||21 Oct 2003||Micron Technology, Inc.||Crossbar switch and control for data networks switching|
|US6636993 *||12 Feb 1999||21 Oct 2003||Fujitsu Limited||System and method for automatic deskew across a high speed, parallel interconnection|
|US6647027 *||10 Nov 1999||11 Nov 2003||Lsi Logic Corporation||Method and apparatus for multi-channel data delay equalization|
|US6658509||3 Oct 2000||2 Dic 2003||Intel Corporation||Multi-tier point-to-point ring memory interface|
|US6667927||1 May 2002||23 Dic 2003||United Memories, Inc.||Refresh initiated precharge technique for dynamic random access memory arrays using look-ahead refresh|
|US6678783 *||1 Dic 2000||13 Ene 2004||Sony Corporation||Inter-device coupler|
|US6681338||21 Jun 2000||20 Ene 2004||Rambus, Inc.||Method and system for reducing signal skew by switching between multiple signal routing layers|
|US6697974 *||14 Mar 2001||24 Feb 2004||International Business Machines Corporation||Method and apparatus for adaptively compensating skews during data transmission on a bus|
|US6735397 *||14 Mar 2001||11 May 2004||Blaze Network Products, Inc.||Skew discovery and compensation for WDM fiber communications systems using 8b10b encoding|
|US6799235||2 Ene 2002||28 Sep 2004||Intel Corporation||Daisy chain latency reduction|
|US6803872 *||9 May 2002||12 Oct 2004||Silicon Graphics, Inc.||Programmable differential delay circuit with fine delay adjustment|
|US6807377 *||5 Ago 1998||19 Oct 2004||Fujitsu Limited||Parallel optical transmission/reception module|
|US6833618||28 Sep 2001||21 Dic 2004||Renesas Technology Corp.||Memory system with a socket having socket pins for mounting memory modules|
|US6871253||29 Jun 2001||22 Mar 2005||Micron Technology, Inc.||Data transmission circuit for memory subsystem, has switching circuit that selectively connects or disconnects two data bus segments to respectively enable data transmission or I/O circuit connection|
|US6874097 *||1 Jun 2001||29 Mar 2005||Maxtor Corporation||Timing skew compensation technique for parallel data channels|
|US6882082||13 Mar 2001||19 Abr 2005||Micron Technology, Inc.||Memory repeater|
|US6898742 *||19 Nov 2002||24 May 2005||Fujitsu Limited||System and method for automatic deskew across a high speed, parallel interconnection|
|US6904050||9 Dic 2002||7 Jun 2005||Interdigital Technology Corporation||User equipment with binary-tree multiplexing scheduling|
|US6928571||15 Sep 2000||9 Ago 2005||Intel Corporation||Digital system of adjusting delays on circuit boards|
|US6937681 *||14 Mar 2001||30 Ago 2005||Fujitsu Limited||Skew correction apparatus|
|US6961347||20 Jun 2000||1 Nov 2005||Hewlett-Packard Development Company, L.P.||High-speed interconnection link having automated lane reordering|
|US6983354||24 May 2002||3 Ene 2006||Micron Technology, Inc.||Memory device sequencer and method supporting multiple memory device clock speeds|
|US6998892 *||13 Feb 2002||14 Feb 2006||Rambus Inc.||Method and apparatus for accommodating delay variations among multiple signals|
|US7012811||10 May 2000||14 Mar 2006||Micron Technology, Inc.||Method of tuning a multi-path circuit|
|US7013361 *||12 Oct 2001||14 Mar 2006||Grass Valley Group Inc.||Routing switcher with variable input/output architecture|
|US7064992||5 May 2005||20 Jun 2006||Micron Technology, Inc.||Method and apparatus for saving current in a memory device|
|US7065101||15 Nov 2001||20 Jun 2006||International Business Machines Corporation||Modification of bus protocol packet for serial data synchronization|
|US7085950 *||28 Sep 2001||1 Ago 2006||Koninklijke Philips Electronics N.V.||Parallel data communication realignment of data sent in multiple groups|
|US7113012 *||20 Dic 2001||26 Sep 2006||Bhavik Amin||Skew delay compensator|
|US7123660 *||27 Feb 2002||17 Oct 2006||Jazio, Inc.||Method and system for deskewing parallel bus channels to increase data transfer rates|
|US7130317 *||19 Nov 2001||31 Oct 2006||Annadurai Andy P||Method and circuit for de-skewing data in a communication system|
|US7139347 *||30 Oct 2001||21 Nov 2006||Fujitsu Limited||Parallel signal automatic phase adjusting circuit|
|US7193429 *||29 Ene 2004||20 Mar 2007||Kabushiki Kaisha Toshiba||Serial data communication system having plurality of data transmission paths|
|US7200790||8 Jul 2003||3 Abr 2007||Sun Microsystems, Inc.||Switch level reliable transmission|
|US7205803 *||29 Jun 2004||17 Abr 2007||Lsi Logic Corporation||High speed fully scaleable, programmable and linear digital delay circuit|
|US7280538 *||15 Jun 2001||9 Oct 2007||Industrial Technology Research Institute||Multicast concentrators|
|US7304520 *||17 Ene 2006||4 Dic 2007||Samsung Electronics Co., Ltd.||Delay circuit and semiconductor device including same|
|US7328362 *||12 Dic 2006||5 Feb 2008||Broadcom Corporation||Method and apparatus for selectively deskewing data traveling through a bus|
|US7401246 *||30 Jun 2005||15 Jul 2008||Intel Corporation||Nibble de-skew method, apparatus, and system|
|US7430728 *||10 Ago 2005||30 Sep 2008||Xilinx, Inc.||Method and apparatus for selecting programmable interconnects to reduce clock skew|
|US7433441 *||17 Abr 2006||7 Oct 2008||Silicon Graphics, Inc.||System and method for adaptively deskewing parallel data signals relative to a clock|
|US7490189 *||14 Jun 2006||10 Feb 2009||Sun Microsystems, Inc.||Multi-chip switch based on proximity communication|
|US7525356 *||14 Sep 2006||28 Abr 2009||Lsi Corporation||Low-power, programmable multi-stage delay cell|
|US7551640||20 Sep 2002||23 Jun 2009||Cisco Technology, Inc.||Method and apparatus for errorless frame timing adjustment|
|US7609695 *||27 Oct 2009||Industrial Technology Research Institute||Optimizing switching element for minimal latency|
|US7643517 *||30 Ago 2006||5 Ene 2010||Annadurai Andy P||Method and circuit for de-skewing data in a communication system|
|US7653776 *||14 Dic 2005||26 Ene 2010||Apple Inc.||Method and apparatus for selectively switching IC ports to card slots through the use of three switches per switch group|
|US7668271||30 Sep 2003||23 Feb 2010||Rambus Inc.||Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency data|
|US7668272||23 Feb 2010||National Semiconductor Corporation||Method and apparatus for data transfer between mesochronous clock domains|
|US7751713 *||23 Jul 2007||6 Jul 2010||Infinera Corporation||Communication network with skew path monitoring and adjustment|
|US7817767||19 Oct 2010||Rambus Inc.||Processor-controlled clock-data recovery|
|US20010039601||10 Jul 2001||8 Nov 2001||Leung Wing Yu||Memory with large number of memory modules|
|US20020009169 *||14 Mar 2001||24 Ene 2002||Takayuki Watanabe||Skew correction apparatus|
|US20020084458||28 Dic 2000||4 Jul 2002||Halbert John B.||Multi-tier point-to-point buffered memory interface|
|US20020112119||13 Mar 2002||15 Ago 2002||Intel Corporation||Dual-port buffer-to-memory interface|
|US20020124153||20 Dic 2001||5 Sep 2002||Daniel Litaize||Memory component with multiple transfer formats|
|US20030001880||1 Ago 2002||2 Ene 2003||Parkervision, Inc.||Method, system, and computer program product for producing and distributing enhanced media|
|US20030018880||7 Ago 2002||23 Ene 2003||Daniel Litaize||Multiple-mode memory system|
|US20030019327||26 Jul 2002||30 Ene 2003||Hiroshi Fujimoto||Ultrafine particles and method and apparatus for producing the same|
|US20030046489||15 Feb 2002||6 Mar 2003||Hitachi, Ltd.||Disk memory device|
|US20030058021||30 Ene 2002||27 Mar 2003||Chih-Sheng Lee||Power-off protection device|
|US20030061447||15 Oct 2002||27 Mar 2003||Perego Richard E.||Memory system including a point-to-point linked memory subsystem|
|US20030095575 *||19 Nov 2001||22 May 2003||Syntera Corporation||Method and circuit for de-skewing data in a communication system|
|US20030105928||4 Dic 2001||5 Jun 2003||International Business Machines Corporation||Method, system, and program for destaging data in cache|
|US20030117172||21 Dic 2001||26 Jun 2003||Wu Chung-Hsiao R.||Bi-directional output buffer|
|US20030120895||10 Feb 2003||26 Jun 2003||Daniel Litaize||Memory controller for synchronous burst transfers|
|US20030163606||20 Jun 2001||28 Ago 2003||Mueo Fukaishi||High-speed memory system|
|US20030193927||10 Abr 2002||16 Oct 2003||Stanley Hronik||Random access memory architecture and serial interface with continuous packet handling capability|
|US20030208511||30 Abr 2003||6 Nov 2003||Earl Leroy D.||Database replication system|
|US20030236939||16 May 2003||25 Dic 2003||Bendik Kleveland||High-speed chip-to-chip communication interface|
|US20040004897||15 May 2003||8 Ene 2004||Kyung-Woo Kang||Layout structures of data input/output pads and peripheral circuits of integrated circuit memory devices|
|US20040117569||21 Ene 2003||17 Jun 2004||Kye-Hyun Kyung||Memory system having two-way ring topology and memory device and memory module for ring-topology memory system|
|US20040122985||6 Oct 2003||24 Jun 2004||Nec Infrontia Corporation||Communication device using a plurality of communication interfaces, and wireless LAN access point|
|US20040153817||29 Jul 2003||5 Ago 2004||Micron Technologies, Inc.||Apparatus and method for detecting over-programming condition in multistate memory device|
|US20040230718||10 May 2004||18 Nov 2004||Advanced Micro Devices, Inc.||System including a host connected to a plurality of memory modules via a serial memory interconnet|
|US20040243769||30 May 2003||2 Dic 2004||Frame David W.||Tree based memory structure|
|US20040256638||18 May 2004||23 Dic 2004||Richard Perego||Configurable width buffered module having a bypass circuit|
|US20050005184||24 Mar 2004||6 Ene 2005||Lindt Paul Georg||Method for measuring and compensating skews of data transmission lines|
|US20050007805||13 Jul 2004||13 Ene 2005||Fred Ware||Configurable width buffered module having flyby elements|
|US20050010737||13 Jul 2004||13 Ene 2005||Fred Ware||Configurable width buffered module having splitter elements|
|US20050060483||24 Nov 2003||17 Mar 2005||Kabushiki Kaisha Toshiba||Microprocessor and video/sound processing system|
|US20050071693||26 Sep 2003||31 Mar 2005||Chun Christopher K. Y.||Method and circuitry for controlling supply voltage in a data processing system|
|US20050078506||8 Oct 2004||14 Abr 2005||Ocz Technology||Posted precharge and multiple open-page ram architecture|
|US20050086549||15 Oct 2003||21 Abr 2005||Solomon Gary A.||Power management over switching fabrics|
|US20050246362||3 May 2004||3 Nov 2005||Borland Devin P||System and method for dynamci log compression in a file system|
|US20050259692||19 May 2004||24 Nov 2005||Zerbe Jared L||Crosstalk minimization in serial link systems|
|US20060136767||5 Ene 2006||22 Jun 2006||Kenneth Ma||Method and apparatus for adaptive power management of memory|
|US20060143372||27 Abr 2005||29 Jun 2006||Walker Robert M||Directed auto-refresh synchronization|
|US20060179334||9 Feb 2005||10 Ago 2006||International Business Machines Corporation||Dynamic power management via DIMM read operation limiter|
|US20060187715||20 Ene 2006||24 Ago 2006||Raza Microelectronics, Inc.||System and method for performing concatentation of diversely routed channels|
|US20060253721||9 May 2005||9 Nov 2006||Micron Technology, Inc.||Adjustable byte lane offset for memory module to reduce skew|
|US20060277310 *||1 Jun 2005||7 Dic 2006||Kalos Matthew J||Apparatus, system, and method for accessing a preferred path through a storage controller|
|US20060288241||16 Jun 2005||21 Dic 2006||Felter Wesley M||Performance conserving method for reducing power consumption in a server system|
|US20070002663||7 Sep 2006||4 Ene 2007||Micron Technology, Inc.||Power savings in active standby mode|
|US20070079219||14 Sep 2006||5 Abr 2007||Takeshi Nagai||Semiconductor memory device having data holding mode using ecc function|
|US20070088754||17 Oct 2005||19 Abr 2007||International Business Machines Corporation||Method and system to guarantee data and metadata referential integrity in content management archival solutions|
|US20070101075||28 Nov 2006||3 May 2007||Jeddeloh Joseph M||Out of order DRAM sequencer|
|US20070113029||14 Nov 2005||17 May 2007||Sandisk Corporation||Structures for the management of erase operations in non-volatile memories|
|US20070124532||17 Abr 2006||31 May 2007||Bennett Jon C||Interconnection system|
|US20070162516||30 Dic 2005||12 Jul 2007||Microsoft Corporation||Computing asynchronous transaction log replication progress based on file change notifications|
|US20080168304||6 Dic 2007||10 Jul 2008||David Flynn||Apparatus, system, and method for data storage using progressive raid|
|US20080175586 *||12 Oct 2007||24 Jul 2008||Perkins Drew D||Communication Network with Skew Compensation|
|US20080175589 *||17 Sep 2007||24 Jul 2008||Perkins Drew D||Communication Network with Skew Determination|
|US20080183953||6 Dic 2007||31 Jul 2008||David Flynn||Apparatus, system, and method for storage space recovery in solid-state storage|
|US20090052892 *||6 Sep 2007||26 Feb 2009||Perkins Drew D||Communication Network with Co-Routed Multi-Channel Traffic|
|US20090324220 *||31 Dic 2009||Infinera Corporation||Communication network with node bypassed co-routed multi-channel traffic|
|EP1369767A2||4 Jun 2003||10 Dic 2003||Broadcom Corporation||Method and apparatus for adaptive power management of memory|
|1||"A Graph for Interconnecting Processors in Parallel Computing", by Hong Xie; Murdock University, Murdoch, W.A, 6150 Australia; Proc. ICCI'94, p. 885-901; 1994 Int. Conf. on Computing and Information.|
|2||"A High-Speed Channel Controller for the Chaos Router", by Robert Wille; p. 1-21; Dec. 8, 1992.|
|3||"Communication in X-Tree, a Modular Multiprocessor System", by C.H. Sequin, A.M.Despain, D.A. Patterson; University of California, Computer Science Division, Electrical Engineering & Computer Sciences; Berkeley, CA, p. 194-203; 1978.|
|4||"Cycletrees: Flexible Interconnection Graphs for Parallel Computing", by Margus Veanes & Jonas Barklund, 36 p., UPMAIL Technical Report No. 97, Uppsala, Sweden, Feb. 21, 1995.|
|5||"Mainstream Computer Components," Lec #10 Spring 2006 May 8, 2006, pp. 1-31.|
|6||"Performance Evaluation of Switch-Based Wormhole Networks", by Lionel M. Ni, Yadong Gui, Sherry Moore; 1045-9219/97-1997 IEEE; p. 462-474.|
|7||"Performance Evaluation of Switch-Based Wormhole Networks", by Lionel M. Ni, Yadong Gui, Sherry Moore; 1045-9219/97—1997 IEEE; p. 462-474.|
|8||"The Alewife CMMU: Addressing the Multiprocessor Communications Gap", by J. Kubiatowicz, D. Chaiken, A. Agarwal; Massachusetts Institute of Technology, Laboratory for Computer Science, Cambridge, MA; p. 1-3.|
|9||"X-Tree: A Tree Structured Multi-Proce3ssor Computer Architecture", by Alvin M. Despain and David A. Patterson; University of California/Computer Science Division, Berkeley, CA, p. 144-151.|
|10||AbouGhazeleh, N., et al., "Energy Conservation in Memory Hierarchies using Power-Aware Cashed-DRAM," Department of Computer Science, University of Pittsburgh, Technical Report: TR-05-123, pp. 1-23.|
|11||Argument and Amendment filed on Mar. 21, 2011 in the Korean Intellectual Property Office (KIPO) for Korean Patent Application No. 10-2009-7008236, 9 pages.|
|12||Bhalodia, V., "Scale DRAM Subsystem Power Analysis," Massachusetts Institute of Technology, Sep. 2005, pp. 1-51.|
|13||*||Chakraborty et al. Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers. ACM. 2006.|
|14||Despaux, O., "DDR SDRAM Controller Using Virtex-4 FPGA Devices," © 2004 Xilinx, Inc., XAPP709 (v1.0) Sep. 10, 2004, pp. 1-9.|
|15||Elpida, "Low Power Function of Mobile RAM(TM) Deep Power Down (DPD)," Elpida Memory, Inc. 2005-2006, Date Published May 2006 (K) Japan, URL: http://www.elpida.com, pp. 1-4.|
|16||Elpida, "Low Power Function of Mobile RAM™ Deep Power Down (DPD)," Elpida Memory, Inc. 2005-2006, Date Published May 2006 (K) Japan, URL: http://www.elpida.com, pp. 1-4.|
|17||Elpida, ‘Low Power Function of Mobile RAMTM Deep Power Down (DPD),’ Elpida Memory, Inc. 2005-2006, Date Published May 2006 (K) Japan, URL: http:// www.elpida.com, pp. 1-4.|
|18||Elpida, 'Low Power Function of Mobile RAMTM Deep Power Down (DPD),' Elpida Memory, Inc. 2005-2006, Date Published May 2006 (K) Japan, URL: http:// www.elpida.com, pp. 1-4.|
|19||European Patent Office Communication from EPO application No. 07 861 460.9-2212 dated Mar. 23, 2010 (3 pages).|
|20||European Patent Office Communication from EPO application No. 07 861 460.9-2212 dated Oct. 15, 2010 (5 pages).|
|21||European Search Report from EPO application No. 08836238.92212/2201463 dated Sep. 14, 2010 (7 pages).|
|22||Fan, X., et al., "Memory Controller Policies for DRAM Power Management," ISPLED'01, Aug. 6-7, 2001, Huntington Beach, California, USA, Copyright 2001 ACM 1-58113-371-5/01/0008, 6 pages.|
|23||Fan, X., et al., "Modeling of DRAM Power Control Policies Using Deterministic and Stochastic Petri Nets," Department of Computer Science, Duke University, Durham, NC 27708, USA, 11 pages.|
|24||Feb. 23, 2010 Non-Final Office Action, U.S. Appl. No. 11/405,083 (19 pages).|
|25||Graefe, G., "Write-Optimized B-Trees," Proceedings of the 30th VLDB Conference, Toronto, Canada, 2004, pp. 672-683.|
|26||Hans-Peter Messer: "PC-Hardwarebuch" 1995, Addison-Wesley, Bonn XP002412835 pp. 31-36, pp. 580-583.|
|27||Hans-Peter Messer: "PC—Hardwarebuch" 1995, Addison-Wesley, Bonn XP002412835 pp. 31-36, pp. 580-583.|
|28||*||Hu et al. Inter-Signal Timing Skew Compensation of Parallel Links with Voltage-Mode Incremental Signaling. IEEE. 2008.|
|29||Intel®, "Understanding the Flash Translation Layer (FTL) Specification," Dec. 1998, Order No. 297816-002, Copyright © Intel Corporation 1997, 1998, pp. 1-20.|
|30||International Search Report for International Application No. PCT US2007/022316, dated Mar. 28, 2008, 3 pages.|
|31||International Search Report for International Application No. PCT/US2007/022316, dated Mar. 28, 2008, 3 pages.|
|32||International Search Report for International Application No. PCT/US2008/074628, dated Mar. 24, 2009, 3 pages.|
|33||International Search Report for International Application No. PCT/US2008/078752, dated Mar. 31, 2009, 3 pages.|
|34||International Search Report for International Application No. PCT/US2008/083969, dated Apr. 30, 2009, 3 pages.|
|35||International Search Report from PCT application No. PCT US2006/014527 dated Apr. 10, 2007 (7 pages).|
|36||International Search Report from PCT application No. PCT/US2006/014527 dated Apr. 10, 2007 (7 pages).|
|37||Jan. 21, 2011 Non-Final Office Action, U.S. Appl. No. 12/245,349 (20 pages).|
|38||Jeffery, C.A., "Performance Analysis of Dynamic Sparing and Error Correction Techniques for Fault Tolerance in Nanoscale Memory Structures," Thesis Presentation to the University of Florida, 2004, 104 pages.|
|39||Jul. 21, 2009 Non-Final Office Action, U.S. Appl. No. 11/405,083.|
|40||Jul. 21, 2010 Final Office Action, U.S. Appl. No. 11/405,083 (20 pages).|
|41||Juonolainen, M. K., "Cand Scient Thesis," University of Oslo, Jan. 2, 1999, 129 pages.|
|42||*||Lee et al. Inter-Pin Skew Compensation Scheme for 3.2-Gb/s/pin Parallel Interface. Journal of Semiconductor Technology and Science. vol. 10. No. 1. Mar. 2010.|
|43||Mar. 14, 2011 Response to European Patent Office Communication from EPO application No. 07 861 460.9-2212 dated Oct. 15, 2010 (13 pages).|
|44||May 28, 2010 Response to European Patent Office Communication from EPO application No. 07 861460.9-2212 dated Mar. 23, 2010 (17 pages).|
|45||Micron, "Calculating Memory System Power for DDR," © 2001 Micron Technology, Inc., pp. 1-26.|
|46||Micron, "DDR2 (Point-to-Point) Features and Functionality," © 2003 Micron Technology, Inc., pp. 1-14.|
|47||Micron, "DDR2 tCKE Power-Down Requirement," © 2003 Micron Technology, Inc., pp. 1-3.|
|48||Micron, "Designing for High-Density DDR2 Memory," © 2005 Micron Technology, Inc., pp. 1-9.|
|49||Micron, "Mobile DRAM Power-Saving Features and Power Calculations," © 2005 Micron Technology, Inc., pp. 1-9.|
|50||Micron, "Mobile SDRAM Power-Saving Features," © 2002 Micron Technology, Inc., pp. 1-3.|
|51||Norvag, K., et al., "Log-Only Temporal Object Storage," Copyright 1997 IEEE, published in the Proceedings of DEXA'97, Sep. 1-2, 1997, Toulouse, France, 6 pages.|
|52||Notice of Preliminary Rejection dated Jan. 24, 2011 from the Korean Intellectual Property Office (KIPO) for Korean Patent Application No. 10-2009-7008236, 2 pages.|
|53||Notification of the First Office Action dated Dec. 26, 2008 from the Patent Office of People's Republic of China for Chinese Patent Application No. 2006800130653, 7 pages.|
|54||Park, J., et al., "Coarse-Grained DRAM Power Management," Department of Computer Science, Department of Electrical Engineering and Computer Engineering, State University of New York at New Paltz, New Paltz., NY 12561, U.S.A., 7 pages.|
|55||Pharris, B., "The SCALE DRAM Subsystem," Massachusetts Institute of Technology, May 2004, pp. 1-79.|
|56||Rajamani, K., et al., "Evaluating Power Management Strategies for High Performance Memory (DRAM): A Case Study for Achieving Effective Analysis by Combining Simulation Platforms and Real Hardware Performance Monitoring," IBM Austin Research Lab, 10 pages.|
|57||Response to Feb. 23, 2010 Non-Final Office Action, U.S. Appl. No. 11/405,083, filed in the PTO on May 12, 2010 (30 pages).|
|58||Response to Jul. 21, 2009 Non-Final Office Action, U.S. Appl. No. 11/405,083, filed in the PTO on Oct. 7, 2009.|
|59||Response to Jul. 21, 2010 Non-Final Office Action, U.S. Appl. No. 11/405,083, filed in the PTO on Nov. 17, 2010 (16 pages).|
|60||Response to May 19, 2010 Non-Final Office Action, U.S. Appl. No. 11/975,269, filed in the PTO on Nov. 9, 2010, 7 pages.|
|61||Sanders, D.A., et al., "Terabyte IDE RAID-5 Disk Arrays," 2003 Conference for Computing in High Energy and Nuclear Physics, LaJolla, California, Mar. 24-28, 2003, pp. 1-8.|
|62||Shirriff, K.W., "Sawmill: A Logging File System for a High-Performance RAID Disk Array," Dissertation Presentation, University of California, 1995, pp. 164.|
|63||US 6,832,284, 12/2004, Perego et al. (withdrawn)|
|64||Written Opinion of the International Searching Authority from the International Search Report from PCT application No. PCT/US2006/014527 dated Apr. 10, 2007 (9 pages).|
|65||Written Opinion of the International Searching Authority from the International Search Report from PCT application No. PCT/US2008/074628 dated Mar. 24, 2009, 5 pages.|
|66||Written Opinion of the International Searching Authority from the International Search Report from PCT application No. PCT/US2008/078752 dated Mar. 31, 2009, 5 pages.|
|67||Written Opinion of the International Searching Authority from the International Search Report from PCT application No. PCT/US2008/083969 dated Apr. 30, 2009, 5 pages.|
|Patente citante||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US9148345||16 Ene 2012||29 Sep 2015||Ciena Corporation||Link management systems and methods for multi-stage, high-speed systems|
|US9164534 *||18 Jul 2013||20 Oct 2015||Socionext Inc.||Circuit for skew reduction has swap circuit swapping and connecting first signal lines to second signal lines|
|US20140021998 *||18 Jul 2013||23 Ene 2014||Fujitsu Semiconductor Limited||Skew reduction circuit|
|Clasificación de EE.UU.||713/503, 710/38, 327/152, 327/149, 327/153, 327/270, 710/317, 714/700, 710/316, 327/271|
|Clasificación cooperativa||G11C5/06, G06F13/4243, H03K19/17736, H03K19/17764|
|Clasificación europea||G11C5/06, H03K19/177F, G06F13/42C3S, H03K19/177H4|
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