|Publication number||US7733855 B1|
|Application number||US 10/863,544|
|Publication date||Jun 8, 2010|
|Filing date||Jun 8, 2004|
|Priority date||Jun 8, 2004|
|Publication number||10863544, 863544, US 7733855 B1, US 7733855B1, US-B1-7733855, US7733855 B1, US7733855B1|
|Inventors||Ola Torudbaken, Bjorn Dag Johnsen|
|Original Assignee||Oracle America, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (75), Non-Patent Citations (7), Referenced by (4), Classifications (5), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present application is related to the following applications, all of which are filed on the same day and assigned to the same assignee as the present application:
“METHOD AND APPARATUS FOR VERIFYING SERVICE LEVEL IN A COMMUNICATIONS NETWORK” (application Ser. No. 10/863,019, filed 8 Jun. 2004), Inventors: Bjorn Dag Johnsen, Christopher Jackson, David Brean and Ola Torudbakken;
“SWITCH METHOD AND APPARATUS WITH CUT-THROUGH ROUTING FOR USE IN A COMMUNICATIONS NETWORK” (application Ser. No. 10/863,016, filed 8 Jun. 2004), Inventors: Bjorn Dag Johnsen, Hans Rygh and Morten Schanke;
“SWITCHING METHOD AND APPARATUS FOR USE IN A COMMUNICATIONS NETWORK” (U.S. patent application Ser. No. 10/862,970, filed 8 Jun. 2004), Inventors: Bjorn Dag Johnsen, Christopher Jackson, David Brean, Ola Torudbakken, Steinar Forsmo, Hans Rygh, Morten Schanke;
“METHOD AND APPARATUS FOR SOURCE AUTHENTICATION IN A COMMUNICATIONS NETWORK” (application Ser. No. 10/863,854, filed 8 Jun. 2004), Inventors: Bjorn Dag Johnsen, Christopher Jackson, David Brean, Ola Torudbakken;
“CREDIT ANNOUNCEMENT” (application Ser. No. 10/863,373, filed 8 Jun. 2004), Inventors: Morten Schanke, Hans Rygh, Marius Hansen and Mathias Hoddevik;
“ADAPTIVE CUT-THROUGH ALGORITHM” (application Ser. No. 10/862,987, filed 8 Jun. 2004), Inventors: Morten Schanke, Brian Manula and Magne Sandven;
“COMMA DETECTION” (application Ser. No. 10/863,374, filed 8 Jun. 2004), Inventors: Magne Sandven, Morten Schanke and Brian Manula;
“SERVICE LEVEL TO VIRTUAL LANE MAPPING” (application Ser. No. 10/862,985, filed 8 Jun. 2004), Inventors: Steinar Forsmo, Hans Rygh and Ola Torudbakken;
“INPUT AND OUTPUT BUFFERING” (application Ser. No. 10/863,038, filed 8 Jun. 2004), Inventors: Hans Rygh, Morten Schanke, Ola Torudbakken and Steinar Forsmo;
“CODEC IMPLEMENTATION FOR INFINIBAND” (application Ser. No. 10/863,439, filed 8 Jun. 2004), Inventors: Steinar Forsmo, Mathias Hoddevik and Magne Sandven;
“VCRC CHECKING AND GENERATION” (application Ser. No. 10/863,013, filed 8 Jun. 2004), Inventors: Steinar Forsmo, Hans Rygh, Morten Schanke and Ola Torudbakken;
“STUMPING MECHANISM” (application Ser. No. 10/863,372, filed 8 Jun. 2004), Inventors: Brian Manula, Ali Bozkaya and Magne Sandven.
The above-identified applications are all hereby incorporated by reference into the present application.
The present invention relates to service level to community separation enforcement, and in particular but not exclusively to CAM-based community separation enforcement within a network device such as an Infiniband switch.
Within networking technologies, the field of community separation is of ever increasing importance. Being able to prevent access to data belonging to one community by end-nodes not belonging to that community allows the use of a single network to carry data belonging to a multitude of different groups, each of which requires that their data be isolated from other network user groups. The effect to the end user being that the network appears to be their private domain which no-one outside the group can access. A lack of adequate community separation provisions can lead to data insecurities and under-utilisation network capabilities. Examples of community separation techniques include VLANs (Virtual-LANs) on IP based networks, Zones in FibreChannel networks, and Partitions in Infiniband.
The present invention has been made, at least in parts, in consideration of problems and drawbacks of conventional systems.
Viewed from a first aspect, the present invention provides an Infiniband device. The device can have an input port for receiving a data packet. The input port can have: a packet interrogator for extracting a group membership identifier from the packet; and a membership confirmation unit for comparing the extracted group membership identifier to a group membership table of the port to determine whether the packet breaches a group membership requirement. The group membership table can be implemented as a content addressable memory storing a plurality of programmable bit masks. This arrangement provides for management of many partitions within an Infiniband subnet or fabric, without a large cost of switching or routing components to manage the large number of partitions.
Particular and preferred aspects and embodiments of the invention are set out in the appended independent and dependent claims.
Specific embodiments of the present invention will now be described by way of example only with reference to the accompanying figures in which:
While the invention is susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are herein described in detail. It should be understood, however, that drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
One particular computer networking architecture is the Infiniband™ architecture. Infiniband™ is a standard architecture defined and administered by the Infiniband™ Trade Association, which was founded by Compaq, Dell, Hewlett-Packard, IBM, Intel, Microsoft and Sun Microsystems. The Infiniband™ Architecture defines a System Area Network (SAN) for connecting multiple independent processor platforms (i.e. host processor nodes), I/O platforms and I/O devices. A full definition of the Infiniband™ Architecture may be found in the Infiniband™ Architecture Specification Volumes 1 and 2, available from the Infiniband™ Trade Association. Infiniband™ defines a standard for flexible and high speed interconnect between computing systems or parts of computing system such as processor and I/O nodes. Infiniband™ allows an order of magnitude more flexibility and scalability than conventional bus based systems through a highly hardware coupled and low latency interface, which is a key factor in multiprocessing architectures.
The Infiniband™ Architecture SAN is a communications and management infrastructure supporting both I/O and interprocessor communications for one or more computer systems. An Infiniband™ Architecture system can range from a small server with one processor and a few I/O devices to a massively parallel supercomputer installation with hundreds of processors and thousands of I/O devices.
The Infiniband™ Architecture defines a switched communications fabric allowing many devices to concurrently communicate with high bandwidth and low latency in a protected, remotely managed environment. An endnode can communicate with over multiple Infiniband™ Architecture ports and can utilise multiple paths through the Infiniband™ Architecture fabric. A multiplicity of Infiniband™ Architecture ports and paths through the network are provided for both fault tolerance and increased data transfer bandwidth.
Infiniband™ Architecture hardware off-loads from the CPU much of the I/O communications operation. This allows multiple concurrent communications without the traditional overhead associated with communicating protocols. The Infiniband™ Architecture SAN provides its I/O and interprocessor communications clients zero processor-copy data transfers, with no kernel involvement, and uses hardware to provide highly reliable, fault tolerant communications.
An example of an Infiniband™ Architecture System Area Network is shown in
Each endnode 32 has therein a Channel Adapter, which may be a Host Channel Adapter (HCA) or a Target Channel Adapter (TCA). Host Channel Adapters are to be found in processor nodes 14, and Target Channel Adapters are to be found in I/O Nodes 16, 18, 20, 22 and 24. Host Channel Adapters are configured to issue requests across the fabric 12, and Target Channel Adapters are configured to respond to such requests, for example by supplying requested data or storing supplied data. Each Channel Adapter uses a queuing system based on Queue Pairs, one queue for send operations and one for receive operations. Each Queue Pair may therefore be considered to provide a virtual communication port of a Channel Adapter. Each Channel Adapter may have up to 224 Queue Pairs, which may be assigned individually or in combination to handle operations affecting different parts (or consumers) of the endnode 32. For example, a processor node 14 may comprise a plurality of processors and each processor may have one or more individual Queue Pairs assigned to handle requests and responses flowing to and from that processor of that processor node 14 via the fabric 12. Alternatively, or in addition, a processor of a given processor node 14 may be running more than one process and each process may have one or more Queue Pairs assigned to handle requests and responses flowing to and from that process via the fabric 12.
The interconnects 28 may be one of three classes, 1×, 4× or 12×, referring to the number of parallel lanes making up that interconnect. Each lane is a single serial connection over a single physical signal carrier path (whether electrical or optical). Thus the bandwidth available to each interconnect is defined by a combination of the number of lanes and the maximum data rate of the physical signal carrier making up each lane.
Examples of possible Infiniband™ Architecture topologies are shown in
Referring now to
The structure of a message to be transmitted through the fabric 12 via the interconnections 28 is illustrated in
The data packet format is illustrated in
The Link Layer describes the packet format and protocols for packet operation, e.g. flow control and how packets are routed within a subnet between the source and the destination. Packets may be data packets which convey data between endnodes and which consist of a number of different headers which may or may not be present. Alternatively packets may be Link Management Packets which are used to train and maintain link operation. These packets are used to negotiate operational parameters between the ports at each end of the link such as bit rate, link width etc. The link layer is responsible for flow control handling to prevent the loss of packets due to buffer overflow by the receiver at each end of a link. This mechanism does not describe end to end flow control such as might be utilised to prevent transmission of messages during periods when receive buffers are not posted. The terms “transmitter” and “receiver” are utilised to describe each end of a given link. The transmitter is the node sending data packets. The receiver is the consumer of the data packets. Each end of the link has a transmitter and a receiver. The Infiniband™ Architecture utilises an “absolute” credit based flow control scheme that is to say that Infiniband™ Architecture receivers provide a “credit limit”. A credit limit is an indication of the total amount of data that the transmitter has been authorised to send since link initialisation.
Credit control is performed by a media access control (MAC) protocol. With respect to a given link, a receiver advertises (by means of a link packet) that credit is available, the amount of which is based on the current status of the receiver's receive buffers. The transmitter receives the link packet and determines how much transmit credit is available from the contents of the link packet. The transmitter then assigns itself the available credit and transmits data packets to the receiver while simultaneously decrementing its available credit count. The transmitter calculates its remaining available credit based on the initial figure determined from the receiver link packet and a record of how much data it has transmitted since that link packet was received.
Errors in transmission, in data packets, or in the exchange of flow control information can result in inconsistencies in the flow control state perceived by the transmitter and receiver. The Infiniband™ Architecture flow control mechanism provides for recovery from this condition. The transmitter periodically sends an indication of the total amount of data that it has sent since link initialisation. The receiver uses this data to re-synchronise the state between the receiver and transmitter.
As can be seen in
The Network Layer, which is present only within routers 30 and endnodes 32, describes the protocol for routing a packet between subnets 13. Thus a Global Route Header (GRH) is present in a packet that traverses multiple subnets 13. The Global Route Header identifies the source and destination ports of the message. Routers 30 use the contents of the Global Route Header to determine the forwarding requirements of the message. As the message traverses different subnets 13 the routers 30 modify the content of the Global Route Header and replace the Local Route Header but the source and destination port identities are not changed and are protected by the Invariant Cyclic Redundancy Check. Thus the Network and Link Layers operate together to deliver a packet to the desired destination.
The Transport Layer, which is present only within endnodes 32, delivers the packet to the proper Queue Pair within the Channel Adapter of the destination endnode 32 and instructs that Queue Pair as to how the packet's data should be processed. The transport layer also has responsibility for segmenting an operation into multiple packets when the message's data payload is greater than the maximum payload carryable by a single packet. The receiving Queue Pair then reassembles the data from the multiple packets at the destination endnode 32. The transport layer adds up to two headers to the packet. The Base Transport Header (BTH) is present in all IBA Packets but not in RAW Packets. It identifies the destination Queue Pair and indicates an operation code, packet sequence number and specifies the operation (Send, Read, Write etc). A number of Extended Transport Headers (ETH) may be present conditional on the class of service and operation code.
The Packet Sequence Number is initialised for a given Queue Pair as part of the communications establishment process and increments each time that Queue Pair creates a new packet. The receiving Queue Pair tracks the received Packet Sequence Number to determine whether any packets have been lost. For reliable service, the receiver endnode 32 may transmit and acknowledge signal back to the originator endnode to indicate whether all packets have been received successfully.
The Upper Level Protocols are completely software based and may comprise any number of protocols used by various user consumers. The payload is the data carried by the packet and I Data is handling data associated with a work activity to be performed on the payload. Also present in the Upper Level protocols are Subnet Management and Subnet Services protocols. These protocols provide management structure including management messages for management of the subnet 13. Each subnet 13 requires only a single Subnet Manager application 34 which may be present in a dedicated node (as illustrated in
Examples of simple Infiniband™ Architecture systems are shown in
Thus there has now been described an overview of the Infiniband™ Architecture for computer networking with examples of how it may be put into practice. Further details may be found in the above referenced Infiniband™ Architecture Specification Volumes 1 and 2, available from the Infiniband™ Trade Association, the contents of which are hereby incorporated hereinto by reference.
The management interface 865 provides access to the switch 26 for one or more external control systems, and can be used to configure switch 26 as appropriate depending upon the circumstances. For example, the subnet management agent 866 can communicate with the subnet manager 34 (see
In the present example, switch 26 has nine ports 81, denoted in
In accordance with the Infiniband Architecture, each link 28 can be subdivided into a maximum of sixteen virtual lanes (VL) to provide logically separate channels that are multiplexed onto a single logical link. The first fifteen virtual lanes (denoted VL0 through VL14) support general purpose data communications, while the remaining virtual lane (denoted VL15) is used for special management purposes. (Note that virtual lane VL15 is not flow-controlled, and so should be considered as not reliable). An Infiniband switch must support at least two virtual lanes on each link (i.e. data lane VL0 and management lane VL15). In one example, switch 26 supports four virtual lanes for general data communication plus one virtual lane for management purposes (VL15).
In accordance with the Infiniband Architecture, a packet can be specified as having one of sixteen different service levels (SLs). The service level for a particular packet is specified in the local route header (LRH), and remains constant as the packet transits an Infiniband subnet. The SL value in the packet determines the virtual lane over which the packet is transmitted across any given link in the subnet. This is achieved by having a switch maintain a set of SL-to-VL mappings (which are specific to each input port/output port combination). The SL-to-VL mappings are initialized and maintained by the subnet manager 34 (see
On receipt of an incoming packet, a port first determines the output port to forward the packet to, based on the DLID value in the packet (as explained in more detail below). The port then uses the SL-to-VL mappings to decide the virtual lane over which the packet should be sent, given the SL value in the packet and the output port from which the packet will be transmitted. Note that since different switches may support different numbers of virtual lanes, a packet may be assigned to different virtual lanes for different links of its journey across a subnet.
The range of service levels can be used to provide a quality of service (QoS) mechanism in an Infiniband network. Thus any given virtual lane can be classified as low priority or high priority, and assigned a weight within that classification. The weight and classification of a virtual lane control its access to the bandwidth of the physical link, relative to the other virtual lanes supported over the same link. The service level of a packet then determines the virtual lane utilised by the packet over the link, in accordance with the SL-to-VL mappings. These mappings can be configured to reflect the number of virtual lanes provided by any given link and also the quality of service policy of the network.
The Infiniband Architecture supports the concept of partitioning in order to provide logical isolation of components sharing the same subnet. All nodes included in a route from a source to a destination must share the same 16-bit partition key (PK), otherwise they are unable to communicate with one another (or even to recognise each other's existence). An individual node may support multiple partition keys, and so belong to multiple different partitions.
A member of a partition can be denoted as a full member or a limited (partial) member, dependent on the high-order bit of the partition key. A full member can communicate with either a limited member or a full member, but a limited member cannot communicate with another limited member of that partition (only a full member). This model corresponds to a client-server architecture, where servers are full members and clients are partial members, and clients do not need generally to talk directly to one another.
Each queue pair at an end node has a partition key table which is assigned to it by the subnet manager 34 (see
Each port 81 on switch 26 is provided with an input buffer (not shown in
Switching matrix 850 is used to transport data from one port to another. For example, if data arrives on link 28D at port P4 81D and is to be forwarded on link 28A, then switching matrix 850 is responsible for transferring the data from port P4 81D to port P1 81A (corresponding to link 28A). It will be appreciated that while ports 81 are constrained by the Infiniband standard (in order to ensure network connectivity), to some extent switching matrix 850 can be regarded as a more generic switching device, since it is internal to switch 26 and therefore shielded (at least in part) from other network devices.
The Infiniband architecture supports two general modes of communication. The first of these is unicast or point-to-point, in which each data packet goes from a single source to a single destination. This translates into switching matrix 850 transferring a packet from one incoming port to one outgoing port. The other mode of communication in Infiniband is multicast, in which a packet may be routed from a single source to multiple destinations. This is mirrored in the passage of the packet through switching matrix 850, whereby a packet from an incoming port may be directed to multiple outgoing ports.
It is desirable for the switch 26 to have low latency and high efficiency. A low latency implies relatively small amounts of buffering, otherwise delays through the switch will tend to increase. A high efficiency implies that the performance of the switch 26 is not degraded due to competition for resources within the chip as the load (i.e. the traffic through the switch) rises.
As part of the start-up procedure of an Infiniband network, the subnet manager 34 (see
Each LID comprises two portions, a base LID and a number of path bits. The number of path bits in the LID for a given port is determined by the LID mask count (LMC), which is also assigned by the subnet manager 34. Each packet in transit on the subnet contains the LID of the port from which it originated, namely the source LID (SLID), and also the LID for the port to which the packet is going, namely the destination LID (DLID). The SLID and the DLID are incorporated into the local route header (LRH) of the packet.
When a packet is received at its destination, the port checks that the DLID in the packet matches the LID for that port. Note that in this comparison the path bits of the LID are masked out, so that in effect the comparison is made against the base LID for the port. Thus for the purpose of destination checking, the path bits are ignored. However, in terms of routing a packet through a switch, the path bits are taken into consideration. This then allows multiple paths to be specified that all arrive at the same destination port. The ability to provide multiple paths through a subnet to the same destination port aids robustness and reliability within the network.
As mentioned above, Infiniband networks can be divided into partitions to provide community separation facilities within a given subnet or fabric. The administration of Infiniband partitions uses P_Key values within each packet to identify a partition membership of each packet. Thus switches and routers can enforce the partitioning by checking the P_Key value of a packet at ingress and egress against those permitted for a given port. As set out in the Infiniband specification, P_Key enforcement at switches and routers is optional and can be implemented at inbound ports, outbound ports or both of a given device. In the switch of the present example, inbound P_Key enforcement is provided. If a partition violation is discovered, i.e. a packet is attempting to move to a partition not permitted by it's P_Key value, the port can drop the packet or truncate the packet to remove the data payload.
In the present example, the part of the port which deals with P_Key values is implemented using content-addressable-memory (CAM). A typical 16-bit CAM can typically support somewhere in the range of 16 to 64 entries. With one entry being required for each partition, limit on the number of partitions that a single switch can support is therefore limited to the same number as the number of CAM entries. As will be appreciated, large CAMs can be used, however these impose other problems, including cost, and switch designs typically dictate that the number of CAMs in the switch scales linearly with the switch radix.
Thus, in the present example, the performance of the CAM is boosted by using bit masks. One bit mask can be applied at each CAM entry and the size of each bit mask can be adjustable. Accordingly, the switch of the present example is operable to support thousands of entries using a single CAM. Accordingly the switch of the present example can support many orders of magnitude more partitions than a switch using a CAM only.
As is set out in the Infiniband specification, in order for a packet to be forwarded whole from an inbound switch port which provides inbound P_Key enforcement, the P_Key of the packet must be considered to match one of the P_Key values stored in the P_Key table of that port. For the purpose of inbound P_Key enforcement, a P_Key matches an entry in the P_Key table if and only if it is not the invalid P_Key (defined as x000000000000000) and one of the following conditions are true:
The output of each AND gate 1105 is passed to a comparator 1107. At each of the comparators 1107 the AND gate result is compared to a corresponding P_Key from a P_Key table 1109 stored in a CAM. Finally, the output of the comparators 1107 is passed to an OR gate 1111 which produces an output indicating whether or not the P_Key value from the packet matches any of the P_Keys from the table.
As will be appreciated, by this process, the masks effectively create don't care values within the P_Keys stored in the P_Key table 1109. Thereby, each P_Key stored in the P_Key table acts as many P_Keys, all sharing some but not all bit positions. Thus a significantly larger number of partitions can be managed than through use of the P_Key table alone. In the example given above, where a P_Key mask is 6 bits long, this can increase the total number of partitions managable by a single P_Key table entry by up to 26=64.
Each P_Key mask can be set individually, therefore a common mask can be set for some or all of the P_Key values in the table if desired. If such an approach is to be used, then it is possible to reduce the size of the P_Key mask table to the number of unique P_Key masks.
Thus there has now been described a system for increasing the partition handling capability of an Infiniband device such as a switch. This arrangement provides an increased community separation capability of the switch, enhancing the usability of an Infiniband network for use by multiple distinct groups.
In some examples, a CAM may be replaced by a TCAM (Ternary CAM). Such a device can store 3 data states (0, 1, and x, where x represents don't know or don't care). The use of such a device enables the arrangement of
Although the embodiments above have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications as well as their equivalents.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4551833||Aug 10, 1983||Nov 5, 1985||At&T Bell Laboratories||Distributed monitoring of packet transmission delay|
|US4896319||Mar 31, 1988||Jan 23, 1990||American Telephone And Telegraph Company, At&T Bell Laboratories||Identification and authentication of end user systems for packet communications network services|
|US5812195||Jul 22, 1997||Sep 22, 1998||Envistech, Inc.||Video compression using an iterative correction data coding method and systems|
|US5956102||Nov 4, 1997||Sep 21, 1999||Hitachi America Ltd.||Methods and apparatus for the efficient implementation of signal synchronization and cyclic redundancy checks in communication systems|
|US6115376||Oct 29, 1997||Sep 5, 2000||3Com Corporation||Medium access control address authentication|
|US6201829||Apr 3, 1998||Mar 13, 2001||Adaptec, Inc.||Serial/parallel GHZ transceiver with pseudo-random built in self test pattern generator|
|US6289015||Sep 17, 1998||Sep 11, 2001||Tut Systems, Inc.||Method and apparatus for the secure switching of a packet within a communications network|
|US6304196||Oct 19, 2000||Oct 16, 2001||Integrated Device Technology, Inc.||Disparity and transition density control system and method|
|US6393082||Nov 6, 1998||May 21, 2002||Nec Corporation||Signal synchronism detecting circuit|
|US6407682||Jun 30, 2000||Jun 18, 2002||Intel Corporation||High speed serial-deserializer receiver|
|US6459698 *||Jun 18, 2001||Oct 1, 2002||Advanced Micro Devices, Inc.||Supporting mapping of layer 3 priorities in an infiniband ™ network|
|US6570884||Nov 5, 1999||May 27, 2003||3Com Corporation||Receive filtering for communication interface|
|US6606328||Dec 15, 1999||Aug 12, 2003||Intel Corporation||Look ahead encoder/decoder architecture|
|US6718392||Oct 24, 2000||Apr 6, 2004||Hewlett-Packard Development Company, L.P.||Queue pair partitioning in distributed computer system|
|US6839794||Oct 12, 2001||Jan 4, 2005||Agilent Technologies, Inc.||Method and system to map a service level associated with a packet to one of a number of data streams at an interconnect device|
|US6851059||Oct 19, 2000||Feb 1, 2005||International Business Machines Corporation||Method and system for choosing a queue protection key that is tamper-proof from an application|
|US6898752 *||May 31, 2002||May 24, 2005||Agilent Technologies, Inc.||Apparatus and methods for combinational error detection in an InfiniBand switch|
|US6920106||Sep 7, 2001||Jul 19, 2005||Agilent Technologies, Inc.||Speculative loading of buffers within a port of a network device|
|US6922749||Oct 12, 2001||Jul 26, 2005||Agilent Technologies, Inc.||Apparatus and methodology for an input port of a switch that supports cut-through operation within the switch|
|US6988161||Dec 20, 2001||Jan 17, 2006||Intel Corporation||Multiple port allocation and configurations for different port operation modes on a host|
|US7010607||Sep 14, 2000||Mar 7, 2006||Hewlett-Packard Development Company, L.P.||Method for training a communication link between ports to correct for errors|
|US7020160||Dec 17, 2001||Mar 28, 2006||Supergate Technology Usa, Inc.||Interface circuits for modularized data optimization engines and methods therefor|
|US7061899||May 1, 2001||Jun 13, 2006||Hewlett-Packard Development Company, L.P.||Method and apparatus for providing network security|
|US7072343||Sep 27, 1999||Jul 4, 2006||Cisco Technology, Inc.||Methods and apparatus for controlling a data stream using a host agent acting on behalf of a host computer|
|US7103626 *||May 24, 2000||Sep 5, 2006||Hewlett-Packard Development, L.P.||Partitioning in distributed computer system|
|US7113995||Oct 19, 2000||Sep 26, 2006||International Business Machines Corporation||Method and apparatus for reporting unauthorized attempts to access nodes in a network computing system|
|US7124241||May 7, 2003||Oct 17, 2006||Avago Technologies General Ip (Singapore) Pte.Ltd.||Apparatus and methodology for a write hub that supports high speed and low speed data rates|
|US7133409 *||Jul 19, 2001||Nov 7, 2006||Richard Willardson||Programmable packet filtering in a prioritized chain|
|US7150021||Oct 12, 2001||Dec 12, 2006||Palau Acquisition Corporation (Delaware)||Method and system to allocate resources within an interconnect device according to a resource allocation table|
|US7180862||Jul 18, 2002||Feb 20, 2007||Intel Corporation||Apparatus and method for virtual output queue feedback|
|US7185062||Jan 18, 2002||Feb 27, 2007||Emc Corporation||Switch-based storage services|
|US7221650||Dec 23, 2002||May 22, 2007||Intel Corporation||System and method for checking data accumulators for consistency|
|US7225467||Oct 11, 2001||May 29, 2007||Lockheed Martin Corporation||Active intrusion resistant environment of layered object and compartment keys (airelock)|
|US7237016||Sep 7, 2001||Jun 26, 2007||Palau Acquisition Corporation (Delaware)||Method and system to manage resource requests utilizing link-list queues within an arbiter associated with an interconnect device|
|US7245627||Apr 23, 2002||Jul 17, 2007||Mellanox Technologies Ltd.||Sharing a network interface card among multiple hosts|
|US7302432 *||Jul 23, 2003||Nov 27, 2007||Mosaid, Technologies, Inc.||Method and apparatus for searching a filtering database with one search operation|
|US7474666 *||Sep 3, 2003||Jan 6, 2009||Cisco Technology, Inc.||Switch port analyzers|
|US7493409 *||Apr 10, 2003||Feb 17, 2009||International Business Machines Corporation||Apparatus, system and method for implementing a generalized queue pair in a system area network|
|US20010056553||Jun 21, 2001||Dec 27, 2001||Nec Corporation||Method and system for routing packets without losing packets by monitoring outgoing lines|
|US20020057699||Apr 19, 2000||May 16, 2002||Roberts Lawrence G.||Micro-flow management|
|US20020087383||Sep 24, 1998||Jul 4, 2002||Timothy J. Cogger||Integrated interface for web based customer care and trouble management|
|US20020101967||Nov 29, 2001||Aug 1, 2002||Chi Eng||Method and a system for settlement of trading accounts|
|US20020118692||Jan 4, 2001||Aug 29, 2002||Oberman Stuart F.||Ensuring proper packet ordering in a cut-through and early-forwarding network switch|
|US20020147947||Mar 2, 2001||Oct 10, 2002||Derek Mayweather||Detecting bit errors in a communications system|
|US20020181455||Jun 1, 2001||Dec 5, 2002||Norman Richard S.||Cell-based switch fabric with inter-cell control for regulating packet flow|
|US20030021230||Mar 9, 2001||Jan 30, 2003||Petaswitch Solutions, Inc.||Switch fabric with bandwidth efficient flow control|
|US20030061379 *||Sep 27, 2001||Mar 27, 2003||International Business Machines Corporation||End node partitioning using virtualization|
|US20030079019||Jan 18, 2002||Apr 24, 2003||Lolayekar Santosh C.||Enforcing quality of service in a storage network|
|US20030093627 *||Nov 15, 2001||May 15, 2003||International Business Machines Corporation||Open format storage subsystem apparatus and method|
|US20030161429||Nov 5, 2002||Aug 28, 2003||Via Technologies, Inc.||Device and method for comma detection and word alignment in serial transmission|
|US20030198251||Jan 21, 2003||Oct 23, 2003||Black Alistair D.||Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost|
|US20030223416||May 31, 2002||Dec 4, 2003||Edmundo Rojas||Apparatus and methods for dynamic reallocation of virtual lane buffer space in an infiniband switch|
|US20030223435||May 31, 2002||Dec 4, 2003||Gil Mercedes E.||Apparatus and methods for increasing bandwidth in an infiniband switch|
|US20030223453||May 31, 2002||Dec 4, 2003||Gil Stoler||Round-robin arbiter with low jitter|
|US20030236900 *||May 14, 2002||Dec 25, 2003||Hsiao-Keng Chu||Method and apparatus for facilitating the implementation of an IP link over an InfiniBand network|
|US20040001487||Jun 28, 2002||Jan 1, 2004||Tucker S. Paul||Programmable InfiniBand switch|
|US20040001503||Jun 28, 2002||Jan 1, 2004||Manter Venitha L.||Apparatus and method for arbitrating among equal priority requests|
|US20040022257||Jul 30, 2002||Feb 5, 2004||Brocade Communications Systems, Inc.||Supporting local IB packet communication between separate subnets|
|US20040024903||Jul 30, 2002||Feb 5, 2004||Brocade Communications Systems, Inc.||Combining separate infiniband subnets into virtual subnets|
|US20040039986||Aug 23, 2002||Feb 26, 2004||Solomon Gary A.||Store and forward switch device, system and method|
|US20040071134||Jun 30, 2003||Apr 15, 2004||Brocade Communications Systems, Inc.||Apparatus and method for routing traffic in multi-link switch|
|US20040073534||Oct 11, 2002||Apr 15, 2004||International Business Machines Corporation||Method and apparatus for data mining to discover associations and covariances associated with data|
|US20040081394||Jan 31, 2001||Apr 29, 2004||Giora Biran||Providing control information to a management processor of a communications switch|
|US20040085977||Oct 30, 2002||May 6, 2004||Intel Corporation||Method, system, and program for processing data packets in packet buffers|
|US20040120254||Dec 23, 2002||Jun 24, 2004||International Business Machines Corporation||Input port routing circuit that performs output port filtering|
|US20040213224||Jun 25, 2001||Oct 28, 2004||Mark Goudreau||Apparatus and method for classifying packets|
|US20040215848 *||Apr 10, 2003||Oct 28, 2004||International Business Machines Corporation||Apparatus, system and method for implementing a generalized queue pair in a system area network|
|US20040225734||May 7, 2003||Nov 11, 2004||Schober Richard L.||Method and system to control the communication of data between a plurality of inteconnect devices|
|US20040252685||Jun 13, 2003||Dec 16, 2004||Mellanox Technologies Ltd.||Channel adapter with integrated switch|
|US20050058150||Sep 16, 2003||Mar 17, 2005||Boles Glenn M.||Method and apparatus for enhancing packet communication|
|US20050071472 *||Sep 30, 2003||Mar 31, 2005||International Business Machines Corporation||Method and system for hardware enforcement of logical partitioning of a channel adapter's resources in a system area network|
|US20050108395 *||Nov 5, 2003||May 19, 2005||International Business Machines Corporation||Determining server resources accessible to client nodes using information received at the server via a communications medium|
|US20050138368||Dec 19, 2003||Jun 23, 2005||Sydir Jaroslaw J.||Method and apparatus for performing an authentication after cipher operation in a network processor|
|WO2002089405A2||Apr 25, 2002||Nov 7, 2002||The Boeing Company||Fibre channel transceiver|
|WO2003075477A2||Feb 28, 2003||Sep 12, 2003||Xilinx, Inc.||High speed configurable transceiver architecture|
|1||3GPP Infiniband Specification Release 1.0a, Jun. 19, 2001, pp. 2, 62, 71, 155-156, 182-186 and 193-194.|
|2||Bu, Long et al., "A Keyword Match Processor Architecture using Content Addressable Memory", GLSVLSI' 04, Apr. 26-28, 2004, Boston Massachusetts, ACM, pp. 372-376.|
|3||Infiniband Architecture Specification vol. 1, Release 1.1, Nov. 6, 2002 Final, Copyright 1999, 2001, 2002, by InfiniBand Trade Association.|
|4||Infiniband Architecture Specification vol. 2, Release 1.1, Nov. 6, 2002 Final, Copyright 1999, 2001, 2002, by InfiniBand Trade Association.|
|5||PCT International Search Report for International Application No. PCT/US2005/016775, 4 pages.|
|6||Written Opinion of the International Search Authority for International Application No. PCT/US2005/016775, 5 pages.|
|7||Xilinx: "Virtex-II Pro Platform FPGAs: Functional Description", Product Specification, Dec. 10, 2003, pp. 1-5, XP-002348226.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7983265 *||Jul 19, 2011||Qlogic, Corporation||Method and system for processing a network packet|
|US8553696 *||Mar 2, 2011||Oct 8, 2013||Intel Corporation||Method and system for processing a network packet|
|US8762518 *||Jul 10, 2009||Jun 24, 2014||Telcordia Technologies, Inc.||Program and method for adaptively maintaining a local peer group in a dynamic environment|
|US20110010446 *||Jul 10, 2009||Jan 13, 2011||Telcordia Technologies, Inc.||Program and Method for Adaptively Maintaining a Local Peer Group in a Dynamic Environment|
|Cooperative Classification||H04L41/0893, H04L12/4641|
|Dec 9, 2004||AS||Assignment|
Owner name: SUN MICROSYSTEMS, INC.,CALIFORNIA
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|Aug 2, 2011||CC||Certificate of correction|
|Nov 6, 2013||FPAY||Fee payment|
Year of fee payment: 4
|Dec 16, 2015||AS||Assignment|
Owner name: ORACLE AMERICA, INC., CALIFORNIA
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