|Publication number||US7809930 B2|
|Application number||US 11/657,134|
|Publication date||Oct 5, 2010|
|Filing date||Jan 24, 2007|
|Priority date||Jan 24, 2007|
|Also published as||US20080177983|
|Publication number||11657134, 657134, US 7809930 B2, US 7809930B2, US-B2-7809930, US7809930 B2, US7809930B2|
|Inventors||Frederic Claude Marie Piry, Norbert Bernard Eugene Lataille|
|Original Assignee||Arm Limited|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Classifications (8), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems utilising register renaming so as, for example, to facilitate out-of-order processing.
2. Description of the Prior Art
It is known to provide data processing systems in which register renaming mechanisms are used whereby register specifiers for an architectural destination register (i.e. the destination register as specified within an instruction of the instruction set) is mapped to a physical register provided within the system for use in executing the associated program instruction. Such techniques are useful in avoiding write-after-read (WAR) hazards, write-after-write (WAW) hazards and in facilitating the reordering of instructions at execution time. The technique is also useful in enabling a data processing system to speculate over unresolved exception points within the program instruction flow. It will be appreciated that register renaming is useful for a variety of reasons, and is not limited in its application to out-of-order processing.
In known register renaming techniques a processor core renames an architectural register specified by an instruction thereby allocating a new physical register to be used in place of an architectural register for each architectural destination register specifier encountered within each instruction. Once this allocation/mapping is done, then the processor core can execute the instruction using the physical registers in the “physical register world”.
There are a number of drawbacks associated with known register renaming techniques. The number of physical registers which may be provided is finite and the register renaming mechanism can run short of available physical registers to be used for mapping to architectural registers. This is particularly the case in data processing systems in which program instructions can involve the use of a large number of registers, e.g. the LDM (load multiple) instructions of the ARM instruction set of the processors produced by ARM Limited of Cambridge, England. If the register renaming mechanism runs out of available physical registers to use for the remapping then this can stall the instruction pipeline. This problem gets worse as pipeline depth increases as there will be more program instructions concurrently “in-flight” and consuming physical registers.
One way of reducing this problem would be to provide a larger number of physical registers. However, the provision of such physical registers consumes circuit area and power, which is in itself disadvantageous.
Another problem associated with register renaming techniques is that the register renaming processing mechanisms themselves consume power and have a finite bandwidth. Signal values transitioning within the register renaming mechanisms to perform mappings for every architectural destination register encountered within an instruction represent a significant source of energy consumption. Furthermore, when some instructions may have a large number of architectural destination registers, either a disadvantageously large register renaming mechanism has to be provided in order that these renaming operations can all be performed in parallel, or the renaming operations have to be serially performed with a consequent potential for stalls and/or delayed processing.
Viewed from one aspect the present invention provides apparatus for processing data, said apparatus comprising:
a physical set of registers;
register renaming circuitry for mapping from register specifiers of an architectural set of register specifiers to registers of said physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set; and
mapping control circuitry coupled to said register renaming circuitry and responsive to a current state of said apparatus to control said register renaming circuitry in respect of a register specifier of said architectural set of registers specifiers for an instruction either:
The present technique recognizes that the known techniques for register renaming in which a renaming operation is performed for each architectural destination register whilst being safe in the sense of avoiding various hazards (e.g. WAR, WAW etc) are wasteful in terms of numbers of physical registers required, consumed renaming bandwidth and energy consumption associated with renaming since a significant portion of the renaming, mappings performed are unnecessary. As an example, it is known that compilers often target particular registers for use as source and destination registers more than other registers which are equally available. Thus, an infrequently used register may be renamed by an architectural to physical mapping and then all the processing activity associated with that mapped physical register finished prior to the next time the architectural register is encountered and is a candidate for a further mapping to a physical register. In this circumstance, the present technique recognizes from the current state of the system that a new mapping is not required and consequently suppresses performance of a mapping operation by the register renaming circuitry and instead allows the existing mapping to be reused. This saves consuming a further physical register as well as saving the processing steps and renaming bandwidth which would be involved in such an unnecessary mapping operation. It will be appreciated that this is merely one example of the circumstances in which the mapping operation may be suppressed.
Whilst the current state of the system to which the mapping control circuitry can be responsive to suppress or not suppress the mapping operation can take a wide variety of different forms, one good candidate for use in suppressing unnecessary mapping operations is detecting when the current state indicates whether the register of the physical set of registers mapped by an existing mapping is allocated to storing a value still required for at least some outcomes of one or more other instructions, whereupon the mapping operation is not suppressed as the existing mapping is not available for use.
The ways in which a value stored within a physical register in accordance with an existing mapping may be required for at least some outcome of other instructions include the use of that value for recovery from one or more speculative changes in architectural state (recovery for example being necessary due to one of a branch misprediction, an abort, an exception and an interrupt), a requirement due to another instruction still needing to read the value stored within that physical register as part of its execution, or the requirement of the original instruction or some other instruction (e.g. one which had already reused the mapping) to write a value to that physical register.
Another example of current state of the system which can be detected and used to suppress unnecessary mappings is the detection of the circumstance in which a mapping is allocated to storing a value written by a first instruction with the same architectural register being written by a second instruction when the first instruction and the second instruction have mutually exclusive conditions controlling their execution such that only one of the first instruction or the second instruction will be executed. In this circumstance, due to the relationship of the mutually exclusive conditions controlling execution of the two instructions, a write-after-write hazard does not exist and the register mapping can be reused without hazard. In practice, this type of relationship between instructions is surprisingly common and accordingly the mechanisms deployed to recognize such situations (e.g. which may be recognizing adjacent instructions with mutually exclusive condition codes) can be relatively simple and yet yield a significant advantage in avoiding unnecessary register renaming.
Viewed from another aspect the present invention provides apparatus for processing data, said apparatus comprising:
a physical set of registers;
register renaming means for mapping from register specifiers of an architectural set of register specifiers to registers of said physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set; and
mapping control means coupled to said register renaming circuitry and responsive to a current state of said apparatus for controlling said register renaming circuit in respect of a register specifier of said architectural set of registers specifiers for an instruction either:
mapping from register specifiers of an architectural set of register specifiers to registers of a physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set; and
controlling said mapping in respect of a register specifier of said architectural set of registers specifiers for an instruction either:
The above, and other objects, features and advantages of this invention will be apparent from the following detailed description of illustrative embodiments which is to be read in connection with the accompanying drawings.
Also illustrated in
As mentioned above, the mapping control circuitry 24 serves to suppress mapping operations by the renaming unit 8 when these are unnecessary. In this case the existing mapping is used and the architectural register renamed with the physical register specifier to produce an instruction in the form of instruction 28 that has been renamed.
If the determination at step 32 was that there are no pending writes, then step 36 checks for any pending reads to the existing physically mapped register which is the candidate for reuse. If there are any such pending reads (e.g. as monitored by the renaming unit 8 using the architectural to physical table 20 and its associated control registers 22), then processing again proceeds to step 34 and a new mapping is generated.
If the determination at step 36 was that there are no pending reads, then step 38 determines whether or not the existing physically mapped register is still required as a recovery register for any pending unresolved instructions. It may be that due to incorrect speculative execution of an instruction by the system the value held in the existing physically mapped register will be needed for use as a recovery register when the processing is rewound following correction of the incorrect speculation. If the determination at step 38 is that the existing physically mapped register is not required as a recovery register for any pending unresolved instructions, then the existing physically mapped register is properly available for re-use and according step 40 suppresses the mapping operation which would otherwise be performed by the renaming unit 8 and instead simply reuse the existing physically mapped register to rename the register specifier in the instruction using the mapping already held within the architectural to physical mapping table 20. This saves renaming bandwidth within the renaming unit 8 and reduces the power consumption of the renaming unit 8.
It will be appreciated that there may be other circumstances in which unnecessary mappings may be suppressed in register renaming. The above are common examples where the technique produces a good return for the necessary provision of control circuitry in the mapping control circuitry 24.
Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6061777 *||Oct 28, 1997||May 9, 2000||International Business Machines Corporation||Apparatus and method for reducing the number of rename registers required in the operation of a processor|
|US6170052 *||Dec 31, 1997||Jan 2, 2001||Intel Corporation||Method and apparatus for implementing predicated sequences in a processor with renaming|
|US6826677 *||Feb 6, 2001||Nov 30, 2004||Pts Corporation||Renaming registers to values produced by instructions according to assigned produce sequence number|
|US7127592 *||Jan 8, 2003||Oct 24, 2006||Sun Microsystems, Inc.||Method and apparatus for dynamically allocating registers in a windowed architecture|
|Cooperative Classification||G06F9/3842, G06F9/384, G06F9/30072|
|European Classification||G06F9/38E1R, G06F9/30A5, G06F9/38E2|
|Apr 19, 2007||AS||Assignment|
Owner name: ARM LIMITED, UNITED KINGDOM
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LATAILLE, NORBERT BERNARD EUGENE;PIRY, FREDERIC CLAUDE MARIE;REEL/FRAME:019213/0085
Effective date: 20070315
|Mar 5, 2014||FPAY||Fee payment|
Year of fee payment: 4