|Publication number||US7076224 B2|
|Application number||US 10/310,252|
|Publication date||Jul 11, 2006|
|Filing date||Dec 4, 2002|
|Priority date||Dec 6, 2001|
|Also published as||US20030129946|
|Publication number||10310252, 310252, US 7076224 B2, US 7076224B2, US-B2-7076224, US7076224 B2, US7076224B2|
|Inventors||Florence Giry-Cassan, François Van Zanten|
|Original Assignee||Stmicroelectronics S.A.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Non-Patent Citations (1), Referenced by (7), Classifications (22), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Technical Field of the Invention
The invention relates to the decoding of a radio frequency transmission channel conveying coded digital information. It applies advantageously but not limitingly to receiving and decoding terrestrial digital television signals.
The invention thus relates more especially to tuners, in particular those of the double-conversion type, such as for example those incorporated into the modulation/demodulation devices (modems) intended for receiving terrestrial digital signals, that is to say those conveyed by cable.
In the case of cable reception, the input frequencies of the signal are spread over a span of from 47 MHz to 864 MHz in intervals of 6 or 8 MHz. This represents 135 channels. An extension to 1 GHz is moreover envisaged in the future.
2. Description of the Related Art
At present, modems are equipped with a head filter. For reasons of economy, the elimination of this head filter is envisaged. This consequently implies that 135 channels can enter the tuner, this representing a considerable input dynamic range. It is consequently necessary to control the gain of the input amplifier stage of the modem so as to avoid nonlinearities which would be caused by a saturation phenomenon, and to do so without excessively degrading the signal-to-noise ratio.
At present, the power of the signal is measured after analog/digital conversion and the gain of the tuner is controlled on the basis of this power measurement according to a predetermined control law. However, the adjustment of the gain does not in any way depend on the power of the signal entering the tuner, but only on the power of the desired signal.
The invention aims to afford another solution to the control of the gain of a tuner.
Implementations of the invention limit the dynamic range required, in particular on the input amplifier stage and the first frequency transposition stage (mixer) of the tuner.
The invention therefore proposes a process for controlling the gain of a frequency tuner, in particular of the double-conversion type, in which the power of the signal is measured after an analog/digital conversion, and the gain is controlled on the basis of this power measurement according to a predetermined control law.
According to a general characteristic of the invention, the power of the analog signal, tapped off between an input amplifier stage and a first frequency transposition stage or immediately after the first frequency transposition stage, is measured. The measured power is compared with a predetermined power threshold so as to obtain first binary information, and the gain control law is set on the basis of the values of binary control information obtained from the said first binary information.
Thus, according to an implementation of the present invention, if the measured power is greater than the threshold, the control law is modified, while the control law is left unchanged otherwise. The received signal power information can be extracted, either at the output of the input amplifier stage, or at the output of the mixer. A person skilled in the art will be able to choose the optimal tap off point as a function of the envisaged application and the desired and/or required performance.
Specifically, in one case the detection of signal power at the output of the input amplifier stage may exhibit a significant load which may penalize this input amplifier stage, especially at high frequencies.
However, in the case of a tuner of the double-conversion type, a bandpass filter is generally integrated at the output of the mixer, thus incurring the risk, in certain instances, of no longer observing jammers (i.e., transmitting devices that jam channels at predetermined frequency ranges) at the extremity of the pass band of the bandpass filter.
Also, in general, if the input amplifier stage is not overly penalized, it may be worthwhile placing the detection of signal power at its output.
If the signal power lies relatively close to the reference threshold adopted, there is a risk of sensitivity to small variations. Also, in this case, it may be preferable to provide for a comparison in a hysteresis-type comparator, i.e. a comparator having hysteresis.
Although the invention applies to all types of tuners, such as for example tuners with zero intermediate frequency and/or used for GSM reception, implementations of the invention apply advantageously to double-conversion tuners, such as those deployed in modems connected to transmission cables for terrestrial digital signals. A tuner of the double-conversion type furthermore may comprise a second transposition stage connected downstream of the first transposition stage and a second amplification stage connected downstream of the second transposition stage. The control law may be used in controlling a first adjustment of the gain of the input amplifier stage and a second adjustment of the gain of the second amplification stage.
According to an implementation of the invention, the modification of the control law, which occurs when the measured power is greater than the threshold, may be used to thereafter perform, for example, an additional decrease of the gain of the input amplifier stage and an increase of the gain of the second amplification stage.
An implementation of the invention is a frequency tuner, for example embodied at least partially in an integrated manner on a semiconductor substrate, comprising an analog block comprising controllable-gain amplification means including at least one input amplifier stage and at least one first frequency transposition stage connected downstream of the input amplifier stage, as well as a digital block connected to the analog block by an analog-to-digital conversion stage and comprising first measurement means for measuring the power of the signal generated by the conversion stage, and gain control means for controlling the gain of the amplification means on the basis of the power measurement and the control law.
According to a general characteristic of the invention, the frequency tuner furthermore includes second measurement means, connected between the input amplifier stage and the first frequency transposition stage or immediately after the first frequency transposition stage, for measuring the power of the tapped analog signal; comparison means, such as a comparator having hysteresis, for comparing the power thus measured with a predetermined threshold and delivering first binary information; and control means, connected between the comparison means and the gain control means, for selectively setting the control law on the basis of the values of binary control information obtained from the first binary information.
According to an embodiment of the invention, the frequency tuner furthermore comprises means for storing the first binary information, for example a D flip-flop connected to the output of the comparator; and filtering means, connected between the output of the D flip-flop and the control means, for performing a filtering of the information provided by the D flip-flip, so as to deliver the binary control information.
If the measured power is greater than the predetermined threshold, the control means, for example, modifies the control law, and otherwise leaves the control law unchanged.
In the case, for example, where the frequency tuner is of the double-conversion type, the control means, for example, modifies the control law which may result in additionally decreasing the gain of the input amplifier stage and increasing of the gain of the second amplification stage.
An application of the invention may be as a receiver of terrestrial digital signals, comprising a frequency tuner as defined hereinabove.
Other advantages and characteristics of the invention will become apparent upon examining the following detailed description, which is in no way limiting, and the appended drawings, in which:
The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, the embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
The receiver RCP may comprise at the head end a tuning device or tuner, TN, intended for selecting the desired channel from among the set of channels present in the signal received at the input of receiver RCP.
The tuner TN may be of the double-conversion type, that is to say it comprises two frequency transposition stages or mixers, MX1 and MX2.
Thus, while the input frequencies of the input signal may be spread from 47 MHz to 864 MHz, in intervals of 6 or 8 MHz, the first mixer performs a transposition at a frequency of, for example, the order of 122 MHz. The second mixer MX2 reduces the frequency to 44 MHz, for example.
Upstream of the first mixer MX1 is a control-gain input amplifier stage AGC1.
The mixer MX1 may be followed by an external bandpass filter SF1 filtering, for example, in the 1090 MHz–1220 MHz band.
A second control-gain amplification stage AGC2 may be disposed between the second mixer MX2 and a second external bandpass filter SF2 centered, for example, around approximately 44 MHz.
Together, these components form part of an analog block BAN, which is linked to a digital block BNM by way of an analog-to-digital conversion stage CAN.
Digital block BNM may comprise a processing means for performing, in a conventional manner, processing for demodulating and decoding the symbols conveyed in the received signal. The processing means may, for example, include conventional demodulation circuitry and decoding circuitry.
Moreover, the digital block BNM may comprise first measurement means MM1 for calculating the power of the digital samples tapped at the output of the conversion stage CAN. First measurement means MM1 may be implemented as conventionally known circuitry that measures signal power. Gain control means and/or device ACTL, of conventionally known structure and known manner of operation, may then control the gain G1 of the amplifier stage AGC1 and the gain G2 of the amplifier stage AGC2 on the basis of the digital power thus calculated, and of a predefined control law. By way of example, the gains G1 and G2 may vary in intervals of approximately 8 dB.
According to the invention, the analog block BAN may furthermore comprise second measurement means and/or device MM2 formed here of a multiplier whose two inputs are coupled to the output of the input amplifier stage AGC1. The output of the multiplier therefore supplies, by multiplying its input signal by itself, power information for the analog signal tapped at the output of the amplifier stage AGC1.
This power measurement is filtered in a low-pass filter FL3, in such a way as to retain only the DC component which relatively accurately represents the power level of the input signal. By way of example, it will be possible to choose a low-pass filter whose cut-off frequency is of the order of approximately 50 KHz, thereby making it possible to eliminate the smallest of the parasitic frequencies, of the order of 6 MHz. This smallest parasitic frequency is equal to F2-F1, where F2 represents the frequency of a jammer and F1 represents the frequency of the input signal or of a jammer.
A comparator CMP makes it possible to compare the total power output from the filter FL3 with a threshold SSE. This threshold SSE can be programmed via an I2C bus in such a way as to allow greater fineness of control of the gain of amplifier stages AGC1 and AGC2.
Of course, the reference threshold SSE depends on the application envisaged and on the accuracy required.
By way of example, in the case of cable reception, this reference threshold SSE can be fixed at approximately −27.75 dBm seen from the input, which corresponds to approximately 135 spectral lines at 0 dBm.
The output of the comparator CMP is therefore a signal taking the voltage level, for example, 0v or Vdd (for example 5 volts), as a function of the comparison. This output of the comparator CMP therefore supplies first information which may be regarded as binary and which may therefore be coded as logic 0 or logic 1.
If the power received lies in a manner very close to the reference threshold SSE, there is a risk of sensitivity to small variations. To avoid this, hysteresis is advantageously utilized in the comparator CMP.
Moreover, a D flip-flip, referenced as BSC in
The digital filter FN makes it possible to average the binary information delivered by the flip-flop BSC and to deliver filtered binary information, hereinafter referred to as “binary control information”.
By way of example, the digital filter FN can perform a sliding average over a few symbol durations, for example over about 10 samples.
Control means and/or circuit MC will then set the control law incorporated into the control means and/or circuit ACTL as a function of the binary control information value delivered by the digital filter FN. The control means ACTL includes circuitry that generates control signals for controlling the gains of amplifiers AGC1 and AGC2.
Thus, referring more especially to
If, on the other hand, the measured power is less than the reference threshold SSE, then the control law is unchanged by control means MC (step 22) and the gains G1 and G2 of the amplifiers AGC1 and AGC2 continue to be controlled by the control law of the control means ACTL without change thereto.
The invention therefore proposes a gain control process which operates permanently during the operation of the receiver and which thus makes it possible to limit the input dynamic range required, in particular on the input amplifier stage AGC1, by taking note of the power which actually enters the tuner, without thereby overly degrading the signal-to-noise ratio.
The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4748684 *||Jun 29, 1987||May 31, 1988||Information Resources, Inc.||Fast tuning control for a television system|
|US5353288 *||Aug 30, 1991||Oct 4, 1994||Alcatel N.V.||Device for selecting reception signals as a function of their power|
|US5552838 *||Dec 22, 1994||Sep 3, 1996||Kabushiki Kaisha Toshiba||Apparatus for tuning offset signals by controlling a tuner based on a difference in frequency of signals tuned by that tuner|
|US5603115 *||Apr 5, 1995||Feb 11, 1997||Hwa Lin Electronics Co., Ltd.||Direct broadcasting satellite tuner with an auto threshold control demodulator|
|US5732341||Aug 31, 1995||Mar 24, 1998||Qualcomm Incorporated||Method and apparatus for increasing receiver immunity to interference|
|US5737033 *||Oct 30, 1995||Apr 7, 1998||Sharp Kabushiki Kaisha||AGC apparatus concurrently satisfying sufficient impedance matching characteristic and linear AGC characteristic|
|US5898912||Jul 1, 1996||Apr 27, 1999||Motorola, Inc.||Direct current (DC) offset compensation method and apparatus|
|US5940143 *||Oct 4, 1996||Aug 17, 1999||Hitachi, Ltd.||High-definition television signal receiving apparatus and gain control circuit thereof|
|US5999802 *||Jun 6, 1994||Dec 7, 1999||Rca Thomson Licensing Corporation||Direct conversion tuner|
|US6148189 *||Apr 26, 1996||Nov 14, 2000||Aschwanden; Felix||AGC circuit arrangement for a tuner|
|US6154503 *||Jun 5, 1997||Nov 28, 2000||Sharp Kk Corporation||Automatic gain control system that responds to baseband signal distortion|
|US6324387||Dec 29, 1998||Nov 27, 2001||Philips Electronics N.A. Corp.||LNA control-circuit for receive closed loop automatic gain control|
|US6421099 *||Nov 19, 1999||Jul 16, 2002||Samsung Electronics Co., Ltd.||Automatic frequency tracking apparatus and method for a television signal receiving system|
|US6678010 *||Jan 25, 2001||Jan 13, 2004||Lg Electronics Inc.||Method and apparatus for generating auto gain control signal having information storing feature|
|US6714776 *||Sep 28, 1999||Mar 30, 2004||Microtune (Texas), L.P.||System and method for an image rejecting single conversion tuner with phase error correction|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7233206 *||Apr 25, 2003||Jun 19, 2007||Renesas Technology Corp.||Semiconductor integrated circuit device and wireless communication system|
|US7271852 *||Sep 10, 2003||Sep 18, 2007||Samsung Electronics Co., Ltd.||Digital television receiver with automatic gain control unit and method|
|US7672659 *||Mar 2, 2010||Telefonaktiebolaget L M Ericsson (Publ)||Mixer with feedback|
|US20030228852 *||Apr 25, 2003||Dec 11, 2003||Motoki Murakami||Semiconductor integrated circuit device and wireless communication system|
|US20040176064 *||Dec 23, 2003||Sep 9, 2004||Sven Mattisson||Mixer with feedback|
|US20040207761 *||Sep 10, 2003||Oct 21, 2004||Samsung Electronics Co., Ltd.||Digital television receiver with automatic gain control unit and method|
|US20070093225 *||Dec 14, 2006||Apr 26, 2007||Renesas Technology Corp.||Semiconductor integrated circuit device and wireless communication system|
|U.S. Classification||455/241.1, 455/138, 455/251.1, 455/192.3, 330/278, 348/685, 348/678, 330/254, 330/282, 455/180.3, 455/136, 348/725, 455/67.11, 455/234.1|
|International Classification||H04B1/06, H04B7/00, H03G3/30, H03G3/00|
|Cooperative Classification||H03G3/3068, H03G3/001|
|European Classification||H03G3/30E3, H03G3/00D|
|Mar 14, 2003||AS||Assignment|
Owner name: STMICROELECTRONICS, S.A., FRANCE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GIRY-CASSAN, FLORENCE;VAN ZANTEN, FRANCOIS;REEL/FRAME:013837/0513
Effective date: 20030214
|Nov 28, 2006||CC||Certificate of correction|
|Jan 5, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Dec 23, 2013||FPAY||Fee payment|
Year of fee payment: 8