|Publication number||US4725972 A|
|Application number||US 06/632,857|
|Publication date||Feb 16, 1988|
|Filing date||Jul 16, 1984|
|Priority date||Jul 14, 1983|
|Also published as||CA1261084A, CA1261084A1, DE3378245D1, EP0131641A1, EP0131641B1|
|Publication number||06632857, 632857, US 4725972 A, US 4725972A, US-A-4725972, US4725972 A, US4725972A|
|Original Assignee||Ant Nachrichtentechnik Gmbh|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Non-Patent Citations (20), Referenced by (33), Classifications (17), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a method and apparatus for the transmission of time discrete signals between two systems operating at different sampling rates. Stated another way, it relates to a method and apparatus whereby a signal sampled at a first sampling rate is converted to a signal sampled at a second sampling rate, and wherein the conversion is effected at a signal processing rate that is not higher than the higher of the two sampling rates.
A known digital sampling frequency converter is disclosed in an article "A Two-channel 16-bit Digital Sampling Frequency Converter for Professional Digital Audio," Lagadec et al, ICASSP-82 (International Conference on Acoustics, Speech and Signal Processing), Paris, Pages 93-96. In the converter described in this article, the sampling rate is increased 215 times and then reduced, resulting in a disadvantageously high processing rate.
It is an object of the present invention to overcome this drawback of the prior art system by providing a method and apparatus for converting from one sampling rate to another sampling rate at a signal processing rate which is not higher than the higher of the two sampling rates.
Another object is to provide an apparatus which can be used at any desired ratio of sampling rates.
Still another object is to provide a system which is simple, employs a relatively low signal processing rate and can be used at any desired sampling rate ratio.
The present invention provides a method and apparatus for the transmission of time discrete signals between source and sink systems wherein a first signal x(n) is generated by the source system at a first sampling rate fi from which signal a second time discrete signal y(m) is derived and fed to a sink system at a second sampling rate f0. The method is carried out by cyclically distributing the first time discrete signal to each of L filter groups at the first sampling rate fi. Each of the L filter groups comprises M filter elements which have their inputs connected to a common terminal and have the transfer function Hl,m (zLM), where L and M are integers, l is an integer 0, 1 . . . L-1 corresponding to the filter group in which the filter element is located and m is an integer 0, 1 . . . M-1 corresponding to the location of the filter element in its associated filter group. The first time discrete signal is filtered in each of the filter elements as a processing rate fi /L and the filtered signals stored in the filter elements. Thereafter, the stored outputs of the M filter elements in each of the L filter groups are cyclically sampled at the second sampling rate f0 and coupled to corresponding inputs of a summing element which generates a signal y(m) at its output at the sampling rate f0 equal to M/L fi.
FIG. 1 is a prior art cascade apparatus for converting the sampling rate of an input signal to a different sampling rate by the use of an integer interpolator and an integer decimator.
FIGS. 2a and 2b are respectively prior art polyphase commutator interpolator and decimator devices which may be used in the apparatus of FIG. 1.
FIG. 3 is a schematic diagram of the present invention for transmitting time discrete signals between systems having different sampling rates.
FIG. 4 is a block diagram of a filter element used in the apparatus of FIG. 3.
FIG. 1 illustrates a prior art apparatus, disclosed in an article "Interpolation and Decimation of Digital Signals--A Tutorial Review", Crochiere et al, Proceedings of the IEEE, Volume 69, No. 3, March 1981, pages 300-331, for digitally converting an input signal x(n) sampled at a first rate F to an output signal y(m) having a sampling rate F'. The sampling rate of the signal x(n) is increased by the factor L in a sampling rate expander 10 to produce a signal w(k), where L is an integer. The output of expander 10 is applied to a low pass filter 12 having an impulse response h(k) which operates at the sampling rate LF. The output of the filter 12, v(k), is applied to a sampling rate compressor 14 which decreases the sampling rate of the signal v(k) by the factor M, where M is an integer, to produce the signal y(m) having a sampling rate F'=L/M F.
As discussed at page 306 of the Crochiere article, the sampling rate conversion system of FIG. 1 increases the signal sampling rate by a factor of L (by filling in L-1 zero-valued samples between each sample of x(n) to give the signal w(k)), filters w(k) by a standard linear time-in variant low-pass filter 12 to give v(k), and compresses v(k) sampling rate by a factor M by retaining one of each M sample of v(k). A direct implementation of this system is inefficient because the low-pass filter 12 operates at the high sampling rate on a signal for which L-1 out of each L input values are zero, and the values of the filtered output are required only once for each M samples.
The signal rate expander 10 (which performs the process of interpolation) and the signal rate compressor 14 (which performs the process of decimation) can be realized by polyphase finite impulse response (FIR) or recursive structures, respectively. FIG. 2a shows a known polyphase integer decimator employing a commutator SD wherein an input signal x(n) is distributed at a sampling rate F to M filters having the impulse response pi (n), where i=0, 1 . . . M-1. Commutator SD, which rotates in the counterclockwise direction, is provided with a common terminal 16 to which the signal x(n) is connected, and m terminals 0 to M-1, each of which is connected to one end of a corresponding polyphase filter p0 (n), p1 (n) . . . pM-1 (n). The other ends of the polyphase filters are commonly connected to an adder 18 to produce the signal y(m) having the reduced sampling rate F/M.
The decimator of FIG. 2a can be transposed into the sampling rate interpolator shown in FIG. 2b by inverting all of the directional arrows and replacing all summing points by branching points. That is, a signal x(n) having a sampling rate F is applied simultaneously via terminal 16' to all of the inputs of filters pi (n) and then cyclically sampled at the rate M by the switch SD rotating in the counterclockwise direction. This produces a signal y(m) at the output terminal 18' at the increased sampling rate MF.
The present invention is based on the realization that the individual filters pi (n) in the decimator of FIG. 2a can be replaced by a decimator operating in a transposed mode, that is, as a sampling rate interpolator, thereby providing for conversion of the sampling rate at the ratio M/L. This substitution makes it possible to perform simultaneously all filter operations at the lowest possible sampling rate, namely fi /L=f0 /M, where fi is the rate at which the input signal x(n) is sampled and f0 is the rate at which the output signal y(m) is sampled.
Referring to FIG. 3, the input signal x(n) at the output of a source system 20, sampled at a rate fi, is coupled to the common terminal 22 of a distributor multiplexer Sn which rotates in the clockwise direction and has terminals l=0, 1, 2, . . . (L-1). Distributor multiplexer Sn may be realized in a practical embodiment of the invention by SN 74 LS 138 produced by Texas Instruments for L=8, for instance.
L filter groups have their inputs connected respectively to terminals l=0, 1 . . . L-1 of distributor multiplexer Sn. Each of the L filter groups consists of M filter elements, and each of the M filter elements has the transfer function Hl,m (zLM), where l is an integer 0, 1 . . . L-1 corresponding to the filter group in which the filter element is located and m is an integer 0, 1 . . . M-1 corresponding to the location of the filter in its associated filter group.
More specifically, the filter group l=0 comprises M filter elements having the transfer functions H0,0 (zLM), H0,1 (zLM) . . . H0,M-1 (zLM), the M filter elements in filter group l=1 have the transfer functions H1,0 (zLM), H1,1 (zLM) . . . H1,M-1 (zLM) and the M filter elements in the L-1st filter group l=L-1 have the transfer functions HL-1,0 (zLM), HL-1,1 (zLM) . . . HL-1,M-1 (zLM).
Sampling multiplexers S0, S1 . . . SL-1, which are arranged to rotate in the counterclockwise direction, couple the outputs of the M filter elements in each of filter groups l=0, 1 . . . L-1 respectively to terminals 0', 1' . . . (L-1)' of a summing device 24. The signal y(m) at the output terminal 26 has the sampling rate f0 =M/F fi, and is provided to the sink system 28. Multiplexers S0, S1 . . . SL-1 and summer 24 are commercially available as SN 74 LS 25A for multiplexing of M=8 signals, and as SN 74 LS 83A for the binary summation of 4 bits, for example, both manufactured by Texas Instruments.
The filter elements used in the apparatus of FIG. 3 can be realized by the state-space filter structure shown in the block diagram of FIG. 4 although other equivalent filter structures may also be used. In this circuit, an input terminal 30 is connected to one of the terminals 0, 1 . . . L-1 of the distributor multiplexer Sn and the output terminal 32 to one of the terminals 0, 1 . . . M-1 of one of the switches S0, S1 . . . SL-1. An vector multiplier 34 having the transfer function b has its single input coupled to terminal 30 and its outputs to terminal 32 through a vector adder 44 and a matrix delay element 36, having a matrix transfer function z-1, and a device 38 for producing the scalar product of its elements together with its input vector having a transfer function cT and an adder 46 for two signals. A feedback matrix multiplier 40 having a matrix transfer function A has its inputs coupled to the outputs of the matrix delay element 36 and and its vector output coupled to the second vector input of the vector adder 44, and a scalar multiplier 42 with a transfer function d is coupled between the input 30 and the second input terminal of adder 46.
The symbols A, b, cT, z-1, x(k) and d have the following definitions:
A is a square matrix with N rows and N columns, where N is the degree of the transfer function of the filter of FIG. 4 ##EQU1## b is the N-dimensional input vector of the structure FIG. 4 (a column vector) ##EQU2## cT is the N-dimensional filter output vector, where the superscript denotes transposition (a row vector)
cT =(c1, c2 . . . cN)
z-1 and z respectively, are diagonal matrices ##EQU3## which represent all delay functions inherent to the filter of FIG. 4, where ##EQU4## x(k) is the N-dimensional state-vector which represents the state of the filter at the time instant k (a column vector), and d is a scalar factor. According, for instance, to the standard textbook S. A. Tretter, "Introduction of discrete-time signal processing", John Wiley+Sons, New York, 1976, pp. 128-137, the operation of the filter of FIG. 4 can completely be described by means of the state-equations for filters with one input and one output
Thus, the actual output signal of the filter of FIG. 4 can be calculated according to the standard rules of vector algebra, which are depicted in FIG. 4: The new state at instant k+1 is given by the sum of matrix A multiplied from the right hand side by the state vector of instant k and the product of the input vector b times the value of the input signal at instant k. Then, the output signal at instant k is given by the sum of the scalar product
cT x(k)=c1 x1 (k)+c2 x2 (k)+ . . . +cN xN (k)
of the output vector and the filter state of instant k and the product of the scalar (one-dimensional) value d with the input signal at time instant k. From this the transfer function of the filter of FIG. 4 can be derived according to Tretter as mentioned above as follows:
H(z)=cT (z-A)-1 b+d
Since the filter of FIG. 4 actually operates at the rate fi/L=fo/M, the argument of H(z) has to be replaced by zLM, as it is already shown in the definiton of the matrices z-1 and z, respectively. Furthermore, since H(zLM) is only a subfilter of FIG. 3, the number of the filter group 1 and the number of the filter within the filter group has to be indicated by indices, yielding
Hl,m (zLM)=cT l,m (z-A)-1 bl,m +dl,m
The detailed operation of the circuit of FIG. 3 will now be explained.
As an arbitrary starting position of the various multiplexers we define all switches to be in l=0 and m=0 position. Then the sample of the source signal x(n) is fed to all branch filters of the group l=0, from which the filter Ho,o (zLM) provides the summer via multiplexer switch So with a contribution to the output signal y(m). The other multiplexer switches S1, S2, . . . , SL-1 may provide additional contributions to y(m) via the summer 24, which stem from earlier inputs to the filter groups l=1, 2, . . . L-1. The key for the understanding of the operation of FIG. 3 is that the input multiplexer Sn switches from one to the adjacent position every Ti =1/fi seconds, whereas the output multiplexers So, S1, . . . , SL-1 change to the adjacent positions every To =1/fo seconds. For any position of every switch the same operations have to be carried out as it was described for the l=0 and m=0 position.
In contrast to the state of the art (FIGS. 1+2), the invention according to FIG. 3 comprises a greater number of parallel branches (higher degree of parallelism), where on the other hand the branches according to the invention can operate at a lower rate.
The system for sample rate alteration can be operated in two fundamentally different modes:
(a) the synchronous mode:
This means that the input and output sampling rate fi and fo, respectively, are derived from a common clock generator providing a frequency of F=L fo =Mfi
(b) the asynchronous mode:
The source and sink systems are totally independent systems with autonomous clocks of their own. Each system has a nominal clock frequency fi and fo, respectively, and a maximum possible deviation of its clock frequency ±Δfi and ±Δfo, respectively. In this case, the input multiplexer Sn may be synchronized by the instantaneous sampling rate fi of the source system fi -Δfi ≦fi ≦fi +Δfi or by the nominal sampling rate of the source system, which is equal to the arithmetic mean of the input sampling rate ##EQU5## On the other hand, the output multiplexers may be synchronized by the sink system in the same manner as it was explained for the input synchronization.
Thus, it can be seen that the present invention is advantageous in that better parallelization is obtained and the operating rate reduced, with no higher sampling rates than fi /L=f0 /M occurring with any selected values of L and M. When it is desired to increase the sampling rates, it is only necessary to add additional filter groups and filter elements corresponding to the values of L and M. Also, as has been shown, the systems coupled by the circuit of FIG. 3 may be operated asynchronously or synchronously; that is, f0 /fi may be approximately equal to M/L.
It will be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims.
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|International Classification||H04B1/66, H03H17/04|
|Cooperative Classification||H04B1/66, H03H17/0277, H03H17/0422, H03H17/0275, H03H17/0628, H03H17/0685, H03H17/0455|
|European Classification||H03H17/04C2, H03H17/04C4R, H03H17/02F8D2, H03H17/02F8D4, H03H17/06C2, H03H17/06C4R, H04B1/66|
|Aug 24, 1987||AS||Assignment|
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