|Publication number||US4835416 A|
|Application number||US 07/091,851|
|Publication date||May 30, 1989|
|Filing date||Aug 31, 1987|
|Priority date||Aug 31, 1987|
|Also published as||CA1322231C, EP0305935A2, EP0305935A3|
|Publication number||07091851, 091851, US 4835416 A, US 4835416A, US-A-4835416, US4835416 A, US4835416A|
|Inventors||William E. Miller|
|Original Assignee||National Semiconductor Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Non-Patent Citations (2), Referenced by (31), Classifications (22), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention is directed to circuitry for on-chip protection against power supply load dump transients, to the structure of the devices utilized in such circuitry, and to methods for fabricating these structures.
2. Discussion of the Prior Art
Integrated circuit devices are easily damaged by power supply transients unless protection circuitry is provided. One of the most severe conditions to be protected against is known as "automotive load dump". This condition can be described in conjunction with the graph provided as FIG. 1.
As is well known, in the basic configuration of an automotive electrical system, a battery and an alternator are connected in parallel to the input VDD power supply pad of the various operative low current logic circuits in the system. The alternator is capable of generating a large current to charge the battery and to supply the other automotive loads. A "load dump" event occurs when the alternator's load is disconnected, for example when a battery connector comes loose or, in a less severe example, when the automobile's headlights are turned off. Because of the current flow through the alternator and its inherent inductance, a magnetic field is established which prevents the alternator's output current from changing rapidly. When the alternator's load is suddenly reduced, charge, and thus voltage, builds up at the VDD power supply pad of the operative circuits, which remain connected to the alternator's output.
As illustrated in FIG. 1, a sudden voltage increase, or "load dump transient", is applied to the VVDD supply pad at the time of the upset, t=0. This transient, which can be expressed as
VDD =14+46e-t/ 120 msec.
for the typical automotive system, is quite high close to the battery and decreases with distance from the battery. For example, the transient voltage might reach 80V in the engine compartment, 60V along the firewall and 40V in the passenger compartment.
The logic circuits in the system must, obviously, remain in their normal operating mode up to a VDD supply voltage of 16V. However, if the VDD supply voltage rises above 16V, such as in the event of a load dump transient, disruption of the circuit's normal operation is permitted, but no permanent damage can result within the circuit and it must not pass greater than 20V to other circuits in the system via its outputs. When, as shown in FIG. 1, the VDD supply voltage returns to less than 16V with time, the circuit must return to normal operation.
The conventional approach to solving the problem of load dump transients has been to provide an arrangement of external passive components between the power supply and the supply pad of the operative circuit. This typically takes the form of an external network of resistors and capacitors which serves as a filter for the voltage surge. Alternatively, an external inductor is inserted in series with the operative circuit to resist the changing current caused by the transient. These solutions require extra components, which increase cost, and consume valuable space within the system.
According to the present invention, protection circuitry is integrated with operative low current logic circuitry such that the operative circuitry can experience a VDD power supply transient, recover, and then return to normal operation without suffering permanent damage. Additionally, the protection circuitry insures that the transient voltage does not traverse the operative circuitry to be passed by its output lines to the system databus. Further protection is provided for an integrated voltage regulator and for on-chip level shifting circuitry which provide an interface with the 16V VDD supply levels and 16V external logic signal levels.
The protection circuitry of the present invention utilizes junction-isolated CMOS device technology. Devices having gate oxides approximately 1000 Angstroms thick are utilized to provide the interface to a 9-16V automotive power supply and signal lines. Devices having gate oxides approximately 400 Angstroms thick are utilized to provide 5V logic and processing circuitry; these devices are powered by the integrated 5V regulator. Voltage reducing devices are connected between the VDD supply pad of the operational circuit and the remainder of the operational circuit to limit the voltage and current passed to the operational circuit.
Thus, as stated above, three integrated circuit areas are protected from load dump transients. First, the integrated 16V low current logic circuits are protected by connecting the VDD supply pad to large value polysilicon resistors in series with the power supply nodes of these circuits. Second, the integrated 16V high current output signal circuits are protected by connecting the VDD supply pad directly to the source of the p-channel MOS output driver of the output circuit, the driver's drain being connected to the output signal pad. Third, the integrated 5V regulated supply circuit is protected by connecting the VDD supply pad to a polysilicon resistor in series with the source of the p-channel MOS output driver of the regulated circuit, the drain of the output driver being connected to the 5V regulated supply pad.
Each of the p-channel MOS driver transistors has its gate connected to an integrated supply voltage detection circuit which, upon detection of supply levels greater than 16V, shorts the gate of the driver to its source to turn it off. The gate of each of these devices is also connected to the normal operational control logic through series, high-value, N-well diffused resistors.
All of the above-described transistors and resistors are uniquely designed to withstand maximum load dump voltage and current transients, yet are fabricated in the course of normal process flow.
Thus, it is a primary object of the present invention to provide integrated protection against power supply load dump transients.
It is also an object of the present invention to provide integrated protection circuitry utilizing a unique application of conventional processing techniques.
It is a further object of the present invention to provide integrated protection both against power supply transients for internal operative circuitry as well as against passage of the transient voltage to the outputs of the internal circuitry.
These and other objects, advantages and features of the load dump protection circuitry of the present invention will be better understood and appreciated by reference to the detailed description of a preferred embodiment of the invention provided below which should be considered in conjunction with the accompanying drawings.
FIG. 1 is a graph illustrating voltage versus time during a power supply load dump transient.
FIG. 2 is a simplified schematic diagram illustrating a preferred embodiment of an integrated load dump protection circuit in accordance with the present invention.
FIG. 3 is a cross-sectional view illustrating a p-channel device structure of the type used in the load dump protection circuit shown in FIG. 2.
FIG. 4 is a cross-sectional view illustrating further detail of a field plate for a p-channel device structure of the type utilized in the load dump protection circuit shown in FIG. 2.
FIG. 5 is a schematic diagram illustrating an integrated load dump detect latch which turns off a logic circuit output driver in accordance with the present invention.
FIG. 6 is a schematic diagram illustrating an analysis of the gate voltage of the P-channel MOS driver transistor during load dump.
FIG. 7 is a schematic diagram illustrating an integrated load dump protection circuit for a supply voltage regulator in accordance with the present invention.
FIG. 8 is a schematic diagram illustrating an analysis of load dump current in the supply voltage regulator shown in FIG. 7.
FIG. 2 shows an automotive load 12, such as an automobile battery, connected through switch S1 to the VDD supply pad 13 of an integrated circuit 10. An alternator power supply 16 is also connected to the supply pad 13. The opening of switch S1 represents the occurrence of an operational upset which causes a power supply load dump transient of the type illustrated in FIG. 1.
Connected between the VDD supply pad 13 and a low current logic circuit 14 are 2KΩ polysilicon resistors 18. While polysilicon resistors 18 are illustrated in FIG. 2 as a single resistor, it should be understood that they may be a plurality of parallel-connected resistors, each such resistor being connected to a separate logic circuit.
In automotive applications, the low current logic circuit 14 swings from voltage levels from 0V up to normal battery voltage, which at a maximum is 16V. The voltage drop across resistors 18 during normal operation will be small because logic circuit 14 requires very low current to operate under normal conditions. However, when, as shown in FIG. 1, the VDD supply voltage rises to approximately 60V during a transient event, the resistors 18 drop most of the transient voltage to protect the devices in circuit 14.
Thus, in accordance with a first aspect of the present invention, 2K106 polysilicon thin film resistors 18 are provided in series with the VDD supply voltage pad 13 to protect and supply the low current logic circuit 14. As stated above, resistors 18 serve to limit the supply current to logic circuit 14 during power supply transients. Under normal operation, poly resistors 18 will pass less than 50 microamps each and drop less than 100 millivolts.
Resistors 18 are fabricated to be large enough so as not to burn out during a power supply load dump transient. Because they are fabricated over field oxides having a thickness of 6-12K Angstroms, resistors 18 have approximately 60-120V isolation from the remainder of the logic circuit 14. The required sizes of resistors 18 for the illustrated application are easily realized at 2μ×200 μm.
The output inverter which drives the output pad 15 of logic circuit 14 presents a more difficult design problem, since it must be a low resistance driver. For example ##EQU1## or <100Ω resistance. where
VOH =output voltage at pad 15 and
IOH =output current at pad 15.
It is impractical to use polysilicon resistors of the type described above in series with the VDD supply voltage on each output driver, since the logic circuit 14 typically has many outputs and these large size poly resistors would also enlarge the output driver devices which together would occupy a very large chip area.
Thus, in accordance with a second aspect of the present invention, load dump protection circuitry is provided which detects the power supply transient voltage and prevents it from reaching the output pad 15 of integrated circuit 10.
When a power supply transient occurs, that is, when switch S1 opens, the VDD supply immediately rises (as shown in FIG. 1). When normally-open switch S3 detects the transient, it closes, thus shorting the gate of driver 20 to its source and turning off driver 20. If switch S3 was not present, the load dump voltage would turn on the p-channel output device 20 and full load dump current would be passed through device 20. This current would be large enough to destroy both the output device 20 and the n-channel output device 22; it would also potentially destroy components off-chip on the databus, which would become low resistive at greater than 20V, the current passing on the databus under these conditions being ##EQU2##
As stated above, and as will be described in greater detail below, the present invention provides a detection circuit which turns off the output driver 20 and maintains all bipolar parasitic devices off during a load dump transient wherein 20V≦VDD ≦60V, and then returns the output driver 20 to normal operation when the VDD supply voltage returns to less than 17V.
The databus associated with circuit 10 is required to be pulled up to full battery voltage during normal operation of the integrated circuit 10. To accomplish this, the output driver 20 is rated at 20V operation under normal conditions. However, as will be described in greater detail below, driver 20 is also capable of withstanding the high voltages generated during power supply transient conditions.
As stated above, in accordance with a third aspect of the present invention, output driver 20 is constructed so that it can withstand a 40V breakdown voltage between its source and drain with its gate off, and a 60V breakdown voltage between its source and the VSS grounded silicon substrate. This is accomplished by providing a unique p-channel, N-well MOS device design which is used to pull up the output pin 15. A conventional n-channel MOS device 22 is used to pull down the output pin 15. Both device 20 and device 22 are fabricated to have approximately 1000 Angstrom gate oxide thickness to provide a breakdown voltage BVDSS approximately equal to 20V. In addition, as will be explained in greater detail below, the breakdown voltage of p-channel device 20 will walk out to approximately 42V due to hot electron injection into the gate oxide near the drain-to-body avalanche breakdown area.
Referring to FIG. 3, it is a well known phenomenon that hot electrons "e" will charge the gate oxide of a field effect transistor and reduce the electric field strength in the depletion layer, allowing the breakdown voltage BVDSS to increase. Due to this effect, the output driver 20, when turned off by the special load dump protection circuitry represented by switch S3, will stand off a drain/source voltage VDS of approximately 42V so that the output voltage VOUT will be less than or equal to 60V-42V=18V.
More specifically, as shown in FIG. 3, as the voltage difference across the source and drain of device 20 increases, the depletion layer, which by definition is a region that contains no free charge carriers, grows larger to hold off the increasing voltage. This results in the creation of an electric field because the free carriers are stripped out and ionized dopant atoms remain. Thus, the P+ region has holes "h" as free carriers which are stripped and negative boron ions which remain. Conversely, in the N- region, the electrons are stripped by the high source/drain potential and positive phosphorous ions remain. This creates positive charge in the N- region and negative charge in the P+ region and produces a large electric field across the junction between the two. As the VDD supply voltage increases, the electric field becomes stronger to the point where electrons "e" are physically torn away from the silicon host material. At this point, the electrons become free to move in the electric field. Because the polysilicon gate of device 20 is tied to a positive potential and the electrons are attracted to a positive potential, the free electrons "e" quickly drift upward toward the poly gate. Thus, the free electrons enter the gate oxide across the potential barrier and provide a negative charge to the gate oxide. This negative charge increases the avalanche breakdown voltage BVDSS of the junction.
Also, the MOS fabrication process utilized to construct the circuit results in bipolar parasitic devices which are able to withstand 60V reverse bias from the VDD nodes (P+ and N- ) to the VSS node (P-), as shown in FIG. 4.
In conventional designs, p-channel output drivers have an N+ guard ring fabricated around the device to prevent an inversion from forming when high voltages occur on the I/O pins. According to a fourth aspect of the present invention, and as shown in FIG. 4, the p-channel channel output driver 20 has a field plate 25 fabricated around it. This field plate 25 is tied to the highest potential present in the output buffer (i.e., the N-well) and, therefore, an inversion channel will not form in the N- area. Also, as described below, the avalanche breakdown voltage of the N-well/P-substrate junction is increased to greater than 60V by the presence of the field plate 25.
The field plate phenomenon illustrated in FIG. 4 makes the N-well/P-substrate junction appear to be planar, when in fact it is curved. The curvature of the junction lowers the breakdown voltage because the electric field is stronger in the curved region. Thus, placing positive charge out over and beyond the PN junction extends the negative potential and, in effect, increases the radius of curvature of the junction.
Thus, in accordance with the present invention rather than injecting carriers as shown in FIG. 3, the field plate 25, which is the same positive potential as the N-well, is physically extended over the junction to increase the avalanche breakdown voltage. Conversely, the effect of placing a negative potential on field plate 25, i.e., tying it to the substrate potential, would make the junction appear as if it physically curves back in. That is, the electric field intensity is reduced by the field plate 25 if it is tied to the diffused N-well region; the electric field intensity is increased if the field plate is tied to the substrate.
Thus, three conditions are met in the design of the output driver 20 to maintain isolation between the N-well and the P-substrate at 60V bias. First, the parasitic bipolar transistors are kept off by absence of base drive voltage. Second, the N- diffusion sufficiently overlaps the P+ diffusion, both vertically and horizontally, to prevent punch through breakdown. Third, the substrate doping is light enough and the field plate 25 described above overlaps the PN junction sufficiently to prevent avalanche breakdown. In general, and in accordance with the present invention, the field plate concept is utilized both in the logic circuit and in the protection circuitry any time an N-well resistor or a P-channel, N-well device is susceptible to having 60V applied to it.
Under load dump transient conditions, the action of the field plate 25 is as shown in FIG. 4. The field plate overlap of the N- well is "a+b". A potential of 60V-2φb =59.4V is present across the distance "a" on the silicon surface. Area "b" on the silicon surface is at potential 2φb =0.6V. As the overlap is reduced, area "b" goes to 0 distance. Then area "a" decreases. When area "a" decreases, the PN breakdown voltage decreases. For maximum PN breakdown voltage, a=c, where "c" is the thickness of the depletion layer into the P-substrate beneath the N-well diffusion. The free electrons formed under the field plate 25 when a+b>c are held captive by the electric field E originating from the polysilicon field plates and do not flow since they are isolated from current sources by the oxide and the depletion layer.
An embodiment of circuitry which detects the load dump transient and turns off the p-channel output driver 20 is shown in FIG. 5. In FIG. 5, p-channel device 20, switch transistor 33 (which is identified as switch S3 in FIG. 2) and 40KΩ resistor 24 correspond to similarly identified components in FIG. 2.
As stated above, to turn off the p-channel output driver 20 requires that switch 33 be closed. In the context of the circuit shown in FIG. 5, this means that the detector circuit comprising resistor 32, transistor 28, resistor 30 and transistor 26 must generate a voltage at Node V2 which activates the gate of switching transistor 33. Thus, components 26, 28, 30 and 32 are configured to form a simple latch which is controlled by the VDD supply voltage. When the VDD supply voltage goes high, transistors 26 and 28 turn on. When the VDD supply voltage drops back down to a safe level, i.e. less than 17V, transistors 26 and 28 turn off.
The latch may be thought of as two inverters, a PMOS inverter and an NMOS inverter, in a loop with the output of the n-channel inverter being provided to the gate of switching transistor 33.
As shown in FIG. 5, when the VDD supply voltage rises above the avalanche breakdown voltage of transistor 26 (BVDSSN ˜18Vwith 1000 Angstrom gate oxide and with long Leff, transistor 26 has no snap back on its ID vs. VDSS curve), then Node V2 l is clamped at BVDSS =18V. If the VDD supply voltage rises above BVDSSN +|VTP |19V, then transistors 28 and switch 33 turn on. As switching transistor 33 turns on, output driver 20 turns off preventing excess load dump voltage on the output pad 15. If the output voltage VOUT was permitted to exceed 18V, then the n-channel output driver device (device 22 in FIG. 2) and external components on the databus could be damaged.
The devices in the load dump detect latch shown in FIG. 5 are sized so that when VDD is less than or equal to 18V, the latch transistors 26 and 28 will be off, i.e. draw no quiescent current, and switching transistor 33 will be off. This is required so that normal operation of driver 20 occurs when the VDD supply voltage is less than 18V. To accomplish this, I4 R32 is designed to be less than or equal to VT26 when VDD is less than 18V so that transistor 26 will be off and Node V2 =VDD. This is realized with resistor 32=40KΩ, transistor 28 W/L=30/70 and VT26 =1.7V. Also, resistors 24, 32 and 30 are all designed to withstand 60V by using N-well and field plates as described above in conjunction with FIG. 4.
During transient conditions, transistor 26 experiences avalanche breakdown. That is, when the VDD supply voltage applied to transistor 26 gets too high, current begins to flow through resistor 30. This turns on transistor 28. In turn, transistor 28 being on allows current flow through resistor 32 which turns on transistor 26. All of this was initiated by the avalanche breakdown of transistor 26. Resistor 30 limits the current so that transistor 26 is not destroyed, but forces the latch to turn on and switch transistor 33 on. Conversely, when the VDD supply voltage returns to normal, i.e. less than 17V, the voltage across resistor 32 goes low, turning off transistor 26, which resets the latch and turns off switch transistor 33.
The advantage of implementing the load dump detect latch utilizing transistor 28 and resistor 32 rather than deleting them, is that when the gate of transistor 28 is clamped at 18V by BVDSS of transistor 26, and the VDD supply voltage and the source of transistor 28 rise to greater than BVDSS of transistor 26, plus 18V, then Node V2 will be set by the latch to 0V. This will occur on the rising edge of a load dump transient greater than 36V. The latch will then hold Node V2 at 0V until the VDD supply voltage becomes less than 18V on load dump. With the full latch, transistor 20 is turned off, IOUT is approximately 0 and VOUT is less than 20V during the entire time of a load dump of magnitude greater than or equal to 36V (at time t=0).
When load dumps of magnitude less than 36V (at time t=0) occur, the latch will not be set, but Node V2 will be held at the BVDSS equal to 18V of transistor 26. Switch 33 will be opened and be capable of pulling V3 greater than VDD -|VTP | so that output driver 20 is off, as explained below and illustrated in FIG. 6.
FIG. 6 provides a schematic illustration of the operation and w/L ratio for device 33 of the load dump protection circuit for output transistor 20 with test model values. Circuit operation can be calculated using the following equation (where VDS, VGS and VTO are all negative values) and results are provided in Table 1 below: ##EQU3## which can be rearranged for solution of VDS ##EQU4##
where β=7×10-6 amp/V2
Transistor 20 will be off when VGS20 =VDS33 >1V=VTP.
TABLE 1______________________________________Peak VDD V2 Peak VDS Peak I3______________________________________60 V 0 V -.30 V 1043 μa36 V 0 V -.22 V 445 μa35 V 18 V -.45 V 413 μa25 V 18 V -.48 V 163 μa21 V 18 V -.61 V 60 μa20 V 18 V -.86 V 29 μa______________________________________
When I3 is greater than 53 ua, which is the saturation current of transistor 27, then transistor 27 will be in avalanche breakdown.
As shown in FIG. 7, the present invention also provides power supply load dump protection for an on-chip supply voltage regulator. The supply voltage regulator circuit relies on the same load dump detect latch and switch circuit as used for the output driver 20, as described above.
The purpose of the on-chip voltage regulator is to drop the voltage from the VDD supply level, which is operating at about 9-16 volts from the battery, to 5V as a supply for the integrated 5V logic load.
In addition to the load dump detector and latch (i.e. components 26, 30, 28 and 32) switching transistor S2 and isolation resistor 34, a 100Ω poly resistor 39 is added in series with the voltage regulator output driver 36. Resistor 39 is required since the output voltage VREG cannot be allowed to go above 10V due to the low avalanche breakdown voltage of the 400 Angstrom gate oxide devices utilized in the low voltage portion of the circuit. Thus, given the maximum 10V requirement on the regulator and the VDS =40V limitation of p-channel device 36 due to its VDS walk out as described above, the resistor 39 handles the additional 10V of the 60V transient. This is illustrated in FIG. 8.
Referring again to FIG. 7, 3MΩ resistor 38 supplies a small current through zener diode 40 to maintain a 5V reference voltage at the gate of n-channel device 42. N-channel devices 42 and 44 in conjunction with p-channel devices 46 and 48 function as a comparator circuit to maintain the voltage VREG at the same level as the voltage of the gate of device 42. Since the gate of n-channel device 44 is tied to the voltage VREG, the gates of both n-channel device 42 and n-channel device 44 are maintained at 5V. Thus, if voltage VREG goes to high, the regulator output voltage applied to the gate of p-channel device 36 tends to turn device 36 off.
The load dump current in the regulator is analyzed as shown in FIG. 8. The load dump current ##EQU5## from t=0 to t=29 msec. when I=100 ma to 0 ma
Standard low voltage process technology is utilized to fabricate the high voltage devices, e.g. output driver 20, described above. Thus, the P-substrate, N-well and field oxide regions are defined according to conventional MOS process steps. Then, a thick 700 Angstrom gate oxide is grown in areas which have been cleared of field oxide. Selected areas of the thick oxide layer are then masked and etched. A thin oxide layer is then grown in these latter areas to define 400 Angstrom thin gate oxide, 1000 Angstrom gate oxide over those areas not cleared of the 700 Angstrom oxide, and field oxide regions. Standard MOS processing is then used to complete the devices.
It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention and that circuit structures within the scope of these claims and their equivalents be covered thereby.
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|U.S. Classification||327/546, 361/56, 326/14, 257/359, 361/111, 327/434, 361/91.5, 257/355, 327/541|
|International Classification||H01L27/02, H01L29/78, H01L27/06, H01L29/06, H01L21/822, H01L29/40, H01L27/04|
|Cooperative Classification||H01L27/0251, H01L29/402, H01L29/7813|
|European Classification||H01L27/02B4F, H01L29/40P, H01L29/78B2T|
|Aug 31, 1987||AS||Assignment|
Owner name: NATIONAL SEMICONDUCTOR CORPORATION, 2900 SEMICONDU
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:MILLER, WILLIAM E.;REEL/FRAME:004819/0748
Effective date: 19870831
Owner name: NATIONAL SEMICONDUCTOR CORPORATION, A CORP. OF DE.
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MILLER, WILLIAM E.;REEL/FRAME:004819/0748
Effective date: 19870831
|Mar 13, 1990||CC||Certificate of correction|
|Jul 20, 1992||FPAY||Fee payment|
Year of fee payment: 4
|Sep 27, 1996||FPAY||Fee payment|
Year of fee payment: 8
|Nov 29, 2000||FPAY||Fee payment|
Year of fee payment: 12