Im very new to cadence. Is it possible to analyse leakage power in low digital circuits at circuit level? what is the difference between leakage power analysis at circuit level and at logic level? which tool is used to do so? I dont know how to..where to start with? My aim is to take tablet PC as a reference..and minimize sub threshold leakage power particularly in digital circuits of tablet PC architecture... results in reduction of its static power dissipation.
It would be very useful if i get any quick response. Thanks.