|Publication number||US7170321 B2|
|Application number||US 11/212,259|
|Publication date||30 Jan 2007|
|Filing date||26 Aug 2005|
|Priority date||27 Aug 2004|
|Also published as||US20060044046|
|Publication number||11212259, 212259, US 7170321 B2, US 7170321B2, US-B2-7170321, US7170321 B2, US7170321B2|
|Inventors||Ross W. Bird, William C. Knoll, John M. Staron|
|Original Assignee||Qortek, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (3), Classifications (13), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is based upon and claims priority under 35 U.S.C. § 119(e) from U.S. Provisional Application No. 60/605,472 filed Aug. 27, 2004, entitled Gate Drive Circuit with Negative Offset, the contents of which are hereby incorporated in its entirety by reference thereto.
1. Field of the Invention
The present invention generally relates to a circuit enabling positive and negative drive from a DC power supply.
2. Description of the Related Art
A conventional integrated circuit driver generates a waveform having a voltage range from ground to some positive value, typically 12 to 15 volts. However, many applications require a voltage waveform having both negative and positive values.
Therefore, what is required is a simple and efficient gate drive circuit capable of offsetting a DC voltage waveform.
Furthermore, what is required is a simple and efficient gate drive circuit that minimizes transients and noise associated with the offset of a positive DC voltage waveform.
An object of the present invention is to provide a gate drive circuit that minimizes switching transients, noise, and other inefficiencies during the offset of a positive DC voltage waveform.
The present invention includes an isolator stage, driver stage, optional tuning stage, offset stage, shaping stage, and switching stage, each electrically coupled in the order described. The isolator stage provides electrical isolation from signal level circuitry and allows for high quality low side gate drivers on both high and low side devices. The driver stage boosts power within the signal from the isolator stage so as to enable drive of the switching stage. The tuning stage slows rising and falling edges within the gate drive signal from the driver stage so as to reduce dV/dt related problems. The offset stage shifts the otherwise positive, unipolar gate drive signal from either the driver stage or the tuning stage so as to include negative voltage values. The shaping stage reshapes the signal from the offset stage so as to ensure squared transitions along the signal. The switching device stage allows for voltage control.
The present invention has several advantages. The invention enables tuning of drive circuitry for optimum switching of a variety of switch devices. The invention enables optimization of the drive waveform so as to reduce switching stresses, reduce noise, maximize efficiency, and/or increase speed. The invention has demonstrated efficiency improvements from 5% to 10% at relatively high switching frequencies when operating in a semi-resonant, turn-off configuration.
1 Isolator stage
2 Driver stage
3 Tuning stage
4 Offset stage
5 Shaping stage
6 Switching stage
7 Gate drive circuit
8 Round transition
9 Square transition
10 Rising edge
U1 First integrated circuit
11 Falling edge
U2 Second integrated circuit
Referring now to
The isolator stage 1 of the gate drive circuit 7 produces a voltage waveform for communication into the driver stage 2. The isolator stage 1 is shown comprised of a first integrated circuit U1. The first integrated circuit U1 may be a commercially available logic gate, preferably an optocoupled device. The GND pin of the first integrated circuit U1 is electrically coupled to the switch Q1. While a variety of waveforms are possible,
The driver stage 2 of the gate drive circuit 7 boosts power in the voltage waveform so as to produce a gate drive signal having a higher maximum voltage, as represented in
The tuning stage 3 is an optional circuit between the driver stage 2 and offset stage 4. This stage of the gate drive circuit 7 functions to increase the time differential of rising edges 10 and falling edges 11 along the gate drive signal after the driver stage 2, so as to avoid dV/dt related problems.
In preferred embodiments, the tuning stage 3 includes a resistor R1 and a capacitor C1. The resistor R1 is electrically coupled to the GATE pin of the driver stage 2 at one end and to the offset stage 4 at the other end. The capacitor C1 is electrically connected at one end between the resistor R1 and offset stage 4 and at the other end to the electrical coupling between the first integrated circuit U1 and switch Q1.
The offset stage 4 of the gate drive circuit 7 offsets or shifts the gate drive signal so as to reduce maximum positive voltage values and to include negative voltage values. The output from a typical offset stage 4 is a signal that extends from −5V to −8V up to +15V to +20V.
In preferred embodiments, the offset stage 4 includes two diodes D1, D2, a capacitor C2, and a resistor R2. The first diode D1, preferably a Zener diode, and capacitor C2 are electrically coupled in a parallel arrangement between the tuning stage 3 or driver stage 2 and shaping stage 5. One end of the parallel arrangement is coupled to the resistor R1, when a tuning stage 3 is present, or to the GATE pin of the second integrated circuit U2, for embodiments without a tuning stage 3. The second diode D2, preferably a conventional diode, and resistor R2 are electrically coupled in series. Thereafter, the resistor R2 is coupled between the parallel arrangement of diode D1 and capacitor C2 and shaping stage 5. The diode D2 is coupled to the electrical connection between first integrated circuit U1 and switch Q1.
The shaping stage 5 refines the gate drive signal from the offset stage 4. As represented in
In preferred embodiments, the shaping stage 5 includes a resistor R3 and an inductor L1. Resistor R3 and inductor L1 are coupled in a parallel configuration which is electrically connected at one end to the switch Q1 in the switching stage 6 and to the parallel arrangement in the offset stage 4. While not intending to be bound by theory, the inductor L1 mimics the use of a current source to drive the gate, whereas the resistor R3 damps ringing of the inductor L1 with the gate capacitance.
The switching circuit 6 is shown including a switch Q1 which is electrically connected to a DC BUS and to the shaping circuit 5. Exemplary switches Q1 include commercially available MOSFETs, IGBTs, JFETs, MESFETs, and other semiconductor type devices.
Referring now to
Referring now to
Referring now to
The present invention shown in
5.1 V 500 MW
75 V 500 MW
21.5 Ohm 1/8 W
1% 1206 SMD
510 Ohm 1/4 W
5% 1206 SMD
51 Ohm 1/4 W
5% 1206 SMD
470 PF 50 V
CERAMIC 10 UF
25 V F TYPE
UH 5% FIXED
1200 V 3 A
MOSF 12 A LO
The description above indicates that a great degree of flexibility is offered in terms of the present invention. Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred versions contained herein.
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|U.S. Classification||327/108, 327/379|
|Cooperative Classification||H03K17/162, H03K5/12, H03K17/687, H03K17/063, H03K17/785|
|European Classification||H03K17/16B2, H03K17/785, H03K5/12, H03K17/687, H03K17/06B|
|21 Jun 2010||FPAY||Fee payment|
Year of fee payment: 4
|24 Sep 2010||AS||Assignment|
Effective date: 20050310
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BIRD, ROSS W.;KNOLL, WILLIAM C.;STARON, JOHN M.;REEL/FRAME:025026/0902
Owner name: QORTEK, INC., PENNSYLVANIA
|17 Jul 2014||FPAY||Fee payment|
Year of fee payment: 8