|Publication number||US6268264 B1|
|Application number||US 09/206,186|
|Publication date||Jul 31, 2001|
|Filing date||Dec 4, 1998|
|Priority date||Dec 4, 1998|
|Publication number||09206186, 206186, US 6268264 B1, US 6268264B1, US-B1-6268264, US6268264 B1, US6268264B1|
|Original Assignee||Vanguard International Semiconductor Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Non-Patent Citations (1), Referenced by (15), Classifications (9), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority benefit of Taiwan application Ser. No. 87117381, filed Oct. 21, 1998, the full disclosure of which is incorporated herein by reference.
1. Field of the Invention
The invention relates in general to a method of forming an integrated circuit, and more particularly, to a method of forming a shallow trench isolation (STI).
2. Description of the Related Art
In the very advanced fabrication technology of integrated circuits, to reduce the dimensions of devices and to increase the integration are a leading trend and topic for further development. However, as the dimensions of devices shrink the isolation structures between devices have to shrink as well. It is thus to cause a problem and difficulty in fabrication. Isolation structure such as a field oxide formed by local oxidation (LOCOS) has been widely used in the conventional fabrication process. Due to the consequently caused characteristics such as a bird's beak, this technique cannot meet the requirement for high integration. Other structure such as a shallow trench isolation has been used instead of the field oxide layer, especially in sub-half micron fabrication process.
To fabricate a shallow trench isolation, a nitride layer is commonly used as a hard mask layer on a substrate. Using anisotropic etching, a trench is formed in the substrate. An oxide plug is then filled in the trench to form the shallow trench isolation. In the conventional method, it is inevitable that a recess occurs around the edge of the oxide plug to cause a corner effect. In the subsequent process, such as using ion implantation to form a source/drain region of a transistor in the substrate, the implanted charged ions would accumulate in the recess around edge. An abnormal subthreshold current is caused in a channel region of the transistor due to accumulated charges. That is, a kink effect is caused. The corner effect has been further discussed by Geissler, Poth, Lasky, Johnson, and Voldman in the paper “A New Three-Dimensional MOSFET Gate-Induced Drain Leakage Effect in Narrow Deep Submicron Device” published in IEEE IEDM Technical Digest, 1911.
To solve the problem of corner effect, Fazan and Pierre C. disclosed a method for fabricating a shallow trench isolation in U.S. Pat. No. 5,799,383. In this disclosure, after the formation of an oxide plug, an oxide layer is formed to cover the substrate and the oxide plug. Using wet etching, a pad oxide layer previously formed on the substrate is removed. However, it is known that the step of etching back the oxide layer is performed by a dry plasma etching process. Since the materials of the oxide layer and the pad oxide layer are apparently the same, the selectivity between these two layers for dry etching is so low that there is no effective way to control the etching level. As a consequence, the pad oxide layer is consequently removed while etching back the oxide layer. The substrate is very likely to be exposed under a plasma environment to be damaged by the plasma. Moreover, in the subsequently process such as an ion implantation, the substrate is directly exposed to the high energy implanted ions. The substrate is thus further damaged. Therefore, though this technique disclosed here improve the corner effect, the substrate is easily damaged by directly exposed under a plasma or implanted ions.
It is an object of the invention to provide a method of fabricating a shallow trench isolation. The problem caused by the corner effect are solved, and the substrate is protected from being damaged.
To achieve the above-mentioned objects and advantages, a method of fabricating a shallow trench isolation is provided. A pad oxide layer is formed on a substrate. A hard mask layer is formed on the pad oxide layer. A trench is formed in the substrate and penetrating through the pad oxide and the hard mask layer. The trench is filled with an oxide plug. The hard mask layer is removed, so that the oxide plug has an upper portion protruding out of the substrate. A silicon thin film is formed to cover the oxide plug and the substrate. The silicon thin film is etched back by plasma dry etching to leave a spacer on a side wall of the protruding upper portion of the oxide plug. Using thermal oxidation, the spacer is oxidized into an oxide spacer, so that a shallow trench isolation is formed without the formation of a recess around the edge.
According to the invention, since the silicon thin film and the oxide layer have obviously different etching rates for dry etching, the pad oxide layer can be used as an etching stop for the etching back process without being removed consequently. With the protection of the pad oxide layer, the substrate is not directly under the attack of the etching plasma. In another aspect, with the formation of the spacer, the problems caused by recessed surface around the edge of the shallow trench isolation are eliminated. Furthermore, the pad oxide further protect the substrate from being damaged during the subsequent process such as ion implantation.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
FIGS. 1A to FIG. 1J are cross-sectional views showing a fabrication process for forming a shallow trench isolation in a preferred embodiment according to the invention.
In FIG. 1A, a pad oxide layer 102 is formed on a substrate 100. The pad oxide layer 102 is formed to protect the substrate 100 from being damaged during the subsequent processes and is removed before forming a gate oxide layer. Preferably, the pad oxide layer 102 is formed by chemical vapor deposition (CVD) with a thickness of about 100 Å to 150 Å. A hard mask layer 104, for example, a silicon nitride layer with a thickness of about 1000 Å to 3000 Å, is formed on the pad oxide layer 102. Using photolithography and etching, a part of the hard mask layer 104 is removed to expose a part of the pad oxide layer 100. The exposed pad oxide layer 102 and a part of the underlying substrate 100 are removed to form a trench 106. Typically, the trench 106 is formed with a depth of about 0.2 μm to 0.8 μm, preferably about 0.4 μm. It is to be noted that the actual depth of the trench 106 depends on the dimension of the practical device to be formed.
In FIG. 1B, using thermal oxidation, a liner oxide layer 108 is formed along a surface of the substrate 100 exposed by the trench 106. The liner oxide layer 108 has a thickness, for example, of about 150 Å to 200 Å.
In FIG. 1C, an insulation layer 110, for example, an oxide layer formed by atmosphere pressure CVD, is formed on the hard mask layer 104 to fill the trench 106. The insulation layer 110 has a thickness dependent on the specific depth of the trench 106 and the thickness of other layers such as the hard mask layer 104. Preferably, the thickness of the insulation layer 110 is ranged between 9000 Å to 11000 Å. A densification step is performed under a temperature of about 1000° for about 10 to 30 minutes. A densified structure of the insulation layer 110 is thus obtained.
In FIG. 1D, using the hard mask layer 104 as a stop layer, the portion of the insulation layer 110 above the hard mask layer 104 is removed by chemical mechanical polishing to form an insulation plug 110 a in the trench 106.
In FIG. 1E, the hard mask layer 104 is removed, for example, using hot phosphoric acid solution, to expose the pad oxide layer 102. As a consequence, the insulation plug 110 a has an upper portion outstanding the substrate 100.
In FIG. 1F, a silicon layer 112, for example, a single crystalline silicon layer, a polysilicon layer, or an amorphous silicon layer with a thickness of about 100 Å to 1000 Å, is formed to cover the insulation plug 110 a and the substrate 100.
In FIG. 1G, the silicon layer 112 is etched back to form a silicon spacer 112 a on a sidewall of the protruded portion of the insulation plug 110 a. The method of etch back includes a dry etch such as an electron cyclotron resonance (ECR), reactive ion etching (RIE), and magnetic enhanced RIE. The plasma reactive gas used in the etch back step comprises halogen elements or a mixture of halogen elements and oxygen, for example, gases such as chlorine, bromine, sulfur hexafluoride, oxygen, and hydrogen bromide. Typically, the etching process using one of these reactive gas has a selectivity larger than 20 of the silicon to silicon oxide. Thus, during etching back process, the silicon spacer 112 a has an etching speed twenty times larger than that of the pad oxide layer 102. While the pad oxide layer 102 is exposed, the etching process is obviously slowed down, or stopped without etching, or even removing the pad oxide layer 102 to expose the substrate 100 directly under the plasma environment.
In FIG. 1H, using thermal oxidation, the silicon spacer 112 a (shown in FIG. 1G) is transformed into a silicon oxide spacer 112 b. The formation of the silicon oxide spacer 112 b eliminates the problems caused by the corner effect. The silicon oxide spacer 112 b has a thickness about twice the thickness of the silicon spacer 112 a. That is, the thickness of the silicon spacer 112 a is 0.4 to 0.6 of the silicon oxide spacer 112 b.
It is often that an ion implantation is performed to adjust the characteristics, for example, the channel effect or the threshold voltage, of a device such as a metal-oxide semiconductor (MOS) formed on the substrate 100 subsequently. The pad oxide layer 102 b can thus act as a protection or barrier layer to protect the substrate 100 from being damaged by the implanted ions. In FIG 1I, the pad oxide layer is removed by wet etching or plasma etching. Since the material of the silicon oxide spacer 112 b and the pad oxide layer 102 is the same, a part of the silicon oxide spacer 102 b is consequently removed and resulted as denoted by 102 c.
In FIG. 1J, using a prior technique, a gate oxide layer 114 is formed, and a gate material layer 116 is formed on the gate oxide layer 116.
Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5733383 *||Dec 13, 1994||Mar 31, 1998||Micron Technology, Inc.||Spacers used to form isolation trenches with improved corners|
|US5801082 *||Aug 18, 1997||Sep 1, 1998||Vanguard International Semiconductor Corporation||Method for making improved shallow trench isolation with dielectric studs for semiconductor integrated circuits|
|US5817566 *||Mar 3, 1997||Oct 6, 1998||Taiwan Semiconductor Manufacturing Company, Ltd.||Trench filling method employing oxygen densified gap filling silicon oxide layer formed with low ozone concentration|
|US5882983 *||Dec 19, 1997||Mar 16, 1999||Advanced Micro Devices, Inc.||Trench isolation structure partially bound between a pair of low K dielectric structures|
|US5918131 *||Oct 30, 1997||Jun 29, 1999||United Microelectronics Corp.||Method of manufacturing a shallow trench isolation structure|
|US5960298 *||Jul 11, 1997||Sep 28, 1999||Lg Semicon Co., Ltd.||Method of fabricating semiconductor device having trench isolation structure|
|US6005279 *||Dec 18, 1997||Dec 21, 1999||Advanced Micro Devices, Inc.||Trench edge spacer formation|
|US6017800 *||Dec 12, 1997||Jan 25, 2000||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device and method of fabricating thereof|
|US6054343 *||Jan 20, 1999||Apr 25, 2000||Texas Instruments Incorporated||Nitride trench fill process for increasing shallow trench isolation (STI) robustness|
|US6084276 *||Jun 22, 1999||Jul 4, 2000||International Business Machines Corporation||Threshold voltage tailoring of corner of MOSFET device|
|JPH0897277A *||Title not available|
|JPH04111312A *||Title not available|
|JPH10199875A *||Title not available|
|TW344120B *||Title not available|
|TW345721B *||Title not available|
|1||*||JD 322100 A Abstracts of Research Disclosure Kenneth Masons Publications, Industrial Opportunites, 1991.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6649489 *||Feb 13, 2003||Nov 18, 2003||Taiwan Semiconductor Manufacturing Company||Poly etching solution to improve silicon trench for low STI profile|
|US6737688 *||Dec 30, 2002||May 18, 2004||Hynix Semiconductor Inc.||Method for manufacturing semiconductor device|
|US7235856 *||Feb 2, 2000||Jun 26, 2007||Micron Technology, Inc.||Trench isolation for semiconductor devices|
|US7244660 *||Oct 31, 2005||Jul 17, 2007||Spansion Llc||Method for manufacturing a semiconductor component|
|US7615494 *||Dec 28, 2006||Nov 10, 2009||Hynix Semiconductor Inc.||Method for fabricating semiconductor device including plug|
|US7879737 *||Feb 1, 2011||Samsung Electronics Co., Ltd.||Methods for fabricating improved gate dielectrics|
|US8350321 *||Jun 29, 2009||Jan 8, 2013||Hynix Semiconductor Inc.||Semiconductor device having saddle fin transistor and manufacturing method of the same|
|US8530327||Aug 31, 2011||Sep 10, 2013||Wafertech, Llc||Nitride shallow trench isolation (STI) structures and methods for forming the same|
|US9035418||Aug 19, 2013||May 19, 2015||Wafertech, Llc||Nitride shallow trench isolation (STI) structures|
|US20030211683 *||Dec 30, 2002||Nov 13, 2003||Kim Jong Su||Method for manufacturing semiconductor device|
|US20070099430 *||Oct 31, 2005||May 3, 2007||Spansion Llc.||Method for manufacturing a semiconductor component|
|US20070114592 *||Nov 21, 2005||May 24, 2007||Intel Corporation||Method of forming non-volatile memory cell using spacers and non-volatile memory cell formed according to the method|
|US20080064221 *||Dec 28, 2006||Mar 13, 2008||Hynix Semiconductor Inc.||Method for fabricating semiconductor device including plug|
|US20100219467 *||Sep 2, 2010||Hynix Semiconductor Inc.||Semiconductor device having saddle fin transistor and manufacturing method of the same|
|US20110003455 *||May 24, 2010||Jan 6, 2011||Woong-Hee Sohn||Methods for fabricating improved gate dielectrics|
|U.S. Classification||438/424, 257/397, 438/296, 257/E21.546, 438/427, 257/510|
|Dec 4, 1998||AS||Assignment|
Owner name: VANGUARD INTERNATIONAL SEMICONDUCTOR CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TSENG, HORNG-HUEI;HSU, HUEI-WEN;REEL/FRAME:009639/0170
Effective date: 19981116
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