Verification and Analysis Software Tools
by Uwe Gläser
In the project VAN (Verification and Analysis Software Tolls), tools and algorithms have been developed to support hardware testing, circuit analysis and formal verification for hardware and software. These new methods are partly based on topological algorithms and partly on integrated topological and symbolic approaches.
Three tools are available for transfer:
- VERIFY - Formal verification by equivalence checking. VERIFY is a method based on graph-algorithms which can check the functional equivalence of two similar sequential circuits. VERIFY was developed in cooperation with the University of California at Santa Barbara. It can be applied to more complex designs than other competitive tools since it does not rely on symbolic techniques.
- RADAR - Automatic optimization of synchronous sequential logic. RADAR is based on the redundancy addition and removal method. It can optimize logic in its sequential behaviour, state coding can be changed within the optimization. RADAR was also developed in cooperation with the University of California at Santa Barbara. VERIFY and RADAR can handle circuits up to 100,000 gates.
- FOGBUSTER Automatic test pattern generation (ATPG) to support the production-test of hardware. Starting from a graph algorithm-based approach, the FOGBUSTER-algorithm was developed to handle ATPG in synchronous sequential circuits. FOGBUSTER has proved to be fast and efficient. It can handle designs with about 10,000 gates.
Free evaluation and research licenses as well as payable licenses for commercial use are available.
Uwe Gläser - GMD
Tel: +49 2241 14 2875