According to Tom’s Hardware the software can pack eight double precision or sixteen single precision floating-point numbers, or eight 64-bit integers, or sixteen 32-bit integers within the 512-bit vectors. This means you can process twice the number of data elements of the AVX/AVX2 with a single instruction and four times that of SSE.
Intel AVX-512 has 32 vector registers each 512 bits wide, eight dedicated mask registers. This means that there are 512-bit operations on packed floating point data or packed integer data. This allows for embedded rounding controls, broadcast,floating-point fault suppression, and memory fault suppression.
Tom notes that the 32 ZMM registers represent 2K of register space. Intel AVX-512 will be seen in the Intel Xeon Phi code name Knights Landing, and will also be supported by some future Xeon processors scheduled to be introduced afterwards.