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With the ever increasing die sizes and the accompanied increase in the average global interconnect length, delay-optimal-routing and buffer-insertion techniques are significantly straining the power budget of modern ICs. To mitigate the impact of the power consumed by the interconnects and buffers, a power-efficient multipin routing technique is proposed in this paper. The problem is based on a graph representation of the routing possibilities, with the objective of identifying the minimum power path between the interconnect source and set of sinks. The technique is tested by applying it to the International Symposium on Physical Design and IBM benchmarks to verify the accuracy, complexity, and solution quality. Results obtained indicate that an average power saving as high as 32% for the 130-nm technology is achieved with no impact on the maximum chip frequency.