> Hi All,
> I wonder if someone can briefly illustrate the pros and cons of using
> Active low signals versus Active High signals.
> - Form both views: a chip design and a board level design
When interconnecting multiple components (especially FPGAs), output enables
and other interchip control signals are usually defined as active low. This is
because during power-up or recovering from error/reset conditions most
components pull their outputs high with a weak pullup, thus putting these
signals in an inactive state.
> - From the Drivers technology selection.
Not exactly sure what you mean, but if you are using an open drain type
driver (GTL, BTL) control signals should be active low (for the reasons
> - From a Connection view:
> (a) in case of a piont to point connection.
> (b) multi-node connection.
As D.C. said, a signal has to meet SI and timing restrictions no matter if it
is going low to high or high to low, so in this case polarity doesn't make a
> Kassem M. Abdallah
> HW Engineer
> EMC Corp. Hopkinton, MA
**** To unsubscribe from si-list: send e-mail to firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****