|Publication number||US7525304 B1|
|Application number||US 11/748,207|
|Publication date||Apr 28, 2009|
|Filing date||May 14, 2007|
|Priority date||May 14, 2007|
|Publication number||11748207, 748207, US 7525304 B1, US 7525304B1, US-B1-7525304, US7525304 B1, US7525304B1|
|Inventors||Yiping Feng, Jianou Shi, Xiafang Zhang|
|Original Assignee||Kla-Tencor Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (14), Classifications (7), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to a method for in-line testing of field capacitance in integrated circuit structures.
As integrated circuits have continued to shrink in size, structures and materials that once were adequate for certain purposes, have become inadequate for their designated purposes. As the term is used herein, “integrated circuit” includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III-V compounds like gallium arsenide, or mixtures of such materials. The term includes all types of devices formed, such as memory and logic, and all designs of such devices, such as MOS and bipolar. The term also comprehends applications such as flat panel displays, solar cells, and charge coupled devices.
For example, the small-featured traces and other electrically conductive structures of integrated circuits need to be adequately electrically insulated one from another. As feature size has decreased, and circuit speeds have increased, the dielectric materials used for electrical isolation are not adequate for the task, and tend to exhibit capacitance and other effects between the electrically conductive features. These effects tend to induce cross-talk and slow the switching speeds of the circuits.
To resolve issues such as these, new dielectric materials with lower capacitance values—so-called low-k materials—have been used in the fabrication of integrated circuits. Unfortunately, after these materials are deposited, subsequent processing of the integrated circuit might alter the capacitance of these low-k materials. For example, the effective k value of low-k films has been observed to change after etching and ashing processes.
Capacitance is traditionally tested in a final test of electrical parameters at the end of the fabrication cycle. However, it can take up to a month or more to complete the fabrication process and perform the tests. If the issues described above in regard to effective k value or uniformity are detected, the substrates bearing the integrated circuits having the problem may need to be scrapped, possibly along with all of the other substrates that are in the line.
What is needed, therefore, is a system that overcomes problems such as those described above, at least in part.
The above and other needs are met by a method for determining an effective capacitance of a dielectric material, by forming first and second asymmetrical electrodes entirely within a field of the dielectric material, where the first electrode, the second electrode, and the field of the dielectric material are co-planar, neither the first electrode nor the second electrode are either electrically connected to ground or to each other, applying a first charge Q on the first electrode, measuring a first voltage change V1 on the first electrode, measuring a second voltage change V2 on the second electrode, depositing a second charge Q′ on the second electrode, measuring a third voltage change V3 on the first electrode, measuring a fourth voltage change V4 on the second electrode, calculating a first ground capacitance Cg1 by Cg1=(V2Q′−V4Q)/(V2V3−V1V4), calculating a second ground capacitance Cg2 by Cg2=(V3Q−V1Q′)/(V2V3−V1V4), and calculating an inter-electrode capacitance Cie by Cie=V3Cg1/(V4−V3)=V2Cg2/(V1−V2).
According to another embodiment of the invention, there is described a method for determining an in-plane effective capacitance of a dielectric material, by forming first and second symmetrical electrodes entirely within a field of the dielectric material, where the first electrode, the second electrode, and the field of the dielectric material are co-planar, neither the first electrode nor the second electrode are either electrically connected to ground or to each other, applying a first charge Q on the first electrode, measuring a first voltage change V1 on the first electrode, measuring a second voltage change V2 on the second electrode, calculating a ground capacitance Cg by Cg=Q/(V1+V2), and calculating an inter-electrode capacitance Cie by Cie=V2Q/(V1 2−V2 2).
Further advantages of the invention are apparent by reference to the detailed description when considered in conjunction with the figures, which are not to scale so as to more clearly show the details, wherein like reference numbers indicate like elements throughout the several views, and wherein:
The various embodiments of the present invention use a new test structure and method to measure effective capacitance or k value. This is accomplished with a planar structure, rather than with a standard stacked structure that is typically used for capacitance measurement or charge storage, where a dielectric layer is deposited between an overlying electrically conductive layer and an underlying electrically conductive layer. Instead, the planar test structure 12 described herein, as depicted in
As depicted in
The structure 12 preferably has at least one first pad 14 a and at least one second pad 14 b. These pads are connected to finger structures 16 a and 16 b, respectively. The finger structures 16 a and 16 b are interlaced, or in other words interdigitated, so as to alternate one finger 16 a, then one finger 16 b, then another finger 16 a, and then another finger 16 b, and so forth. The number of fingers 16 a and 16 b as depicted in
Further, the configuration of the fingers 16 a and 16 b as depicted in
The fingers 16 a and 16 b have, in one embodiment, a length of about fifty microns, and form fields of low-k material 22 that also have lengths of about fifty microns. In one embodiment, the pads 14 a and 14 b are symmetrical, meaning that the pad or pads 14 a are the same size and the same number as the pad or pads 14 b. In one embodiment, there is one pad 14 a that is about fifty microns by about fifty microns square, and one pad 14 b that is about fifty microns by about fifty microns square. This would be a symmetrical configuration, as depicted in
An asymmetrical configuration is one in which there are a different number of pads 14 a and 14 b, or the same number of pads, but the pads are of different sizes, or both. If the surface area of the pad or pads 14 a is more than insignificantly different than the surface area of the pad or pads 14 b, then it is an asymmetrical configuration. The structure 12 depicted in
With reference now to the asymmetrical configuration of
An effective k value for the material 22 in either case, be it symmetrical or asymmetrical, can be calculated from the capacitance values as derived above, and the critical dimension Cd 18 between the fingers 16 a and 16 b of the structure 12, as described above. Thus, a planar structure 12 has been described that can be used as soon as it is formed, and at any time thereafter, to measure the effective k value of a field of dielectric material 22.
The charges Q and Q′ can be applied in a variety of different ways, be they direct-contact or non-contact. Similarly, the differential voltages can be sensed in a variety of different ways, be they direct-contact or non-contact. For example, the charges Q and Q′ can be applied using non-contact corona-based micro QV technology. The charges Q and Q′ can also be applied using an electron beam or ion beam. The voltages can be sensed using the same technologies. Of course, the charges can be applied and voltages can be measured using direct contact methods, such as physical probes. The voltages can also be measured using a work function sensor that is at least one of a Kelvin probe, a Monroe probe, an electrostatic force probe, and an atomic force measurement probe. The voltages can be measured at frequencies from about zero kilohertz to about one kilohertz.
Multiple voltage measurements can be made for each of the voltage measurements V1, V2, V3, and V4, and then the multiple readings for each value can be distilled to a single value in a variety of different ways, such as by averaging the multiple readings. For example, eight readings can be taken for V1, and then the eight readings added together to form a total, which is then divided by eight to determine the final value that is used for V1. Other methods could also be used to collect data and discard or otherwise reduce the effect of erroneous data points.
The foregoing description of preferred embodiments for this invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiments are chosen and described in an effort to provide the best illustrations of the principles of the invention and its practical application, and to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.
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|International Classification||G01R31/28, G01R31/26|
|Cooperative Classification||G01R27/2605, G01R31/2648|
|European Classification||G01R27/26B, G01R31/26P|
|May 14, 2007||AS||Assignment|
Owner name: KLA-TENCOR TECHNOLOGIES CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FENG, YIPING;SHI, JIANOU;ZHANG, XIAFANG;REEL/FRAME:019289/0863;SIGNING DATES FROM 20070426 TO 20070514
|Oct 29, 2012||FPAY||Fee payment|
Year of fee payment: 4