|Publication number||US8018704 B2|
|Application number||US 11/466,741|
|Publication date||Sep 13, 2011|
|Filing date||Aug 23, 2006|
|Priority date||Aug 23, 2006|
|Also published as||US20080055808|
|Publication number||11466741, 466741, US 8018704 B2, US 8018704B2, US-B2-8018704, US8018704 B2, US8018704B2|
|Inventors||William Andrew Burkland, Adolfo A. Garcia|
|Original Assignee||Micrel, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (2), Classifications (5), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to circuit breakers in power controllers for sensing overcurrent faults and disconnecting power to electronic equipment in the case of an overcurrent condition.
A conventional power controller integrated circuit controls a power transistor to couple or decouple a power supply from a load to be powered. The power controller typically detects overcurrent faults, detects voltage levels, detects externally-generated control signals such as an enable signal, and senses other conditions to determine whether to couple or decouple the power supply to or from the load. The overcurrent circuit acts like a circuit breaker, where the current through the transistor is detected and, if it is above a threshold level, the power controller turns off the transistor.
Since the current threshold may be momentarily exceeded due to a current surge when the load is first powered up or due to some other transitory reason, the power controller typically includes a delay circuit which allows the current to exceed the threshold for a short period of time without tripping the circuit breaker. If the overcurrent period exceeds the delay time, the power controller turns off the transistor, and the system must be reset, after the fault is fixed, before the transistor is turned on again. This avoids nuisance faults.
It is important that the delay time during which the overcurrent exists does not exceed a time that will damage the transistor or damage the load or other components. Accordingly, a maximum time for the delay must not be exceeded.
Some power controllers include an autoretry circuit that automatically resets the circuit breaker, after a delay, one or more times after the circuit breaker is tripped in case the previous overcurrent situation has been cleared up. It is important that the reset of the transistor does not occur too soon after the initial shutting off of the transistor since the transistor may heat up and become damaged due to being repeatedly turned on during an overcurrent condition. The ratio of the time that the transistor is on during the overcurrent versus the total cycle time (i.e., the duration of the time that the transistor is on during the overcurrent plus the delay between the autoretry attempt) is referred to as a duty cycle of the transistor during the overcurrent. The duty cycle must not exceed a maximum in order to prevent damage to the transistor.
The delay circuits in the circuit breakers and autoretry circuits may be analog or digital. Analog delay circuits set the delay time by selecting the value of a capacitor that is charged between an initial voltage (e.g., 0 volts) and a threshold voltage. A larger capacitor increases the tripping time. Such capacitors are external to the power controller package and provide flexibility to the user. The analog delay may also be set by selecting an external resistor in addition to the capacitor to set the time constant. Digital timers may be integrated on the same chip as the power controller and are thus inexpensive, but provide no flexibility to the user since the delay time is fixed.
When using an analog timer, the user may err and use a capacitor that provides too much delay and damages the transistor in an overcurrent condition. Similarly, the user may use a capacitor in the analog timer for the autoretry that results in the transistor exceeding its maximum duty cycle for the overcurrent.
What is needed is a technique to prevent the transistor controlled by a power controller being damaged due to a sustained overcurrent or a duty cycle that is too high.
A circuit breaker for a power controller is described where an analog timer and a digital timer are provided in parallel. The digital timer is implemented entirely on the power controller chip so adds no cost to the power system. The digital timer provides a maximum delay during an overcurrent condition to ensure the transistor will not be damaged. The analog timer allows the user to select an external capacitor or resistor to provide a delay time that is shorter than the time provided by the digital timer. The user may disable the analog timer by not using a capacitor and connecting a terminal to ground. Accordingly, the power controller retains all the flexibility of an analog timer but prevents the overcurrent exceeding a maximum time limit.
An autoretry circuit is also included in the power controller which prevents the duty cycle from exceeding a maximum. The autoretry timer is a digital timer that uses the same oscillator as the digital timer for the circuit breaker. Both digital timers are counters, with the autoretry counter having a higher count than the circuit breaker digital timer before triggering. Since the autoretry timer is a fixed time and runs off the same oscillator as the circuit breaker digital counter, a maximum duty cycle of the transistor is enforced which cannot be altered by the user.
The remainder of the circuit is primarily for acting as a circuit breaker in the event an overcurrent through the transistor 14 is sensed.
The current to the load passes through a low value sense resistor 20 (e.g., 0.02 ohms), connected in series with the transistor 14. The sense resistor 20 and transistor 14 will typically be external to the power controller integrated circuit package to give the user flexibility in choosing a suitable transistor 14. One terminal of the resistor 20 is connected to a comparator 22, and the other end of the resistor 20 is connected to an offset voltage 24. In the example of
The high output of the comparator 22 is applied to one input of a NAND gate 26. The high output of the comparator 22 also starts an analog timer 28 and a digital timer 30.
The analog timer 28 starts by closing a switch that couples a fixed current source (e.g., 2.5 microamps) to a timing capacitor 32. A comparator in timer 28 compares the capacitor voltage to a reference (e.g., 1.25 v). When the capacitor voltage exceeds the reference, the output of the timer goes high. The timer 28 is turned off and the capacitor is discharged when a logical 0 is applied to the start input of the timer 28. The larger the capacitor 32, the longer the delay before the timer 28 trips. An optional resistor 34 may be connected to the timer 28 to change the trip level of the timer 28. If a resistor 34 is also used, increasing the value of the resistor increases the delay. In one embodiment, the timer 28 delay in milliseconds equals C (in microfarads)×R (in kohms)×5. The analog timer 28 will typically be set to be less than 40 ms. All portions of the analog timer 28 except for the capacitor 32 and resistor 34 are on the power controller integrated circuit chip. The timer 28 circuitry may be conventional.
The digital timer 30 is a counter that increments every clock pulse. The clock pulses are supplied by an oscillator 36. The entire digital timer 30 and oscillator are on the power controller integrated circuit chip. The timer 30 and oscillator 36 circuitry may be conventional. An example of a suitable delay time for the digital timer is 40 ms, equivalent to 4092 clock cycles supplied by oscillator 36. After the timer 30 times out, its output will generate a logical high pulse. The timer 30 is off when the signal at its start terminal is low.
The outputs of both timers 28 and 30 are applied to an OR gate 38, so the two timers operate in parallel, and the one that times out first controls the circuit breaker function. The output of the OR gate 38 is connected to the second input of the NAND gate 26. Upon an overcurrent tripping the comparator 22, the output of the NAND gate 26 will be a logical 1 until one of the timers 28 or 30 times out, and will then become a logical 0 after the first timer times out, assuming the overcurrent still exists.
The output of the NAND gate 26 is connected to an input of a NOR gate 40. A second input into the NOR gate 40 is a logical 0 when an externally generated enable signal to the power controller chip is high and there is no power-on-reset (POR) pulse generated internal to the power controller. The POR pulse is generated when the power controller has adequate power initially applied to it. Conversely, the second input to the NOR gate 40 is a logical 1 if either the enable signal has been deasserted or the POR pulse is generated.
The enable signal is coupled to the input of an inverter 42 whose output is connected to an OR gate 44. The POR signal is also connected to the OR gate 44. The output of the OR gate 44 is coupled to the second input of the NOR gate 40. The external toggling ON-OFF-ON of the enable terminal of the power controller acts as a signal to clear all fault flags (including resetting the circuit breaker).
Assuming the power controller is enabled and there is no POR pulse, the output of the NOR gate 40 will be: Condition 1) a logical 0 after an overcurrent has been detected but before either timer 28 or 30 has timed out; or Condition 2) a logical 1 after an overcurrent has been detected and one of the timers 28 or 30 has timed out.
The output of the NOR gate 40 is connected to a set input of an SR flip flop 46, and the output of the OR gate 44 is connected to the reset input of the flip flop 46. Upon Condition 1 occurring, the logical 0 signal output from the NOR gate 40 will not affect the state of the flip flop 46 since the flip flop 46 had been previously reset upon the power controller starting up. Accordingly, upon Condition 1 occurring, the set signal is a logical 0, and the inverted Q output (identified as /Q in
Upon a first of the timers 28 and 30 to time out while there is an overcurrent condition, Condition 2 results, where the output of the NOR gate 40 goes high. In this case, the flip flop becomes set, and the /Q output goes low. This logical 0 is applied to the AND gate 18 to cause the AND gate 18 to output a logical 0 and turn off the driver 16 and transistor 14. Power is thus removed from the load.
Since the digital timer 30 is guaranteed to time out at a preset time, not controlled by the user, there is no chance that the user could inadvertently set a damaging delay time by choosing a wrong value for the timing capacitor 32. This avoids damage to the transistor 14 as well as the load. If the user wants a shorter delay time (e.g., 40 ms) then provided by the digital timer 30, the user may use the equations for calculating the analog timer 28 delay time to set the desired delay (e.g., 1-39 ms). The user may disable the analog timer 28 by connecting the timing capacitor terminal to ground.
In another embodiment, an additional current sense comparator having a higher offset voltage than provided by offset voltage 24 is used to detect a larger overcurrent that is clearly a “permanent” fault condition and immediately shuts off the transistor 14. The output of such an additional current sense comparator may be coupled so as to immediately apply a high set signal to the flip flop 46.
The autoretry circuit of
When the autoretry timer 54 times out, its output generates a logical 1 pulse. Its output is connected to the D input of a D flip flop 56, which receives clock pulses from the oscillator 36. The Q output of the D flip flop 56 follows the output of the autoretry timer 54. The Q output is connected to an input of the OR gate 44. A high output of the D flip flop 56 resets the SR flip flop, causing the /Q output of the SR flip flop to be a logical 1. After a clock cycle, the D flip flop 56 changes state, and its inverted Q output (labeled /Q in
The maximum duty cycle of the transistor 14 is thus fixed by the digital timer 28 and autoretry timer 54, where the maximum duty cycle is digital timer 30 delay divided by the combined duration of the digital timer 30 delay and the autoretry timer 54 delay. When it is desired to reduce this maximum duty cycle, the user may set the analog timer 28 to provide a circuit breaker trip time shorter than that provided by the digital timer 30.
Many different types and combinations of logic circuits may be used to implement the invention. The various logic levels described may be opposite logic levels. The entire power controller of
Having described the invention in detail, those skilled in the art will appreciate that, given the present disclosure, modifications may be made to the invention without departing from the spirit of the inventive concept described herein. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.
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|Cooperative Classification||H02H3/087, H02H9/025|
|Aug 23, 2006||AS||Assignment|
Owner name: MICREL, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BURKLAND, WILLIAM ANDREW;GARCIA, ADOLFO A.;REEL/FRAME:018162/0408;SIGNING DATES FROM 20060816 TO 20060821
Owner name: MICREL, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BURKLAND, WILLIAM ANDREW;GARCIA, ADOLFO A.;SIGNING DATESFROM 20060816 TO 20060821;REEL/FRAME:018162/0408
|Mar 13, 2015||FPAY||Fee payment|
Year of fee payment: 4