March 4, 2009
ECE graduate student Siddarth Garg and Professor Diana Marculescu have won a Best Paper Award at the upcoming 10th International Symposium on Quality Electronic Design March 16-18 in San Jose, California.
Their paper is titled "3D-GCP: An Analytical Model for the Impact of Process Variations on the Critical Path Delay Distribution of 3D ICs."
Due to variations in the manufacturing process parameters, nano-scale CMOS integrated circuits (ICs) are subject to increasing uncertainty in their performance characteristics. This paper makes the first attempt to theoretically characterize the impact of process variations on the maximum operational frequency of three dimensional (3D) ICs - an emerging IC packaging technique in which multiple dies are stacked vertically on top of each other and interconnected using through-silicon vias (TSVs).
The analysis reveals that process variations can impact 3D ICs more than their equivalent 2D implementations, a prediction that motivates the need for further research into novel variability mitigation techniques for 3D technology.
A recognition ceremony for authors will be held at a luncheon on March 17 at the conference.
Siddarth Garg and Diana Marculescu