Weighing nanotech’s risk and rewards
Harnessing the exotic properties of materials at the nanoscale promises huge societal benefits, from the production of clean energy to the treatment of deadly diseases.
Analysts see deja-vu chip growth in 2007, before peak in 2008
Analysts surveyed by SST generally reviewed 2006 as a decent year for the semiconductor industry, if you take away a “bloodbath” in microprocessors and a surprising weakness in ASPs.
Turning to an old friend, device engineers are reconsidering germanium
Yhe limitations of silicon are becoming more evident. Since the 90nm technology node, manufacturers have used silicon germanium (SiGe) source and drain regions, silicon carbide (SiC) liners, and other methods to strain the silicon channel.
High-volume full-wafer step-and-flash imprint lithography
S-FIL is a unique method for printing sub-100nm geometries [1-3]. When high-resolution alignment is needed, the S-FIL process uses field-to-field drop dispensing of UV curable liquids for step-and-repeat patterning.
An alternative technology for dose and focus monitoring
CD budget constraints necessitate focus and dose monitoring as standard process procedure.
Assessing the challenges of EUV lithography
It is expected that single-exposure 193nm immersion lithography will reach the ultimate physical limits at the 32nm half-pitch technology node.
Electron Devices Meeting goes 3D, low-power
The 2006 International Electron Devices Meeting in San Francisco, Dec. 10, 13, may be remembered as the start of a trend toward 3D integrated circuits with stacked devices.