In planar NAND cells, to keep interference to an acceptable regime, the charge storage thickness needs to be scaled down to around 5nm (Figure 1a). The charge storage can either be a dielectric layer, a layer of nano-crystals or a conductive floating gate layer (Figure 1b).
Figure 1a: Interference vs. storage node thickness
Figure 1b: Schematics of various planar cell options.
Silicon nitride films are very compatible with the standard silicon processes and traps in silicon nitride can be used as charge storage centers. NAND cell is programmed and erased through Fowler-Nordheim tunneling. In order for the silicon nitride film to be an effective charge trap layer, it needs to trap electrons efficiently during programming, which means the traps need to be shallow traps. This, however, conflicts with retention and lateral charge confinement, which prefer deep traps. Good NAND performance requires at least +6V/-5V program/erase window . SiN, being a dielectric typically has no free electrons that can be removed to achieve the negative NAND cell Vt. Negative cell Vt can be achieved only through hole injection, which either requires much higher erase electric fields or Barrier Engineered Tunnel dielectric . Any dielectric storage has to be able to address these fundamental trade-offs in order to be viable. Alternatively, the material properties of silicon nitride could be engineered to circumvent hole erase by tailoring the silicon/nitrogen ratio.
Metallic nano-crystals as well as silicon nano-crystals have been discussed as options for charge storage layer in the literature. While silicon nano-crystals are more compatible with the standard silicon process, they suffer from the disadvantage of having insufficient electron density of states leading to poor threshold voltage window. On the other hand, metal nanocrystals are free from this limitation due to the much higher density of states available in metal nano-crystals. However, metal nano-crystals are harder to integrate into the standard silicon process due to metal contamination concerns. The metal nano-crystals additionally offer the option of engineering a higher work-function which can be useful in achieving better retention. One key advantage of metal nano-crystals is that it can be very thin in effective thickness compared to silicon nitride trap layer which can help reduce the cell to cell interference.
Thin conductive floating gate for charge storage is another option for the charge storage node. The conductive floating gate could be made of poly silicon, which would be highly compatible with the standard silicon process or could be specially engineered to have the appropriate work functions. One potential advantage for a nano-crystal or dielectric based charge storage over a conductive floating gate cell is that the former systems may be able to act as discrete charge storage nodes (no trap to trap or nano-crystal to nano-crystal charge transport), allowing for process simplification as the trap layer could be continuous between cells and they could also result in significant SILC benefit allowing for tunnel oxide scaling.
Due to the lack of “wrap” planar cell requires the blocking dielectric EOT to be scaled down from ~12nm of ONO to ~68nm while maintaining a low leakage current under the high field conditions of program/erase and low field conditions of retention and disturbs. Most commonly used high-K dielectric has been the Al2
owing to its promise of high band offset (conduction band offset to Si ~2.8eV) and reasonably high dielectric constant. In practice, however, the high conduction band offset has been quite elusive. A systematic scan of various dielectrics such as AlOx, HfOx, ZrOx, DyScOx, TiOx, HfAlOx, HfSiOx, ZrAlOx, ZrSiOx, LuAlOx, GdOx and their combinations was conducted to arrive at the right blocking dielectric.
The control gate (CG) electrode for planar cell applications needs to have high work function (WF) to prevent back injection from the control gate during erase operation. Again a systematic evaluation of various films including TiN, WN, TaN and TaSiN was carried out to identify the right material.