|Número de publicación||US4594560 A|
|Tipo de publicación||Concesión|
|Número de solicitud||US 06/724,245|
|Fecha de publicación||10 Jun 1986|
|Fecha de presentación||17 Abr 1985|
|Fecha de prioridad||17 Abr 1985|
|Número de publicación||06724245, 724245, US 4594560 A, US 4594560A, US-A-4594560, US4594560 A, US4594560A|
|Inventores||Andrew G. F. Dingwall, Victor Zazzu|
|Cesionario original||Rca Corporation|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citas de patentes (3), Citada por (8), Clasificaciones (14), Eventos legales (7)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
This invention relates to means for biasing an amplifying means at a preselected voltage level.
In many applications, it is desirable that the input and output of an amplifying means be biased at a preselected voltage level in order to optimize its response and/or to attain certain system requirements. For example, where the amplifying means is used to form a comparator, it is desirable to bias the amplifying means midway between the operating potential applied across the amplifying means to enable the comparator to operate over the widest possible range and at a point at which the amplifying means has the highest gain and responds fastest.
However, biasing an amplifying means at its mid-point is problematic, as illustrated by reference to FIG. 1A which shows a complementary inverter operated as a comparator. The inverter includes insulated-gate field-effect transistors (IGFETs) P1 and N1, of P and N conductivity, respectively. The conduction path of P1 is connected between VDD and output terminal 51, the conduction path of N1 is connected between the output terminal 51 and ground, and the gate electrodes of P1 and N1 are connected to an input terminal, 53, to which an input signal VIN is, selectively, capacitively coupled. A feedback switch, SF, is connected between the input and output terminals. When switch SF is closed,--a condition for which the inverter is referred to as being "auto-zero'ed"--the input and output terminals of the inverter are at the same potential.
For symmetric operation, P1 and N1 are designed to be "matched" such that the effective impedance (ZP1) of P1 is equal to the effective impedance of (ZN1) of N1, for like bias conditions. Then, for the auto-zero condition, the transfer characteristic of the inverter is expected to be as shown for waveform A in FIG. 1B, with the quiescent (toggle, or flip) point, Q1, set at VDD /2 .
However, in practice, it is found that, although P1 and N1 are designed to be matched, exact matching of the characteristics of the P-type and N-type devices is difficult to achieve. As a result, the transfer characteristic of a supposedly matched inverter may vary over a relatively wide range with the equivalent impedance of the P-type device being either greater than, or less than, that of the N-type device. For example, for the condition where ZP1 is less than ZN1, for like bias conditions, the transfer characteristic will be to the right of waveform A, as illustrated by waveform B of FIG. 1B and the toggle point Q2 of the inverter is more positive than VDD /2, for the auto-zero condition. Similarly for the condition where ZP1 is greater than ZN1, for like bias conditions, the transfer characteristic lies to the left of waveform A, as illustrated by waveform C of FIG. 1B and the toggle point Q3 of the inverter is then more negative than VDD /2, for the auto-zero condition.
The auto-zero (or self-bias) condition of the inverter establishes the quiescent voltage (VQ) at nodes 51 and 53 against which the input voltage (VIN) to be measured is compared. Thus, when VQ deviates from VDD /2, which is the "supposed" bias point, the maximum symmetrical dynamic range of the amplifier, which is, theoretically, equal to ±VDD /2, is reduced by the amount of the offset.
By way of example, in successive-approximation charge-redistribution analog-to-digital (A/D) converters, a comparator is first biased at some voltage VQ, which is ideally equal to VDD /2. Then, an input voltage (VIN) to be measured and a set of successively smaller test voltages--(i.e., successively smaller fractions of a reference voltage VREF), are applied to the comparator input. Where the comparator is of the type shown in FIG. 1A, the voltage (VB), at node 53, resulting from the application of VIN and the first test voltage, which is typically set at VREF /2, may be expressed as follows:
VB =VQ -VIN +VREF /2 eq. 1
Assume by way of example, that VDD is equal to +5 volts and that VDD /2 and VREF /2 are each equal to 2.5 volts. When VQ is equal to VDD /2, VIN can range between 0 volts and +5 volts without overdriving the input of the comparator and without loss of charge and signal information. As shown in FIGS. 1C, if VIN is equal to 0 volts, VB will rise to +5 volts during the first step of the sequence when VREF /2 is applied, and, as shown in FIG. 1D, if VIN is equal to +5 volts, VB decreases to 0 volts during the first step of the sequence. However, when the bias point (VQ) is offset relative to VDD /2, e. g., VQ is equal to 3.0 volts, the comparator input (VB) is driven positive with respect to VDD for values of VIN less than 0.5 volts. When VB goes positive with respect to VDD, parasitic diode junctions become forward biased and signal information is lost. Similarly, if, for example VQ is equal to 2.0 volts, the input (VB) of the comparator is driven negative with respect to ground for values of VIN more positive than 4.5 volts, resulting in the loss of charge and signal information.
Consequently, it is desirable that the comparator input be precisely centered between the power supply lines for providing maximum symmetrical dynamic range. The problem of centering the bias point of a comparator input was the primary problem faced by Applicants. However, in general, the problem is to be able to set the bias of a comparator input at a preselected voltage level with a high degree of precision.
Accordingly, a circuit embodying the invention includes: (a) an amplifying means comprising an inverter and a controllable variable impedance means, connected in series with the inverter, for shifting the transfer characteristic of the inverter; and (b) control means also comprising an inverter and a controllable variable impedance means similar to that of the amplifying means. The output of the control means inverter is fed back to its controllable variable impedance means for producing a control voltage which is a function of the voltage level applied to the input of the control means inverter and of the characteristics of its inverter and controllable variable impedance means. The control voltage is applied to the controllable variable impedance means of the amplifying means for setting the input and output of the amplifying means inverter, at a voltage level which is substantially equal to that applied to the input of the control means inverter, when the latter is auto-zero'ed. In a particular embodiment of the invention, a bias voltage applied to the input of the control means inverter is made equal to one half the operating voltage applied across the control means, and the voltage produced at the input and output of the amplifying means inverter, when the latter is auto-zero'ed, is substantially equal to that bias voltage.
In the accompanying drawing, like reference denote like components; and
FIG. 1A is a schematic diagram of a prior art comparator circuit;
FIG. 1B is a drawing of transfer characteristics associated with the comparator of FIG. 1A;
FIGS. 1C and 1D are drawings illustrating the application of test voltages to the input node of a centered comparator;
FIG. 2 is a schematic diagram of a comparator circuit embodying the invention; and
FIG. 3 is a drawing of the transfer characteristics of a comparator circuit embodying the invention.
The circuit of FIG. 2 includes a resistive divider network 9, a control voltage generating stage I, a first comparator and amplifying stage II, an amplifying stage III, a binary weighted comparator ladder network 10, a set of control switches 12, and switch means for applying a voltage VIN or a reference voltage VREF to the circuit.
The resistor divider network 9 is comprised of resistors R1 and R2 connected between terminal 11, to which is applied ground potential, and terminal 13, to which is applied a potential, VDD, which is positive with respect to ground. In the discussion to follow, it will be assumed, by way of example, that VDD is equal to 5 volts. The ratio of R1 and R2 may be set at any value to obtain a desired direct current (d.c.) voltage at node 1. When R1 is made equal to R2, the voltage (V1) developed at node 1 is equal to VDD /2. The divider network may be replaced by a rheostat or other variable impedance to generate any other desired d.c. voltage to be applied to node 1.
Stages I, II and III are compound inverting stages. Each stage includes two insulated-gate field-effect transistors (IGFETs)--(Pi1, Pi2)--of P-conductivity type and two IGFETs (Ni1, Ni2) of N-conductivity type, where i represents the order of the stage. Each inverting stage has a signal input terminal (SNi), a control input terminal (CTi), and an output terminal (OTi). The conduction paths of IGFETs Pi1 and Pi2 of each stage are connected in series between power terminal 13 and output terminal OTi and the conduction paths of IGFETs Ni1 and Ni2 are connected in series between output terminal OTi and terminal 11. The gate electrodes of IGFETs Pi1 and Ni1, which function to form a complementary inverter (Ii), are connected to a signal input terminal SNi. The gate electrodes of IGFETs Pi2 and Ni2, which function as controllable variable impedance means, are connected to a control input terminal CTi.
The signal input terminal SN1 of the first stage is connected to node 1, at which is applied the bias voltage level, V1, which is to be reproduced at the inputs of stages II and III when stage II is auto-zero'ed. The output terminal OT1 of stage I is connected to the control input terminals (CT1, CT2 and CT3) of stages I, II and III.
The signal input terminal (SN2) of stage II is connected via conductor 15 to the output node of charge redistribution network 10 whose input nodes are coupled via a switching arrangement 12 to a conductor 7 to which is selectively applied, via a switch SA, either an input signal VIN, or a reference voltage VREF. The output terminal OT2 of stage II is connected to the signal input terminal (SN3) of stage III.
A complementary transistor transmission gate 14 is connected between the signal input terminal (SN2) and the signal output terminal (OT2) of amplifying stage II. Transmission gate 14 includes transistors P14 and N14 having their conduction paths connected in parallel between signal input terminal SN2 and output terminal OT2. Complementary auto zero control signals (AZ and AZ) are applied to the gate electrodes of transistors N14 and P14, respectively. When AZ is high and AZ is low, the signal input and signal output terminals of stage II are connected via a low impedance path and are essentially at the same potential. For this condition, stage II is referred to herein as being "auto-zero'ed".
Applying V1 to the gate electrodes of P11 and N11 of inverter I1 and feeding back the output (OT1) of stage I1 to the gate electrodes of P12 and N12 results in the production of a control (or intermediate bias) voltage (VOT1) which is applied to the control electrodes of P22, N22 of stage II and P32, N32 of stage III. As detailed below, the control voltage (VOT1) ensures that the inputs and outputs of inverters I2 and I3 are driven to a voltage substantially equal to V1 when I2 (and I3) is auto-zero'ed. In any case, the control voltage controls the impedances of the Pi2 and Ni2 IGFETs in Stages II and III so as to center the transfer characteristics of inverters I2 and I3 along the line for which VOTi is equal to VSNi.
It is important to bear in mind that, although the manufacture of IGFETs is well developed and the general characteristics of the IGFETs and like devices is predictable, it is not possible to control the exact characteristic of the IGFETs and like devices. Many variants come into play during the processing of an integrated circuit which affect the exact characteristics of the IGFETs and like devices being manufactured. Although the exact characteristic of a particular device may not be predicted, like devices of like conductivity formed on the same integrated circuit at the same time will, typically, be very similar. Thus, the devices of N-conductivity of like geometry and doping will have similar characteristics to each other and the devices of P-conductivity of like geometry and doping will have similar characteristics to each other. However, variations in the characteristics and responses of the devices of one conductivity type does not necessarily indicate how the characteristics and response of devices of complementary conductivity type will vary. However, as already stated, similar devices of same conductivity formed at the same time, in the same environment, on the same integrated circuit will typically have the same characteristics. Significant use of this fact is relied upon in the manufacture and operation of the circuit of the invention. Thus, in the circuit of FIG. 2, each one of stages I, II and III includes two P-type IGFETs connected in series and two N-type IGFETs of N-conductivity type. The Pi2 transistors are designed to have similar (or proportional) geometries and characteristics. Likewise, the Pi1 IGFETs will be similar (or proportional) to each other, the Ni1 IGFETs will be similar (or proportional) to each other and the Ni2 IGFETs will be similar (or proportional) to each other. Consequently, the IGFETs in one stage or string will be similar (or proportional) to the IGFETs in another stage or string. The devices in one stage need not be identical to the devices in another stage. However, the devices of one stage should be ratioed, geometrically, relative to the devices of another stage, so that their characteristics remain proportional. Thus, the transistors of P-conductivity type in string I have the same or similar geometries to the corresponding P-type transistors in stages II and III. Likewise, the N-type transistors in stage I have the same or similar geometries to the corresponding N-type transistors in stages II and III.
The operation of stage I, which functions as a biasing and control voltage generating stage, and of stage II, which functions as the first amplifying stage is best explained with reference to FIG. 3.
Assume that V1 applied to node 1 and input terminal SN1 increases towards VDD volts, starting from zero volts. The response (VOT1) at OT1 of the first stage I, as a function of V1, is shown in waveform D of FIG. 3. The circled points along waveform D represent actual measurements made on a test circuit. The first inverting stage with its output fed back to the gate electrodes of P12 and N12 may be viewed as a feedback quasi-differential amplifier with a closed loop gain of -1. The stage is highly stable. Any change at the OT1 output produces a feedback signal applied to the gates of P12 and N12 which has a polarity and magnitude to oppose the change. The voltage (VOT1) at the output of stage I is the inverse of V1. But, it also is indicative of the degree of "mismatch", if any, between the P and N devices. For example, for a "matched" condition, (i.e. when ZP11 and ZP12 are equal to ZN11 and ZN12, for like bias conditions) and for V1 equal to VDD /2, the output (VOT1) should equal VDD /2. Consequently, when VOT1 is more positive than VDD /2 for V1 equal to VDD /2, it indicates that the equivalent impedance (ZP11 and ZP12) of P11 and P12 is less than the equivalent impedance (ZN11 and ZN12) of N11 and N12, for like bias conditions. Likewise, a value of VOT1 below VDD /2 indicates that ZP11 and ZP12 and is greater than ZN11 and ZN12 for like bias conditions. Thus, the polarity of VOT1, relative to VDD /2, indicates the polarity of the mismatch (i.e. whether the P devices are "weaker" or "stronger" than the N devices) and the amplitude of VOT1 indicates the extent of the mismatch. VOT1 is then used to control the variable impedance transistors (Pi2 and Ni2) in stages II and III. VOT1 is applied to stage I in a manner to compensate and correct for any deviation in VOT1 relative to VDD /2. Since the devices in stages II and III are similar to those in stage I, and since VOT1 is applied in a similar manner to the control transistors in stages I, II and III, it is evident that VOT1 will compensate for the "mismatch" between the P and N devices.
An examination of waveform D, which is the response of stage I of an actual circuit under test, reveals that, when V1 is equal to 2.5 volts, VOT1 is approximately equal to 2.0 volts. To produce this result, the net equivalent impedance (ZNi1 and ZNi2) of Ni1 and Ni2 must be less than the net equivalent impedance (ZPi1 and ZPi2) of Pi1 and Pi2. However, note that in the circuit of FIG. 2, the VOT1 of 2.0 volts is applied to the gate electrodes of P22 and N22, whose source electrodes are at +5 volts and ground respectively. This causes P22 to be turned-on harder than N22, and, in effect, decreases the impedance between the source of P21 and VDD and increases the impedance between the source of N21 and ground. The control voltage (VOT1) thus acts in a direction to establish a "matched" condition between the P and N devices of each stage. Thus stage I produces a control voltage (VOT1) which when fed to the gate (control) electrodes of the variable impedance transistors (Pi2, Ni2) of stages II and III biases these stages at a desired level. For the case where V1 is made equal to VDD /2, Pi2 and Ni2 of stage II are controlled by VOT1 to make the equivalent impedance (ZP22 and ZP21) of P22 and P21 approximately equal to the equivalent impedance (Zn22 and ZN21) of N22 and N21. For the case where stage II is auto-zero'ed, this results in the input SN2 and output OT2 of stage II being biased midway between the rail potential (VDD and ground). In essence, the Pi2 and Ni2 IGFETs function as controllable impedances connected in series with the sources of the Pi1 and Ni1 IGFETs, respectively functioning as complementary inverters. The net effect of varying the impedances of P22, N22 and P32, N32 is to shift the transfer characteristic of of stages II and III as shown for waveform E of FIG. 3. Clearly, the first stage thus produces a correctly phased control voltage which, when applied to stages II and III, compensates for a mismatch of the components in stages II and III.
The response of stage II at SN2 and OT2, as a function of V1 and VOT1, is shown in waveform F of FIG. 3 for the condition when stage II is auto-zero'ed--i.e. transmission gate 14 is enabled.
Note that for values of V1 ranging between VTN and VDD -VTP the auto-zero'ed voltag'es VOT2 and VSN2 track V1 very precisely; where VTN is the threshold voltage of the N-type devices and VTP is the threshold voltage of the P-type devices. The circled points along waveform F represent measurement made on a test circuit embodying the invention and attest to the high degree of "voltage follower" action produced by the combination of "biasing" stages I and "amplifying" stage II. These results verified the theoretical expectation, as further discussed below.
The operation of the comparator may be briefly explained as follows. As V1 applied to the input SN1 of stage I increases, VOT1 decreases causing VSN2 and VOT2 to increase, when stage II is auto-zero'ed. Thus, VSN2 and VOT2 must follow V1. Recall further that there is a correspondence between the IGFETs in string I and those in string II. Since the control voltage VOT1 applied to P12 and N12 in string I is also applied to P22 and N22 in string II, essentially the same current flowing in string I must flow in string II, (i.e. current mirror action exists). The voltage drops across P22 and N22 must then be substantially equal to the voltage drops across P12 and N12. The source to drain current through P21 and N21 reflects, very approximately, the condition imposed on P11 and N11 by V1. Hence the voltage VSN2 and VOT2 at nodes SN2 and OT2 must be very close to V1, and follow the input bias voltage V1 throughout the range described above.
Where the comparator is used as part of an analog-to-digital converter, it is desirable that VSN2 and VOT2 be set at VDD /2 when an input signal (VIN) to be measured is applied to the comparator input via networks 12 and 10, and, with VDD applied to terminal 13 and ground to terminal 11.
The operation of the comparator is outlined as follows. First, stage II is auto-zero'ed. AZ is driven high and AZ is driven low, and with V1 set to VDD /2, VSN2 and VOT2 will be substantially equal to VDD /2.
After VSN2 and VOT2 are set to VDD /2, the input voltage (VIN) is sampled. Switch 14 is opened by AZ going low and AZ going high. The signal input (SN2) and output (OT2) of stage II remain set at, approximately, VDD /2, a bias point at which the inverter I2 is in its high gain region, can respond the fastest and has the widest operating range.
The input VIN is then applied via switch SA placed in position 1 to conductor 7. Control switches S1, S2, S3, S4, and S5 when placed in position 2 then couple VIN via the charge redistribution capacitors C1-C5 to conductor 15 and via conductor 15 to the signal input SN2 of I2. Following the coupling of VIN, the control switches are selectively driven to apply fractions of VREF to the capacitor inputs. Assuming all of VIN to be applied via the charge distribution capacitors to SN2, node SN2 is driven to a potential VSN2 equal to: VDD /2 +VIN -VREF /2. The actual value of VIN is then determined by a series of successive approximations. This method is well known in the art and need not be detailed. Suffice it to say that the output voltage OT2 of string II is applied to the input of stage III. Stage III is configured identically to string II and is biased in the same manner as a string II. Therefore, when string II is auto-zero'ed and biased b VOT1 to produce VDD /2 at SN2 and OT2, VSN3 of node 3 is also set at, approximately, VDD /2 which is a high gain, high speed point providing the widest range of response. When the signal VIN is applied to string II, an amplified signal is produced at OT2 and applied to SN3. Stage III amplifies the signal further and produces an output at OT3 which is a significantly amplified output signal.
A significant property of a circuit embodying the invention is that it enables the largest possible internal signal level to be used in a single supply voltage system (essentially 5 volts in a 5 volt power supply system). This is in sharp contrast to the prior art conventional auto-zero'ed inverter whose range and speed are significantly reduced.
The precision centering of the bias point of the signal amplifying stage II provides another significant operating advantage. When the voltage at SN2 and OT2 is centered, the transmission gate transistors P14 and N14 have equal voltages applied across their source/drain-to-gate regions. As a result, when turn-on and turn-off clocking signals are applied to transmission gate 14, there is substantial cancellation of the clocking signal transitions. Thus, by using a precisely-centered auto-zero'ed point, the charge injected into the sampled input signal via the `large` auto-zero'ing transmission gate is very well neutralized, since the positive goin9 and negative going gate-signals undergo the same swing relative to VDD /2 operating point.
Still another significant advantage of circuits embodying the invention is that an exact VDD /2 operating point assures symmetrical speed of response with respect to positive and negative inputs.
In a sense, amplifying stage II functions as a differential amplifier stage having two inputs. One input is the reference voltage level (V1) generated at node 1 and "mirrored" via stage I and controllable elements P22, N22 of stage II to the input and output of stage II. The other input is the external signal applied via networks 12 and 10 to the signal input SN2 of stage II. The output OT2 of stage II produces a signal which is the amplified difference of the two inputs.
Another significant feature of the circuit of FIG. 2 is that there is no connection between the signal input (SN1) and the signal output (OT1) of stage 1. There is therefore no mixing of the signal at the output of stage I with the signal at the input to stage I. Thus, a signal source applied to SN1 will not be loaded by and, in turn, will not load the output at OT1. The signal source connected to the input of stage I only sees the extremely high AC and DC impedance present at the gate electrodes of P11 and N11. Thus, while the output OT1 of stage I is fed back to the gate electrodes of P12 and N12, there is no connection to the signal input terminal. As noted above, the feedback of OT1 to P12 and N12, which function as controllable impedance means, causes stage I to have a closed loop gain of (-)1 and provides compensation for mismatch between the components (P11, P12, N11, N12) forming the stage.
The circuit of the invention defines over the "self-biased" complementary transistor amplifier shown in U.S. Pat. No. 3,886,464, assigned to the assignee of the present application, and issued to Andrew G. F. Dingwall, one of the Co-applicants of the present application. In the instant application, the voltage V1 is generated externally to stage I and after being generated by means of a voltage divider network (e.g. 9) or other signal input source (not shown) is direct current connected to the input SN1 of stage I. The externally generated V1 sets the voltage (VOT1)at the output (OT1) of stage I. Due to the similarity in the structure of stages I and II, VOT1 then induces a voltage level at SN2 and OT2 which in effect becomes the operating or biasing point at those two nodes. For V1 equal to VDD /2, stage I is used to drive VSN2 and VOT2 at, or close to, VDD /2 in the absence of an external signal applied to the signal input of stage II.
The control (or intermediate bias) voltage VOT1 produced at the output (OT1) of stage I and applied to the control electrodes of the variable impedance IGFETs [P22, N22 and P32, N32] causes the current level in stage I to be "mirrored" in stages II and III. Furthermore, and of great significance, as a result of the "mirroring" the voltage induced at the input and output of stage II is very nearly equal to that applied to node 1, in the absence of an external signal to SN2.
In the discussion above, it was observed that SN2 and OT2 are biased, at or close to, VDD /2 when the transmission gate 14 is enabled. However, in any event, in the absence of an external signal to SN2, the voltage induced at SN2 and OT2 follows the voltage applied to node 1. This is so, even where the transmission gate 14 is disabled (turned-off).
By way of example, note that stage III with no connection between its signal input and its signal output but with its control input (gates of P32 and N32) connected to OT1, is biased at, or close, to VDD /2 when SN2 and OT2 are driven to VDD /2 by an appropriate control voltage (VOT1) developed in response to V1 being set, or driven, to VDD /2.
|Patente citada||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US3914702 *||1 Jun 1973||21 Oct 1975||Rca Corp||Complementary field-effect transistor amplifier|
|US4038607 *||23 Ago 1976||26 Jul 1977||Rca Corporation||Complementary field effect transistor amplifier|
|US4068182 *||21 Ene 1977||10 Ene 1978||Rca Corporation||Direct-coupled cascade amplifier with automatically adjusted quiescent output signal level|
|Patente citante||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US4748421 *||8 Abr 1987||31 May 1988||Scs Telecom, Inc.||Enhanced class SM power amplifier|
|US4764734 *||18 Dic 1987||16 Ago 1988||Scs Telecom, Inc.||Class SM power amplifier|
|US4935703 *||31 May 1989||19 Jun 1990||Sgs-Thomson Microelectronics, Inc.||Low bias, high slew rate operational amplifier|
|US5329246 *||25 Oct 1993||12 Jul 1994||Motorola, Inc.||Circuit and method of setting a bias point for a single-ended ampliifier during power-up|
|US6972620||19 Feb 2004||6 Dic 2005||Optical Communication Products, Inc.||Post amplifier array integrated circuit|
|US7847629 *||22 Ene 2009||7 Dic 2010||Mediatek Inc.||Sample-and-hold amplifiers|
|US20090195315 *||22 Ene 2009||6 Ago 2009||Mediatek Inc.||Sample-and-hold amplifiers|
|EP0414888A1 *||9 Mar 1990||6 Mar 1991||Synaptics, Inc.||Synaptic element and array|
|Clasificación de EE.UU.||330/296, 330/277, 330/51, 330/264, 330/267|
|Clasificación internacional||H03K17/687, H03F1/30, H03F3/18, H03M1/38, H03F3/30, H03K5/08, H03F3/20|
|17 Abr 1985||AS||Assignment|
Owner name: RCA CORPORATION, A CORP OF DE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:DINGWALL, ANDREW G. F.;ZAZZU, VICTOR;REEL/FRAME:004427/0796
Effective date: 19850416
|30 Sep 1986||CC||Certificate of correction|
|22 Sep 1989||FPAY||Fee payment|
Year of fee payment: 4
|3 Dic 1993||FPAY||Fee payment|
Year of fee payment: 8
|30 Sep 1997||FPAY||Fee payment|
Year of fee payment: 12
|28 Sep 1999||AS||Assignment|
Owner name: INTERSIL CORPORATION, FLORIDA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HARRIS SEMICONDUCTOR PATENTS, INC.;REEL/FRAME:010247/0161
Effective date: 19990813
|8 Nov 1999||AS||Assignment|
Owner name: CREDIT SUISSE FIRST BOSTON, AS COLLATERAL AGENT, N
Free format text: SECURITY INTEREST;ASSIGNOR:INTERSIL CORPORATION;REEL/FRAME:010351/0410
Effective date: 19990813