|Publication number||US4956766 A|
|Application number||US 06/759,002|
|Publication date||Sep 11, 1990|
|Filing date||Jul 25, 1985|
|Priority date||Jul 25, 1985|
|Also published as||CA1262777A, CA1262777A1, DE3670161D1, EP0213306A1, EP0213306B1|
|Publication number||06759002, 759002, US 4956766 A, US 4956766A, US-A-4956766, US4956766 A, US4956766A|
|Inventors||Dhirendra Dhopeshwarkar, Scott A. Hightower, Mac A. Mathis, John W. Mehl|
|Original Assignee||International Business Machines Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (20), Non-Patent Citations (10), Referenced by (6), Classifications (12), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to operator controlled computer systems, especially those systems which include provision for insertion/removal of one or more memory cartridges including read only storage and/or random access memory.
Computer systems are used for a wide variety of tasks and are usually directed by an operator. It is now common in the computer industry to provide systems which include provision for the insertion/removal of memory cartridges, wherein the cartridges are either read only storage or read/write storage, or both. Examples of such systems include Wenninger et al U.S. Pat. No. 3,971,925; Hamano et al U.S. Pat. No. 4,220,991; Housey, Jr. U.S. Pat. No. 4,385,366; Takahashi et al U.S. Pat. No. 4,419,738; Lou U.S. Pat. No. 4,454,591 and Daniels, Jr. U.S. Pat. No. 4,481,587.
Wenninger et al for example provides an Adaptable Programmed Calculator with a provision for plug in memory modules. These plug in ROMs can contain programs which can be executed by the user from the keyboard. Hamano deals with electronic cash registers which accept plug in random access (read/write) cartridges. Housey, Jr. describes a programmable device in which memory modules are selectively connected (such as by a plug in cartridge) read only memories to personalize the device. Takahashi describes a system in which a plug in read/write memory is used to transfer data to a dedicated read/write memory in an electronic cash register. Lou describes an interface system for bus line control in an electronic calculator which employs, in addition to fixed memory modules, plug in memory modules.
Finally, Daniels, Jr. describes an apparatus for providing interchangeable keyboard functions, which apparatus includes insertable memory modules.
In some systems in which read only or read/write memory can be inserted/removed, operating instructions require that the insertion/removal be accomplished when the system is powered down, an example of such a system is the last-mentioned Daniels, Jr. patent. He describes (see col. 8, lines 53 et seq) that after ROM insertion is effected, the "user then turns the scale 112 on by supplying power thereto". Video games and the PCjr are other examples of systems which include memory cartridges which can be inserted or removed, but in which the insertion/removal is effected when the system is powered down. In many cases, however, while the insertion/removal of the memory cartridge effects a reset operation, data is to be retained across this reset; that is, data stored prior to the reset is to be retained so that it can be used after the reset. In other systems, or other applications of the same systems, there is a desire to maintain the system powered up even though a memory cartridge may be inserted/removed. We have found that the insertion/removal of a cartridge can, in response to the electrical disturbances caused by the insertion/removal, produce unwanted changes and/or erroneous operations. The insertion/removal of an electrical component will, by reason of contact bounce and similar phenomena, produce undesired changes in electrical voltages on the conductors connected thereto. These undesired voltage changes can be catastrophic. For example, the undesired voltage changes may alter a word on a data or address bus which can result in:
execution of an incorrect instruction; or
access of an incorrect memory address (for either a read or a write operation).
The consequences of noise on a data or address bus has been recognized in the prior art, see Hartlipp et al U.S. Pat. No. 3,548,177; Shutler U.S. Pat. No. 3,548,176 and Carnevale U.S. Pat. No. 3,548,178. In these patents, a noise detector is provided in the computer system which, in the presence of noise, initiates some action to inhibit or minimize the consequences of the noise. These references are not related to memory cartridges which can be inserted/removed, require the addition of noise detector hardware, and may slow down machine execution
In contrast the present invention recognizes that if the noise can be isolated, the harmful effects can be limited or eliminated. The present invention relates to a computer system which includes provision for memory cartridges which can be inserted/removed and includes at least two separate buses, wherein each bus may include address conductors, data conductors, and control conductors. The first of these two buses is dedicated to the fixed or immovable components which for example includes a central processing unit, read/write memory and read only storage, and may also include additional peripheral equipment such as input apparatus or output apparatus. The second or cartridge bus is the bus to which a memory cartridge is connected when the memory cartridge is inserted, and from which the memory cartridge is disconnected when a memory cartridge is removed. Obviously the system bus and the cartridge bus cannot be entirely divorced, since if that were the case the CPU could never obtain access to any memory cartridge. Rather, isolating logic is coupled between the system bus and the cartridge bus, the isolating logic provides isolation except when access is required to address space which resides on the cartridge bus. To the extent that the isolating logic decouples the cartridge bus from the system bus; the noise on a cartridge bus will not be reflected on the system bus. It is then only necessary to require that when a memory cartridge is being inserted/removed, that the isolating logic is controlled so as to maintain isolation between the cartridge bus and the system bus. In accordance with the invention the isolation is maintained by the presence of an idle loop which does not require access to the cartridge bus.
In a particular embodiment of the invention the computer system which includes provision for plug in memory cartridges may be a typewriter or word processor. In systems of this sort, the system is executing tasks (operating) only in response to operator requests For example the operator may be inserting text into read/write memory, this requires operator actuation of an input device such as a keyboard; alternatively the operator may request the printing of text from read/write memory, and this too requires operator action to initiate the printing. The invention is implemented in such a typewriter or word processor by providing the program with an idle loop which is operative in the absence of execution of a task requested by an operator. The idle loop does not require access to the cartridge bus and thus the isolation is effective during execution to decouple system and cartridge buses. During this period of time the operator can insert/remove memory cartridges without affecting the system components coupled to the system bus since the decoupled state prevents any noise present on the cartridge bus from reaching the system bus. This operation is assured by instructing the operator that cartridge removal/inserted is only effected when operator initiated commands are not being executed. Since the operator's attention would normally be directed to memory cartridge insertion/removal, under normal circumstances operator invoked commands would not be executed simultaneously with cartridge insertion/removal.
The invention can be employed by providing the system ROS with a program which includes the idle loop, and which provides for the appropriate control of the isolating logic to decouple the cartridge and the system bus except during those times when apparatus coupled to the cartridge bus is invoked. An alternative scheme, which does not require the system ROS to include the idle routine can be effected by recognizing that in many systems the program stored in the system ROS is not executed from the ROS itself. Rather, in those systems initial program steps transfer the program from the system ROS to system RAM, and the program is executed out of RAM. Accordingly, in order to prevent disturbances occasioned by memory cartridge removal, the idle routine may be contained in the memory cartridge itself. Here, cartridge insertion necessarily requires that the system be powered down. When the system is powered up, the idle routine from the memory cartridge itself is transferred to system RAM. The idle routine thus is executed out of system RAM and provides for the appropriate isolation so that on memory cartridge removal, the isolation ensures the decoupling of the cartridge bus and system bus.
Thus in accordance with one aspect, the invention provides, in a computer system arranged to perform tasks initiated at operator request, which system includes a central processor and main memory unit connected by a system bus, and in which at least some of said tasks require additional memory cartridges, a method of inhibiting errors caused by the insertion/removal of a memory cartridge, said method comprising the steps of:
(a) providing a cartridge bus to which memory cartridges are connected/disconnected on insertion/removal,
(b) providing a controllable isolation between said system bus and said cartridge bus, and
(c) providing an idle loop for said central processor effective except at times when an operator requests a task to be performed, which idle loop does not provide for access to said cartridge bus.
In another aspect, the invention provides in a computer system arranged to perform tasks initiated at operator request, which system includes a central processor and a main memory interconnected by a system bus and in which at least some of said tasks require additional memory cartridges, apparatus for inhibiting errors caused by the insertion/removal of a memory cartridge. The apparatus includes a cartridge bus associated with apparatus for connecting/disconnecting memory cartridges to the cartridge bus on insertion/removal. The apparatus further includes a controllable isolation logic which is coupled between the system bus and the cartridge bus for isolating the system bus and the cartridge bus except when access is required to the cartridge bus. Finally, the apparatus includes an arrangement for limiting the central processor from execution on the system bus unless the operator requests a task to be performed.
The present invention will be further described in the following portions of this specification when taken in conjunction with the attached drawings in which like reference characters identify identical apparatus and in which:
FIG. 1 is a block diagram of a computer system which includes provision for insertion/removal of memory cartridges;
FIG. 2 is an embodiment of software routines implementing the invention.
FIG. 1 shows an example of a computer system which includes memory cartridges which may be inserted and removed. More particularly, the computer system 10 includes a fixed series of components including CPU 100, ROS 105, RAM 110, an input device 130 and an output device 140. All these devices are interconnected by system bus 150 through connectors 111, 106, 107, 137 and 147. In addition, the system 10 provides a slot 116 for a memory cartridge 115. When inserted in the slot 116 the memory cartridge 115 is connected to the bus 165 via the connector 117. As shown in FIG. 1, a second slot 126 may be provided which, when filled with a memory cartridge is connected to the bus 165 via the connector 127.
The slot 126 may be used for memory in the form of additional ROS or RAM. Obviously, the number of slots can be increased beyond the two which are illustrated. The system bus 150 is coupled to cartridge bus 165 via isolation logic 160. The isolation logic 160 is available in typical commercially available devices and is described in the Intel iAPX 86, 88 User's Manual (August 1981) as including latch, buffer and transceivers. Isolation logic 160 is responsive to signals carried over address and/or control conductors of the system bus 150 to allow coupling of bus 150 to bus 165 only when address space connected to bus 165 is accessed. There may be further cartridge buses coupled to the system bus 150 via other isolation logic modules. The system 10 is subject to the prior art deficiencies in that when a memory cartridge such as ROS 115 is inserted/removed the act of insertion/removal produces noise on the bus 165 which can adversely affect the performance of any of the devices connected thereto. Specifically, since the isolation logic 160 may allow signals to pass from one bus to the other, there is no guarantee that noise on bus 165 will be isolated from system bus 150.
In one prior art system fixed ROS 105 provided essentially no operating functions except support for functions directed by a feature cartridge such as ROS 115. The typical ROS 115 maintained the CPU 100 executing in a tight loop of instructions from ROS 115. In such a system the insertion/removal of any other cartridge (such as in slot 126) was almost surely to generate erroneous execution since the logic 160 was almost continuously maintained in a condition to couple bus 150 to bus 165 (for instruction fetch). We have recognized that to the extent that the isolating logic 160 decouples the cartridge bus 165 from the system bus 150, then noise produced or: the cartridge bus 165 as a consequence of the insertion/removal of the memory cartridge will be unable to affect any of the other components, e.g. the RAM 110, the ROS 105, the CPU 100, the input device 130 or the output device 140. To eliminate the problem it was necessary, once the problem was recognized, to ensure that the operator's act of insertion/removal was, in time, mutually exclusive of the CPU accessing the cartridge bus 165.
As will be described in connection with FIG. 2 the software executed by the CPU 100 includes an idler function. The idler function is invoked by the system feature via a vector stored at a predetermined address in system RAM 110. The idler function, executing only within the system bus 150, retains control so long as an idler spin flag in the system RAM 110 is in a predetermined condition, for example zero. The invoker or system feature is responsible for maintaining the idler flag. As soon as the idler flag becomes non-zero (or more generally different than its rest or normal state) the idler function returns control to the invoker. The feature software, residing in an inserted memory cartridge, invokes the idler whenever it is waiting for work. When an external interrupt is fielded by the feature, indicating work is being requested, the feature interrupt handler alters the idler spin flag. After the interrupt is fully processed the idler function returns control to the feature to process the work request.
More particularly, FIG. 2 shows software which is used to implement the invention. The dashed line in FIG. 2 separates the main system software (residing in a component coupled to the main bus 150) from the cartridge software (which is associated with a memory cartridge). More particularly, as shown in FIG. 2 an idler function includes interrupt scan 20 and a decision point 30 in the form of a branch, one route being followed (back to the scan 20) in the event that the idler flag or idler bits are in a predetermined condition (zero). On the other hand, the other path (to the decision point 40, associated with the memory cartridge) is followed if the idler flag (idler bits) are not in their predetermined condition. FIG. 2 omits the typical power on and initialization functions which are conventional. Generally, these functions are executed with the system bus 150. The decision point 40 determines whether or not there is work to do, and itself branches to one of two paths. A first path is followed in the event there is work pending, and that path leads to the function 60 to execute or perform the work. After a particular work unit is performed, the decision point 40 is again entered. When the work has been completed, the other path from decision point 40 is followed to function 50. Function 50 clears the idler bits (alters the idler flag back to its predetermined condition). It should be apparent therefore that as long as the idler flag (idler bits equal zero) are in their predetermined condition, then there is no need to nor is there any reference to the memory cartridge. Under these conditions the isolating logic 160 is maintained in its decoupled condition and noise on the cartridge bus 165 will be unable to adversely affect any component coupled to the system bus 150. When the system interrupt handler 70 fields an interrupt requiring execution out of or reference to a memory cartridge, one step during the fielding of the interrupt is function 75 to alter the idler flag from its predetermined condition to another condition (such as to set an idler bit to one). On return from the interrupt to the idler, the decision point 30 will determine that the idler flag is no longer in its predetermined condition (the idler bits are no longer zero). This will invoke reference to the appropriate memory cartridge and generate an address within the cartridge bus address space so that the isolating logic 160 no longer decouples the cartridge bus 165 from the system bus 150. After completion of any work requiring reference to a memory cartridge, the function 50 is performed to alter the idler flag back to its predetermined condition. Of course, absence of references to cartridge bus address space renders isolation again effective.
The operating instructions accompanying the computer system advise the operator not to insert or remove a memory cartridge while the system is "busy". The term "busy" is defined, based on the particular characteristics of the system and the feature or features provided by the memory cartridge or cartridges. Thus when a cartridge is inserted or removed, the noise on the cartridge bus 165 created by altering the electrical connections will have no effect on any component coupled to the system bus 150.
As shown in FIG. 2, only when the idler bits are non-zero (occasioned by the need for reference to a memory cartridge) is there reference to the cartridge bus which inhibits the isolation between a system bus 150 and a cartridge bus 165. In one implementation of the invention, CPU 100 was an Intel 8088.
FIG. 2 specifically illustrates those functions related to the invention. There may be, in addition, other functions which CPU 100 executes wholly within the system bus 150 and thus do not require reference to cartridge bus 165. Typically, the invention will be implemented by providing ROS 105 (the on card ROS) with the idler function (20, 30). However, that is not essential. An alternate implementation is based on the recognition that instructions need not be executed out of ROS, but rather the initial program steps in the ROS call for loading the program into the RAM 110 and the majority of the code is executed from the RAM 110. In systems of the latter type, the software represented in FIG. 2 need not be contained in the ROS 105. Alternatively, this software can be contained in a ROS memory cartridge, along with other feature or features provided by the memory cartridge. Using the alternate implementation the ROS feature cartridge (such as 115) is initially referenced to load RAM 110 with the idle loop. Thereafter, the idle loop is executed from RAM 110 and no reference to cartridge bus 165 is necessary except for the feature code contained therein.
In accordance with this alternate implementation, the system should be powered up with a a ROS feature cartridge (including the software of FIG. 2) in order to obtain the full protection of the invention. If the alternate implementation is employed, the system is powered up in the absence of an ROS feature cartridge having the software of FIG. 2, and thereafter a memory cartridge is inserted, the idler loop (20-30) may be absent and thus the full protection provided by the invention may not be present.
Assuming that the system is powered up with an ROS feature cartridge inserted, then when the RAM 110 is loaded with the program (from the ROS 105) it is also loaded with at least the idle loop software of FIG. 2 (from the ROS feature cartridge 115). Thereafter, the alternate implementation operates in exactly the same fashion as if the software of FIG. 2 had been included in the ROS 105.
Those skilled in the art will recognize that many changes can be made within the scope of the invention, which is to be interpreted in accordance with the following claims.
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|U.S. Classification||714/30, 714/E11.018|
|International Classification||G06F11/00, G06F12/16, G06F13/40, G06F1/18|
|Cooperative Classification||G06F13/4081, G06F11/00, G06F1/183|
|European Classification||G06F11/00F, G06F13/40E2H, G06F1/18S|
|Jul 25, 1985||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, ARMON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:DHOPESHWARKAR, DHIRENDRA;HIGHTOWER, SCOTT A.;MATHIS, MAC A.;AND OTHERS;REEL/FRAME:004435/0901;SIGNING DATES FROM 19850719 TO 19850722
|Jan 7, 1992||CC||Certificate of correction|
|Jan 10, 1994||FPAY||Fee payment|
Year of fee payment: 4
|Apr 7, 1998||REMI||Maintenance fee reminder mailed|
|Sep 13, 1998||LAPS||Lapse for failure to pay maintenance fees|
|Nov 24, 1998||FP||Expired due to failure to pay maintenance fee|
Effective date: 19980911