JEDEC Solid State Technology Association today announced the publication of JESD209-4 Low Power Double Data Rate 4 (LPDDR4) aimed at boosting memory speed and efficiency for mobile computing devices. Members of Joint Electron Device Engineering Council (JEDEC), a standards organization made up of industry volunteers, redesigned the architecture to operate at twice that of LPDDR3.
Going from a one-channel die with 16 bits per channel to a two-channel die with 16 bits per channel, for a total of 32 bits, LPDDR4 launches at I/O data rate of 3200 MT/s and will eventually operate at 4266 MT/s, twice that of LPDDR3, according to a press release. (LPDDR3 operates at 2133 MT/s.)
The power savings occurs because the two channels reduce the distance data signals travel from the memory array to the I/O bond pads, which means less power is needed to transmit data.
"LPDDR4 represents a dramatic performance increase," said Mian Quddus, chairman, JEDEC Board of Directors in the press release. "It is intended to meet the power, bandwidth, packaging, cost and compatibility requirements of the world's most advanced mobile systems."
Key specifications include:
- Two-channel architecture
- Internal Vref supplies for CA and DQ
- Data Bus Inversion (DBI-DC)
- ODT for CA and DQ
- I/O throughput: 3200 MT/s, rising to 4266 MT/s
- Signaling voltage: 367mV or 440mV
- Operating voltage: 1.1V
- Pre-fetch size: 32B per channel
- Topology: Point to point, PoP, MCP
- Max I/O capacitance: 1.3pF
- Write leveling
- 6-pin SDR CA bus CA training (12 pins per two channels)
- As with previous low-power DRAM generations, LPDDR4 does not require a delay-locked loop (DLL) or phase-locked loop (PLL)