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On primitive fault identification and test generation
The finite propagation delays of gates and leads in a circuit limit the speed at which it can operate. The fault-free temporal behavior of a circuit is guaranteed if no delay fault is present. We use the path delay fault model to model the timing failures that can occur in a circuit.^ This dissertation proposes a method for identification and test generation of primitive path delay faults (the only faults that have to be tested to guarantee timing correctness at the operating speed) in a combinational circuit. We introduce the concept of sensitizing cubes which helps in identifying paths that are sensitizable only together and aids in the identification of primitive faults. We check the effectiveness of the algorithm by obtaining experimental results on the ISCAS'89 and MCNC'91 benchmark circuits.^ The space in which a sequential circuit operates, called normal operation, is determined by the states that are reachable from a known initial state. Thus, the timing behavior of a sequential circuit is determined by the reachable states. We extend the primitive fault identification method for identifying the primitive faults in a sequential circuit, taking into account the set of reachable states during normal operation. Since the tests that can be applied in a sequential circuit are determined by the reachable states, not all primitive faults may have tests that guarantee their detection, even though there exist combinational tests that detect such faults. We propose a synthesis method for sequential circuits, that results in a test for a every primitive fault. We address the initialization problem in the presence of untestable path delay faults and propose a synthesis method to prevent it. ^
Engineering, Electronics and Electrical
Ramesh Chandra Tekumalla,
"On primitive fault identification and test generation"
(January 1, 1998).
Doctoral Dissertations Available from Proquest.