|Publication number||US7447105 B2|
|Application number||US 11/586,665|
|Publication date||Nov 4, 2008|
|Filing date||Oct 26, 2006|
|Priority date||Oct 26, 2006|
|Also published as||US20080101148|
|Publication number||11586665, 586665, US 7447105 B2, US 7447105B2, US-B2-7447105, US7447105 B2, US7447105B2|
|Original Assignee||Winbond Electronics Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Referenced by (6), Classifications (5), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The invention relates to a memory row decoder and more particularly to a memory row decoder with reduced gate induced drain leakage (GIDL) current.
2. Description of the Related Art
Gate induced drain leakage (GIDL), with regards to off-state current, constitutes a serious constraint in scaled down CMOS device. GIDL is induced by strong electric field between the gate and drain, and increases exponentially due to reduced gate oxide thickness. Since increased integration of semiconductor devices requires thinner gate oxide layer between a substrate and gate, GIDL is an issue when MOS transistors are scaled towards the deep sub-micrometer regime.
The circuit of
As shown, when the memory row decoder 200 is in an unselected mode, the source-to-gate voltage of the enhancement PMOS transistor mep1 is (VNN-VPP). In memory design, the level of VNN is chosen relatively negative to the bulk voltage of other transistors outside the memory for the purpose of minimizing the off-state sub-threshold current of the transistors in the memory. However, this makes (VNN-VPP) more negative and results in increased off-state sub-threshold current due to GIDL effect and accordingly more power consumption.
It is thus important to provide a memory row decoder with reduced GIDL current to reduce power consumption.
The invention discloses a memory row decoder with reduced GIDL current when operating in an unselected mode, with reduced power consumption.
The invention provides a memory row decoder comprising a first depletion NMOS transistor having a first source/drain, a second source/drain coupled to a first partially decoded signal, and a gate coupled to a second partially decoded signal, a first enhancement PMOS transistor having a first source/drain, a second source/drain coupled to the second partially decoded signal, and a gate coupled to the first source/drain of the first depletion NMOS transistor, a first enhancement NMOS transistor having a first source/drain coupled to the first source/drain of the first enhancement PMOS transistor, a second source/drain coupled to a first reference potential, and a gate coupled to the first partially decoded signal, and a second enhancement NMOS transistor having a first source/drain coupled to the first source/drain of the first PMOS transistor, a second source/drain coupled to the first reference potential, and a gate coupled to a reset signal. The first source/drain of the first enhancement PMOS transistor acts as an output terminal of the memory row decoder to be coupled to a word line of a memory.
Since the gate voltage of the first enhancement PMOS transistor is reduced when the memory row decoder is in an unselected mode to deactivate the word line, the GIDL current in the first enhancement PMOS is reduced, and accordingly the memory row decoder consumes less power and provides enhanced power efficiency.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The transient current flows until voltage VPG at the gate 38 of the enhancement PMOS transistor mep1 is charged to (VNN-Vtnd) so as to turn off the depletion NMOS transistor mdn1, wherein Vtnd denotes threshold voltage of the depletion transistor NMOS transistor mdn1. The enhancement PMOS transistor mep1 stays turned off and its source-to-gate voltage is stabilized at [VNN−(VNN−Vtnd)]=Vtnd.
Next, in a period Ps, the first partially decoded signal bMWL is turned to low (at level VNN), the signal WLDV is a turned to high (at level VPP), and WLRST is turned to low (at level VNN). The low bMWL and WLRST turn off the NMOS transistors men1 and men2. Further, since bMWL is low and WLDV is high, the depletion NMOS transistor mdn1 is turned on, pulling the voltage VPG at the signal terminal 38 down to VNN, turning on the enhancement PMOS transistor mep1. Resultingly, the voltage VWL at the output terminal 33 is pulled up to VPP.
Since a high potential VPP is applied to the word line WL, activation thereof and enabling the memory cell transistors with gates coupled to the word line WL, the memory row decoder 300 is deemed to operate at a “selected” mode.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5365479 *||Mar 3, 1994||Nov 15, 1994||National Semiconductor Corp.||Row decoder and driver with switched-bias bulk regions|
|US5563842 *||Jan 10, 1995||Oct 8, 1996||Nexcom Technology, Inc.||Row decoder for a memory having settable threshold memory cells|
|US5636175 *||Jan 18, 1995||Jun 3, 1997||Micron Semiconductor, Inc.||Row decoder/driver circuit for determining non selected wordlines and for driving non-selected wordlines to a potential less than the lowest potential of the digit lines|
|US7277315 *||Dec 14, 2005||Oct 2, 2007||Etron Technology, Inc.||Multiple power supplies for the driving circuit of local word line driver of DRAM|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7697367 *||Jun 26, 2008||Apr 13, 2010||Fujitsu Microelectronics Limited||Semiconductor memory device with reduced current consumption|
|US8120968||Feb 12, 2010||Feb 21, 2012||International Business Machines Corporation||High voltage word line driver|
|US8503136||Oct 24, 2011||Aug 6, 2013||Winbond Electronics Corp.||Protecting circuit and control circuit for reducing leakage current|
|US9117547||May 6, 2013||Aug 25, 2015||International Business Machines Corporation||Reduced stress high voltage word line driver|
|US20090092000 *||Jun 26, 2008||Apr 9, 2009||Fujitsu Limited||Semiconductor memory device with reduced current consumption|
|US20110199837 *||Feb 12, 2010||Aug 18, 2011||International Business Machines Corporation||High Voltage Word Line Driver|
|U.S. Classification||365/230.06, 365/189.09|
|Oct 26, 2006||AS||Assignment|
Owner name: WINBOND ELECTRONICS CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, CHENG-SHENG;REEL/FRAME:018466/0892
Effective date: 20060921
|Apr 12, 2012||FPAY||Fee payment|
Year of fee payment: 4
|Apr 28, 2016||FPAY||Fee payment|
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