Cadenas, Oswaldo and Megson, Graham M. (2002) Improving mW/MHz ratio in FPGAs pipelined designs. In: Euromicro symposium on digital system design: architectures, methods and tools: proccedings. IEEE, pp. 276-282. ISBN 0769517900Full text not available from this repository.
This paper presents a simple clocking technique to migrate classical synchronous pipelined designs to a synchronous functional-equivalent alternative system in the context of FPGAs. When the new pipelined design runs at the same throughput of the original design, around 30% better mW/MHz ratio was observed in Virtex-based FPGA circuits. The evaluation is done using a simple but representative and practical systolic design as an example. The technique in essence is a simple replacement of the clocking mechanism for the pipe-storage elements; however no extra design effort is needed. The results show that the proposed technique allows immediate power and area-time savings of existing designs rather than exploring potential benefits by a new logic design to the problem using the classic pipeline clocking mechanism.
|Item Type:||Book Section|
|Uncontrolled Keywords:||field programmable gate arrays, logic design, systolic arrays, FPGAs pipelined designs, Virtex-based FPGA circuits, clocking technique, logic design, mW/MHz ratio, synchronous functional-equivalent alternative system, systolic design|
|Subjects:||University of Westminster > Science and Technology > Electronics and Computer Science, School of (No longer in use)|
|Depositing User:||Miss Nina Watts|
|Date Deposited:||27 Jan 2009 12:15|
|Last Modified:||19 Oct 2009 13:11|
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