Endura® Volta™ CVD Cobalt
The Applied Endura® Volta™ CVD Cobalt system sustains Applied’s technical leadership in CVD, introducing the first material change in more than 15 years of copper barrier/seed (CuBS) development to enable continued high-performance interconnect scaling. The first-of-its-kind technology makes possible deposition of seed-enhancing liner and selective cap layers less than 20Å thick that improve interconnect yield and reliability at the 2Xnm node and beyond. It is the industry’s only vacuum-based electro-migration (EM) mitigation solution and the only CVD cobalt liner product integrated on the same platform with pre-clean, barrier, and copper seed processes.
Driven by the demand for complex mobile technologies, multi-component system-on-chip (SoC) designs are proliferating to deliver desired functionality and compact form factor. Aggressive pitch scaling for these modern processors in turn is driving greater circuit density and necessity for high performance from interconnects that run for literally miles through these multi-level devices. These trends make it more challenging to achieve the coverage, adhesion, and fill that produces the void-free copper interconnects essential for device operation. Even a single void can render portions of the chip useless.
The Volta CVD Cobalt system introduces a new materials era for extending copper interconnect technology. It promotes copper seed layer coverage by improving copper wetting, resulting in a thin, continuous, conformal layer that facilitates repair of discontinuities and formation of a robust seed layer. This high-quality layer in turn promotes void-free copper gap fill at the most advanced nodes.
Shrinking geometries also result in higher resistance as well as greater susceptibility to EM failures in the copper lines. A high-quality bond at the interface between the copper and dielectric barrier layer is vital for avoiding EM failures. The Volta system’s best-in-class (>100:1) selective metal capping process strengthens adhesion at the copper-dielectric interface to improve EM performance by an order of magnitude without increasing line resistance or degrading time-dependent dielectric breakdown.
The combined use of Volta CVD Cobalt as both liner and selective metal cap enables complete encapsulation of copper lines and ensures the most robust interconnect reliability for the 2Xnm node and beyond.