|Publication number||US5274713 A|
|Application number||US 07/764,221|
|Publication date||28 Dec 1993|
|Filing date||23 Sep 1991|
|Priority date||23 Sep 1991|
|Publication number||07764221, 764221, US 5274713 A, US 5274713A, US-A-5274713, US5274713 A, US5274713A|
|Inventors||Han-Chieh Chang, Ting-Yao Chen, Hsien-Yei Chen|
|Original Assignee||Industrial Technology Research Institute|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Referenced by (20), Classifications (13), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a real-time apparatus for detecting surface defects on objects.
The most traditional way for detecting surface defects of objects is by human visual inspection, which has the following drawbacks:
(1) the human eye is limited to detecting stationary objects, not quickly moving objects; and
(2) the human eye easily tires, lowering the efficiency thereof.
Another conventional way of detecting surface defects is to utilize arrays of photosensors to test an object and to detect the surface defects thereof. The drawback of photosensors arises from the large amounts of photosensors which causes difficulty in implementation and which generates a faulty result if anyone of the photosensors malfunctions.
Another technique to accomplish surface-defect detection may utilize a laser detecting device. However, the speed of an object under test is limited under 1.2 m/s, if it is tested with a conventional laser detecting device. A drawback for a real-time detecting laser device is that it costs too much to be readily affordable in this field.
The invention refers to a real-time apparatus for detecting surface defects on objects comprising a high-frequency linear light source for generating linear light which is focused on a line position of the tested object, a linear CCD (charge coupled device) camera for scanning the line position and generating an analog image signal, an image-signal processing device for converting the analog image signal to digital image signal which is a 256-level gray signal, and further converting the digital signal to a HIGH or a LOW signal depending on a predetermined threshold of the gray scale of the digital image signal, a combination of the HIGH and LOW signals constituting binary image data in the form of binary pulses, an image-storing circuit connected to the image-signal processing circuit for storing the binary image data, a defect-detecting unit for detecting if an area unit has a valid defect which meets one of a set of predetermined defect patterns or detecting statistical defects which are not valid defects but a plurality of small defects combined together still counted as defects, and a defect detecting statistic unit connected to the image-storing circuit for calculating a total amount of defect, and the area and location of each defect by a well-known connectivity analyzation process.
The primary object of the present invention is to provide a real-time apparatus for detecting surface defects on objects to replace a traditional human-eyed detecting, photosensor detecting, or laser detecting.
Another object of the present invention is to provide a real-time apparatus for detecting a surface "valid defect" which has an area unit meeting with one of a set of predetermined patterns.
Another object of the present invention is to provide a real-time apparatus for detecting surface defects which pas in the previous detecting stage in an area unit but together are still counted as defects if the amount of the small defects in a predetermined area, such as an area equals to 30 scanning lines, exceeds a predetermined value.
Another object of the present invention is to provide a real-time apparatus which automatically detects the surface defects on a tested object with high speed and has statistic analyzation.
Another object or the present invention is to provide a real-time apparatus having a linear detecting mode for checking a moving object.
Another object of the present invention is to provide a real-time apparatus having a high-frequency linear light source (at least 25 KHz) to generate linear light for operating in a linear detecting mode.
Another object of the present invention is to provide a real-time apparatus having an illumination compensation table to equalize linear light.
Another object of the present invention is to provide a real-time apparatus having connectivity analyzation ability to calculate the amount of defects, the area of each defect spot, and the location of each defect spot.
Further objects and advantages of the present invention will become apparent from a careful reading of the detailed description provided hereinbelow, with appropriate reference to the accompanying drawings.
FIG. 1 is an perspective view of a preferred embodiment according to the present invention;
FIG. 2 is a block diagram of the present invention.
FIG. 3 is a block diagram of an image signal processing unit of the present invention;
FIG. 3A is a schematic view showing a distortion effect at two sides of a scanning line;
FIG. 3B is a schematic view showing a-compensation effect on the scanning line of FIG. 3A.
FIG. 4A is a top view of a high-frequency linear light source of the present invention;
FIG. 4B is a front view of a high-frequency linear light source of the present invention;
FIG. 4C is a sectional view cut from FIG. 4A;
FIG. 4D is a side view of a high-frequency linear light source of the present invention;
FIG. 4E is a schematic view showing the high-frequency linear light source incorporating with a linear CCD camera.
FIG. 5 is a schematic representation of scanning process of a linear CCD camera to different defect patterns;
FIG. 6 is a Boolean expression for determining whether an area unit has a valid defect;
FIG. 6A is a schematic view of four FIFOs connected through a multiplexer to a defect-detecting circuit of the present invention;
FIG. 6B is a schematic view of the defect-detecting circuit connected to two peripheral devices; and
FIG. 7 is a block diagram of a defect-detecting statistic unit in the invention.
Referring to FIG. 1, a real-time detecting apparatus in the present invention comprises a linear CCD (charge coupled device) camera 1, a lens 2, a high-frequency linear light source (at least 25 KHz) 3, a driving circuit 4 for the linear CCD camera, an image-signal processing circuit 5, an image-storing circuit 6, a defect-detecting circuit 7, a statistical-defect detecting circuit 8, a signal bus main board 9, and a defect-detecting statistic unit 13. An object under test 11 (hereinafter shortened as OUT) is located on a simplified conveying device 10 and is moved continuously thereby. The conveying device 10 is not in the scope of the present invention and needs not be described in detail.
FIGS. 4A, 4B, 4C, and 4D shows the high-frequency linear light source 3 used in the present invention. The high-frequency linear light source 3 comprises two fluorescent lighting tubes 31 each with a semicircular light shield 32 supported by a pair of supporting means 36 on longitudinal sides thereof. Two hinges 33 are connected between the two light shields 32. A gap 34 is formed between the two light shields 32 which is used as a channel for the light reflected from the surface of OUT 11 to the linear CCD camera 1. The width of the gap 34 remains constant because of the geometry of the light shields 32 (semicircular) and the engagement of the hinges 33 therewith. One light shield 32 is engaged to the pair of supporting means 36 with a pair of secured points 38 thereon. Two knobs 35 are fixed to two longitudinal ends of the other light shield 32, with two guiding grooves 37 formed on each supporting means 36, respectively, such that a user can adjust a focusing angle of the light source 3 by lifting up or pulling down the knobs 35 along the guiding grooves 37, and "lock" the knobs 35 when the focusing angle has been adjusted. It should be noted that the two guiding grooves 37 are formed such that when the knobs 35 are lifted up or pulled down along the guiding grooves 37, the focusing angle between the light shields 32 are changed respondingly. Therefore, the light source 3 is employable in different distances of OUT. FIG. 4E shows the sectional view of the high-frequency linear light source 3 incorporated with the linear CCD camera 1.
Referring to FIGS. 2 and 5, the high-frequency linear light source 3 generates a linear light which is focused on the surface of the OUT 11. The linear CCD camera 1 picks up the reflected light from the OUT 11 through the lens 2 disposed thereon, and generates image signals which represent a scanning line. As the OUT 11 moves, the linear CCD camera 1 scans the OUT 11 line-by-line. The technical details for processing the reflection light to image signal is a known skill not included in the scope of the present invention.
The driving circuit 4 for the linear CCD camera 1 controls the image signal to couple with the image-signal processing circuit 5.
Referring to FIG. 3, the image signal from the linear CCD camera 1 is coupled with an illumination compensation circuit 51 which acquires a plurality of compensation factors from a compensation table 52, thereby compensating for the light deviation problem in linear light. It is known that the signal level on the two sides of a scanning line is distorted (see FIG. 3A) and should be compensated as an original scanning line (see FIG. 3B). The compensation table 52 is implemented as a hardware construction and is installed in the driving circuit 4.
After the compensation from the illumination compensation circuit 51, a compensated image signal thereof is coupled through a clamp circuit 53 and an amplifier circuit 54 to an A/D (analog to digital) converter 55. The A/D converter 55 digitalizes the compensated and amplified image signal to a 256-level digitalized image signal which is represented by an 8-bit digital signal. The digital image signal is leveled from degree 0 to degree 255, according to its gray scale level. The digital image signal is coupled through a latch circuit 56 to a binary circuit 57. The binary circuit determines a digital image signal to be either a HIGH (i.e. "1" in Boolean algebra) signal or a LOW (i.e. "0" in Boolean algebra) signal as in binary digital signal. For example, if the gray scale level of the digital image signal is less than or equal to a predetermined value, such as 100, then it is converted to a HIGH signal; otherwise, it is a LOW signal. The predetermined value is set according to requirements of different OUTs 11. A combination of HIGH and LOW signals constitute a binary image in the form of binary pulses.
The train of binary pulses is stored in the image-storing circuit 6 which comprises four first-in-first-out (FIFO) high-speed memories for storing the binary image. In practice, one of the four FIFOs receives the binary image corresponding to a scanning line, while the other three FIFOs pass a binary image corresponding to three scanning lines already stored therein to the defect detecting unit 70 and to the defect detecting statistical unit 13. Each time this occurs, one of the four FIFOs is used to receive a line of scanning image alternately. The schematic view of the FIFOs incorporated with the defect detecting unit 70 is shown in FIG. 6A.
The defect detecting unit 70 comprises the defect determining circuit 7 and the statistic defect-detecting circuit 8. The defect-detecting circuit 7 processes binary data by checking a plurality of data units continuously. Each data unit corresponds to an area unit 90 which is composed of 3×3 matrix pixels as shown in FIG. 6. In this area unit 90, if the Boolean expression equals "1" (i.e., HIGH), the area is deemed as a "valid defect"; if some of the pixels are in a HIGH status but the Boolean expression equals "0" (i.e., LOW), the area is deemed as a "small defect"; if none of the pixels is in a HIGH status, the area unit is deemed "defectless." The Boolean expression may be changed according to different requirements of defect detecting. For example, one available Boolean expression for a valid defect is described as follows: ##EQU1##
Q1 to Q9 represents one bit of binary digital data, respectively, each of which corresponds to a pixel in the original scanning line. Moreover, "Q1, Q4, Q7 " represents three bits of binary digital data corresponding to three adjacent pixels in a first scanning line and is stored in a first FIFO; "Q2, Q5, Q8," a second scanning line and a second FIFO; "Q3, Q6, Q9," a third scanning line and a third FIFO. While the first, second, and third FIFOs are passing binary data to the defect-detecting circuit 7, a fourth FIFO is used for receiving a binary image corresponding a scanning line from the image-signal processing circuit 5. The first, second, third, and fourth FIFOs are not definitely numbered but changed alternately as described above.
The Boolean expression is realized by the defect-detecting circuit 7 which comprises a plurality of AND gates and OR gates. The technique for realizing the Boolean expression as described above to a real circuit (i.e., the defects detecting circuit 7) simply utilizes a combination of AND gates and OR gates, which is well known and not limited to a specific structure.
Referring to FIG. 6B, if a valid defect is detected, the defect-detecting circuit 7 will either actuate a label device to label the position of the valid defect or actuate a location identification device to store the defect location. The label device and the location identification device are peripheral devices which may be used to incorporate with the real-time apparatus of the present invention and are not included in the scope thereof.
Referring to FIG. 2 again, the statistical defect-detecting circuit 8 detects small defects which pass undetectedly in defect-detecting circuit 7 in an area unit 90 (see FIG. 6) but together are still counted as defects if the amount of the small defects in a predetermined area, such as an area equals to 30 scanning lines, exceeds a predetermined value (for example, 10 small defects).
The defect detecting statistic unit 13, as shown in FIG. 2, is connected to the image-storing circuit 6 for calculating the amount of defects and the area and location of each defect by a well-known connectivity analyzation process. Referring to FIG. 7, is a block diagram of the defect detecting satatistic unit 13 is shown. The first block 6 represents obtaining data from the image data storing circuit 6. The procedure goes to block 7A. In block 7A a plurality of hardware counters calculates the starting address and ending address of each area unit 90 (see FIG. 6), and the procedure goes to block 7B. Blocks 7B to 7E are all software blocks. In block 7B, the run-length for the moving OUT 11 is calculated and encoded to a plurality of analyzed data which are sent to block 7C. The analyzed data are processed through a set of connectivity algorithm 7C and obtains the amount of defects, each area and location of corresponding defect, in block 7D. The procedure goes to block 7E, and has a statistical data report thereof.
The driving circuit 4 of the linear CCD camera 1 comprises a system-clock selecting circuit 40 and an exposure-time control circuit 41. The system-clock selecting circuit 40 is used to select a clock pulse of up to 20 MHz. The frequency of the clock pulse is selected according to the moving speed of the OUT 11. If the system clock has a high frequency (above 5 MHz), a sensor (not shown) in the CCD camera 1 is ON all the time since the defect detecting is proceeding, while a low frequency (less than 5 MHz) renders the CCD camera 1 ON for a first time-period and OFF for a second time-period alternately. The lengths of the first time-period and the second time-period are determined by the frequency of the clock pulse, which is not in the scope of the present invention. The exposure-time control circuit 41 is used for selecting a complete exposure mode or a half exposure mode. In the complete exposure mode the linear CCD camera 1 works with high frequency (such as 6 MHz) and the sensor of the CCD camera 1 is ON during the entire defect detecting operation. In the half exposure mode, the linear CCD camera 1 works with low frequency (such as 2 MHz) and the sensor is ON for a first time-period and OFF for a second time-period alternately.
Although this invention has been described with a certain degree of particularity, it is to be understood that the present disclosure has been made by way of example only and that numerous changes in the detailed construction and the combination and arrangement of parts may be resorted to without departing from the spirit and scope of the invention as hereinafter claimed.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4758782 *||10 Sep 1986||19 Jul 1988||Kowa Company Ltd.||Method and apparatus for inspecting printed circuit board|
|US4811410 *||23 Oct 1987||7 Mar 1989||American Telephone And Telegraph Company||Linescan inspection system for circuit boards|
|US4975972 *||18 Oct 1988||4 Dec 1990||At&T Bell Laboratories||Method and apparatus for surface inspection|
|US5137362 *||26 Mar 1990||11 Aug 1992||Motorola, Inc.||Automatic package inspection method|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5657394 *||4 Jun 1993||12 Aug 1997||Integrated Technology Corporation||Integrated circuit probe card inspection system|
|US5878153 *||9 Sep 1996||2 Mar 1999||Ford Global Technologies, Inc.||Method for monitoring coating adhesion propensity based on surface morphology|
|US5978499 *||5 Jun 1996||2 Nov 1999||International Paper Box Machine Company, Inc.||Apparatus and method for inspecting box blanks|
|US6115490 *||22 Apr 1996||5 Sep 2000||Platsch; Hans||Apparatus for determining the powder density on a dusty printed article|
|US6118894 *||21 Jan 1997||12 Sep 2000||Schwartz; Rodney E.||Integrated circuit probe card inspection system|
|US6354724||25 Feb 2000||12 Mar 2002||Kokusai Gijutsu Kaihatsu Co., Ltd.||Line illuminating apparatus|
|US6434264 *||11 Dec 1998||13 Aug 2002||Lucent Technologies Inc.||Vision comparison inspection system|
|US6493597 *||30 Jan 1998||10 Dec 2002||Inspectron||Print monitoring system and method using slave signal processor/master processor arrangement|
|US7443498 *||27 May 2005||28 Oct 2008||Hoya Corporation||Method and apparatus for inspecting a mura defect, and method of manufacturing a photomask|
|US7783103 *||26 Sep 2006||24 Aug 2010||Sharp Kabushiki Kaisha||Defect detecting device, image sensor device, image sensor module, image processing device, digital image quality tester, and defect detecting method|
|US20040120602 *||8 Dec 2003||24 Jun 2004||Konica Minolta Holdings, Inc.||Method and apparatus for processing image data|
|US20050271262 *||27 May 2005||8 Dec 2005||Hoya Corporation||Method and apparatus for inspecting a mura defect, and method of manufacturing a photomask|
|US20070071304 *||26 Sep 2006||29 Mar 2007||Sharp Kabushiki Kaisha||Defect detecting device, image sensor device, image sensor module, image processing device, digital image quality tester, and defect detecting method|
|DE19516274C1 *||8 May 1995||14 Nov 1996||Jenoptik Technologie Gmbh||Optical sensing of objects for control on moving conveyor|
|EP1043580A2 *||15 Mar 2000||11 Oct 2000||Kokusai Gijutsu Kaihatsu Co., Ltd.||Illuminating apparatus with linear spot of light|
|EP1429541A2 *||4 Dec 2003||16 Jun 2004||Konica Minolta Holdings, Inc.||Method and apparatus for processing image data|
|WO1994029816A1 *||3 Jun 1994||22 Dec 1994||Integrated Technology Corporation||Integrated circuit probe card inspection system|
|WO1996007158A2 *||1 Sep 1995||7 Mar 1996||Rautaruukki Oy||Method for detecting imperfections on a surface inspected|
|WO1996007158A3 *||1 Sep 1995||28 Mar 1996||Pertti Kontio||Method for detecting imperfections on a surface inspected|
|WO2007062563A1 *||14 Sep 2006||7 Jun 2007||Bohai Shipbuilding Industry Co., Ltd.||On-line automatic inspection method for detecting surface flaws of steel during the pretreatment of the ship steel|
|U.S. Classification||382/141, 356/237.2, 348/128, 250/559.46, 348/E07.085|
|International Classification||G06T7/00, H04N7/18|
|Cooperative Classification||G06T2207/30164, G06T7/0004, H04N7/18, G06T2207/20076|
|European Classification||G06T7/00B1, H04N7/18|
|23 Sep 1991||AS||Assignment|
Owner name: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:CHANG, HAN-CHIEH;CHEN, TING-YAO;CHEN, HSIEN-YEI;REEL/FRAME:005851/0282
Effective date: 19910910
|18 Jun 1997||FPAY||Fee payment|
Year of fee payment: 4
|14 Jun 2001||FPAY||Fee payment|
Year of fee payment: 8
|28 Jun 2005||FPAY||Fee payment|
Year of fee payment: 12