|Publication number||US5991305 A|
|Application number||US 08/992,922|
|Publication date||Nov 23, 1999|
|Filing date||Dec 18, 1997|
|Priority date||Feb 14, 1997|
|Also published as||US5983308, US5999441, US6011799, US6029197, US6052751, US6058112, US6058427, US6108342, US6111874, US6111875, US6122669, US6128310, US6151322, US6157623, US6167054, US6169742, US6178483, US6181702, US6185630, US6192028, US6223305, US6236643, US6236654, US6243020, US6249521, US6269098, US6292483, US6310876, US6356551, US6393021, US6393548|
|Publication number||08992922, 992922, US 5991305 A, US 5991305A, US-A-5991305, US5991305 A, US5991305A|
|Inventors||Philip Simmons, Bahadir Erimli|
|Original Assignee||Advanced Micro Devices, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Non-Patent Citations (6), Referenced by (22), Classifications (98), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority from provisional patent application Ser. No. 60/038,025, filed Feb. 14, 1997, the entire disclosure of which is hereby incorporated by reference herein.
Some of the subject matter disclosed in this application is similar to subject matter disclosed in copending application Ser. No. 08/992,919, entitled MANAGEMENT INFORMATION BASE (MIB) ACCUMULATION PROCESSOR, filed Dec. 18, 1997 and copending application Ser. No. 08/992,920, entitled MANAGEMENT INFORMATION BASE (MIB) REPORT INTERFACE FOR ABBREVIATED MIB DATA, filed Dec. 18, 1997.
The present invention relates to network switching and, more particularly, to the accumulation of Management Information Base objects (MIBs) on a data network switch logic chip.
A data network switch permits data communication among a plurality of media stations in a local area network. Data frames, or packets, are transferred between stations by means of data network switch media access control (MAC) enabling network interface cards. The network switch passes data frames received from a transmitting station to a destination station based on the header information in the received data frame.
Packet transmission events typically are tracked to provide a basis for statistical analysis of network operation with respect to each data network switch port.
For example, the number of transmitted packets, received packets, transmission collisions and the like can be counted and polled periodically. These significant parameters, termed objects, may be collected for purposes of statistical analysis. Through the use of statistical counters, determination can be made of improper device operation such as, for example, loss of packets.
Typically, each MAC unit may include a receive state machine and a transmit state machine having internal counters of limited capacity for counting a small number of transmission event parameters for each frame that traverses the respective switch port. Flip-flops, dedicated to the particular parameter objects, are respectively incremented each time an item in that frame is identified. For each incoming frame, which may be temporarily stored in a receive FIFO buffer, the respective flip-flops in the receive state machine are read and the resulting data are appended to the frame. For outgoing frames, similar processing takes place. Thus, the outgoing frame, transitionally stored in a transmit FIFO buffer, contains appended data relating to the receipt operation and transmit operation. The transmit operation data is added when the frame is transmitted out from the transmit FIFO buffer.
As data networks become more robust and data traffic increases, additional operational parameters become significant. The need to track all significant parameters imposes difficulties relating to increased MAC complexity. Such complexity involves the provision of more registers and supporting logic elements, as well as a requirement for larger buffer capacities. Integration of these additional elements for each MAC on the switch logic chip places a burden on chip architecture. These projected difficulties, and the relatively limited reporting functionality for the prior art arrangement, are significant disadvantages. These disadvantages are magnified if the data representing the operational parameters are retained in uncompressed format.
More recent network switch versions provide a RAM based memory on the switch logic chip as a full counter for data received from all of the MACs on the chip. Incorporation of a large capacity RAM in the chip to accommodate operational parameter data from all ports incurs undesirable expense. As the number of parameters increases to keep up with expanding statistical requirements, available RAM capacity must meet these needs. Polling of the RAM for external statistical diagnostic functions would require transfer of significantly increased quantities of data. Space constraints inherent in the integration of the various elements on a single logic chip are significant concerns.
The accumulation of this increased operational parameter data and the frequent access thereof for statistical processing imposes additional operational considerations. Traffic events and parameters of interest are monitored as they occur and contemporaneously added during the course of operation. The data will be retrieved frequently to perform appropriate statistical processing to analyze normal operation or for diagnostic purposes during a testing period. Whether the data to be retrieved is to be stored in registers or memory, on or off chip, the system should be able to reset such devices without clearing other registers on the logic chip so that switch operation can continue unfettered in the expected manner. The application to the chip of a global reset for the purpose of retrieval of statistical data would not permit this objective.
In view of the limitations described above, the need exists for effectively satisfying the expanding requirements for provision of switch performance data by a network switch. Such requirements stem not only from the large number of ports and usage that can be expected from future implementations, but from the greater number of network operational parameters that will be monitored.
An arrangement is needed that can supply this required data while performing in an efficient manner from the standpoint of accuracy, speed and expense. Such an arrangement should be able to perform real time functions on the data network switch chip without occupying an inordinate amount of chip architecture. Accessing and processing performance data must be achieved without interfering with normal switch traffic operations.
The present invention addresses the above noted needs by defining significant event parameters as objects of a Management Information Base (MIB). An improved data network switch architecture includes an on-chip "MIB engine" having a MIB report processor that enables monitoring of a large number of MIB objects by each on-chip MAC, ultimately to be stored in external memory, while minimizing MAC complexity.
In accordance with the invention, an Integrated Multiport Switch (IMS) includes all logic components on a single chip. A MAC for each port in the switch outputs a MIB report for each transmission or reception of data according to a specific compressed format to a MIB engine that can be centrally located on the chip. The compression of the data that represents the monitored events enables conservation of the capacity of MAC buffer elements. As the MIB report is immediately dispatched to the MIB engine upon receipt of a data frame, the report data is not appended to the received frame, thereby enabling efficient use of the receive FIFO buffer.
The MIB engine of the present invention includes a MIB report processor that decodes the MIB report into a plurality of associated MIB objects, which are temporarily accumulated at storage in the MIB engine until the external memory is updated. MIB report data received from the MAC for each port is allocated to a respective portion of the accumulation storage. Each such portion is sectioned into variable length segments, which correspond to predefined MIB objects.
The MIB engine initiates an external memory MIB value updating process by retrieving the values from the external memory and adding the accumulated MIB objects to the retrieved values. The updated MIB objects are then transmitted back to the external memory for storage therein and the MIB engine object values are reset.
The switch management entity, or host, which is external to the logic chip, can access the full MIB counters in the external memory through a PCI interface and bus on the chip to which both the host and external memory are coupled. The host can process this information, then issue data signals to clear some or all of the external memory and reset the MIB engine. This reset data signal will not cause a global reset of other registers in the chip. Resetting preferably will "zero out" MIB logic registers. The resetting function can also be initiated while the chip is accumulating data during a testing period for diagnostic and debugging purposes. The host can accumulate local data accumulated during the testing period.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
Reference is made to the attached drawings, wherein elements having the same reference numeral designations represent like elements throughout and wherein:
FIG. 1 is a block diagram of a packet switched system in accordance with an embodiment of the present invention.
FIG. 2 is a block diagram of a multiport switch used in the packet switched system of FIG. 1.
FIG. 3 is a partial block diagram relating to the processing and storage of MIB information.
FIG. 4 is an example of data structure for the on-chip RAM storage in the MIB engine of FIG. 3 in accordance with the present invention.
FIG. 5 is a block diagram of the MIB engine 92, shown in FIG. 3.
FIG. 6 is a flow chart that illustrates the MIB engine reset operation.
The present invention is exemplified herein in a packet switched network environment, such as an Ethernet (IEEE 802.3) network. From the following detailed description it should be apparent that the present invention, illustrated as system 10 in the block diagram of FIG. 1, is also applicable to other packet switched systems. The packet switched network includes an integrated multiport switch (IMS) 12 that enables communication of data packets between network stations. The network stations may have different configurations. In the current example, twenty-four (24) 10 megabit per second (Mb/s) network stations 14 send and receive data at a network data rate of 10 Mb/s, and two 100 Mb/s network stations 16 send and receive data packets at a network speed of 100 Mb/s. The multiport switch 12 selectively forwards data packets received from the network stations 14 or 16 to the appropriate destination, based upon Ethernet protocol.
The 10 Mb/s network stations 14 send and receive data packets to and from the multiport switch 12 via a media 18 and according to half-duplex Ethernet protocol. The Ethernet protocol ISO/IEC 8802-3 (ANSI/IEEE Std. 802.3, 1993 Ed.) defines a half-duplex media access mechanism that permits all stations 14 to access the network channel with equality. Traffic in a half-duplex environment is not distinguished or prioritized over the medium 18. Rather, each station 14 includes an Ethernet interface card that uses carrier-sense multiple access with collision detection (CSMA/CD) to listen for traffic on the media. The absence of network traffic is detected by sensing a deassertion of a receive carrier on the media. Any station 14 having data to send will attempt to access the channel by waiting a predetermined time after the deassertion of a receive carrier on the media, known as the interpacket gap interval (IPG). If a plurality of stations 14 have data to send on the network, each of the stations will attempt to transmit in response to the sensed deassertion of the receive carrier on the media and after the IPG interval, resulting in a collision. Hence, the transmitting station will monitor the media to determine if there has been a collision due to another station sending data at the same time. If a collision is detected, both stations stop, wait a random amount of time, and retry transmission.
The 100 Mb/s network stations 16 preferably operate in full-duplex mode according to the proposed Ethernet standard IEEE 802.3×Full-Duplex with Flow Control-Working Draft (0.3). The full-duplex environment provides a two-way, point-to-point communication link between each 100 Mb/s network station 16 and the multiport switch 12, so that the IMS and the respective stations 16 can simultaneously transmit and receive data packets without collisions. The 100 Mb/s network stations 16 each are coupled to network media 18 via 100 Mb/s physical (PHY) devices 26 of type 100 Base-TX, 100 Base-T4, or 100 Base-FX. The multiport switch 12 includes a media independent interface (MII) 28 that provides a connection to the physical devices 26. The 100 Mb/s network stations 16 may be implemented as servers or routers for connection to other networks. The 100 Mb/s network stations 16 may also operate in half-duplex mode, if desired. Similarly, the 10 Mb/s network stations 14 may be modified to operate according to full-duplex protocol with flow control.
As shown in FIG. 1, the network 10 includes a series of switch transceivers 20, labelled QUEST, that perform time division multiplexing and time division demultiplexing for data packets transmitted between the multiport switch 12 and the 10 Mb/s stations 14. A magnetic transformer module 19 maintains the signal waveform shapes on the media 18. The multiport switch 12 includes a transceiver interface 22 that transmits and receives data packets to and from each switch transceiver 20 using a time-division multiplexed protocol across a single serial non-return to zero (NRZ) interface 24. The switch transceiver 20 receives packets from the serial NRZ interface 24, demultiplexes the received packets, and outputs the packets to the appropriate end station 14 via the network media 18. In the disclosed exemplified embodiment, each switch transceiver 20 has four independent 10 Mb/s twisted-pair ports and uses 4:1 multiplexing across the serial NRZ interface enabling a four-fold reduction in the number of PINs required by the multiport switch 12.
The multiport switch 12 contains a decision making engine, switching engine, buffer memory interface, configuration/control/status registers, management counters, and MAC (media access control) protocol interface to support the routing of data packets between the Ethernet ports serving the network stations 14 and 16. The multiport switch 12 also includes enhanced functionality to make intelligent switching decisions, and to provide statistical network information in the form of management information base (MIB) objects to an external management entity, as described below. The multiport switch 12 also includes interfaces to enable external storage of packet data and switching logic in order to minimize the chip size of the multiport switch 12. For example, the multiport switch 12 includes a synchronous dynamic RAM (SDRAM) interface 32 that provides access to an external memory 34 for storage of received frame data, memory structures, and MIB counter information. The memory 34 may be an 80, 100 or 120 MHz synchronous DRAM having a memory size of 2 or 4 Mb.
The multiport switch 12 also includes a management port 36 that enables an external management entity to control overall operations of the multiport switch 12 by a management MAC interface 38. The multiport switch 12 also includes a PCI interface 39 enabling access by the management entity via a PCI host and bridge 40. Alternatively, the PCI host and bridge 40 may serve as an expansion bus for a plurality of IMS devices.
The multiport switch 12 includes an internal decision making engine that selectively transmits data packets received from one source to at least one destination station. In lieu of the internal decision making engine, an external rules checker may be utilized. External rules checker interface (ERCI) 42 allows use of an external rules checker 44 to make frame forwarding decisions in substitution for the internal decision making engine. Hence, frame forwarding decisions can be made either by the internal switching engine or the external rules checker 44.
The multiport switch 12 also includes an LED interface 46 that clocks out the status of conditions per port and drives LED external logic 48. The LED external logic 48, in turn, drives LED display elements 50 that are human readable. An oscillator 30 provides a 40 MHz clock input for the system functions of the multiport switch 12.
FIG. 2 is a more detailed block diagram example of the multiport switch 12 shown in FIG. 1. The multiport switch 12 includes twenty-four (24) 10 Mb/s media access control (MAC) ports 60 for sending and receiving data packets in half-duplex between the respective 10 Mb/s network stations 14 (ports 1-24), and two 100 Mb/s MAC ports 62 for sending and receiving data packets in full-duplex between the respective 100 Mb/s network stations 16 (ports 25, 26). As described above, the management interface 36 also operates according to MAC layer protocol (port 0). Each of the MAC ports 60, 62 and 36 has a receive first-in-first-out (FIFO) buffer 64 and transmit FIFO buffer 66. Data packets from a network station are received by the corresponding MAC port and stored in the corresponding receive FIFO buffer 64. The received data packet is output from the corresponding receive FIFO buffer 64 to the external memory interface 32 for storage in the external memory 34.
The header of the received packet is also forwarded to a decision making engine, comprising an internal rules checker 68 and an external rules checker interface 32, to determine which MAC ports will output the data packet. Whether the packet header is forwarded to internal rules checker 68 or external rules checker interface 42 is dependent on the operational configuration of multiport switch 12. Use of the external rules checker 44 provides advantages such as increased capacity, a random-based ordering in the decision queue that enables frame forwarding decisions to be made before the frame is completely buffered to external memory, and enables decisions to be made in an order independent from the order in which the frames were received by the multiport switch 12.
The internal rules checker 68 and external rules checker 44 provide the decision making logic for determining the destination MAC port for a given data packet. The decision making engine may indicate that a given data packet is to be output to either a single port, multiple ports, or all ports (i.e., broadcast). Each data packet includes a header having source and destination address, in accordance with which the decision making engine can identify the appropriate output MAC port(s). The destination address may correspond to a virtual address, in which case the decision making engine identifies output ports for a plurality of network stations. Alternatively, a received data packet may include a VLAN (virtual LAN) tagged frame according to IEEE 802.1d protocol that specifies another network (via a router at one of the 100 Mb/s stations 16) or a prescribed group of stations. Hence, the internal rules checker 68 or the external rules checker 44 via the interface 42 will decide whether a frame temporarily stored in the buffer memory 34 should be output to a single MAC port or multiple MAC ports.
The decision making engine outputs a forwarding decision to a switch subsystem 70 in the form of a port vector identifying each MAC port that should receive the data packet. The port vector from the appropriate rules checker includes the address location storing the data packet in the external memory 34, and the identification of the MAC ports to receive the data packet for transmission (e.g., MAC ports 0-26). The switch subsystem 70 fetches the data packet identified in the port vector from the external memory 34 via the external memory interface 32, and supplies the retrieved data packet to the appropriate transmit FIFO 66 of the identified ports.
Additional interfaces provide management and control information, as exemplified by the following elements. A management data interface 72 enables the multiport switch 12 to exchange control and status information with the switch transceivers 20 and the 100 Mb/s physical devices 26 according to the MII management specification (IEEE 802.3u). The management data interface 72 also outputs a management data clock (MDC) providing a timing reference on the bidirectional management data IO (MDIO) signal path. The PCI interface 39 is a 32-bit PCI revision 2.1 compliant slave interface for access by the PCI host processor 40 to internal IMS status and configuration registers 74, and access external memory SDRAM 34. The PCI interface 39 can also serve as an expansion bus for multiple IMS devices. The management port 36 interfaces to an external MAC engine through a standard seven-wire inverted serial GPSI interface, enabling a host controller access to the multiport switch 12 via a standard MAC layer protocol.
The processing and storage of MIB information is illustrated by the partial block diagram of FIG. 3. The dotted line boundary delineates a portion of the IMS logic chip. Each of MACs 60, collectively illustrated as a single block, generates a MIB report that details the transmission activity at its port for each transmitted or received data frame. Each MIB report is formulated according to a compression scheme whereby the report packet is allocated specific bit groupings, or fields, that correspond to particular MIB information. The report is sent from the MAC through a MIB report interface 90 to MIB engine 92. For the embodiment illustrated in FIGS. 1 and 2, the IMS may have 34 MIBs per each 10 Mb/s port including the Management port, 36 MIBs per each 100 Mb/s port and one MIB for the whole chip. The MIB engine will accumulate the received data in its own temporary RAM storage, associate the data with respective MIBs, and update MIB information in the external memory 34. The counters preferably are grouped in memory by port. IMS MIB counters are mapped into the external memory 34 and are accessible to the PCI Host processor 40 through PCI interface 39. Only the lower n bits of all port MIBs are maintained on-chip while the full versions are in the external memory, thereby conserving on-chip RAM space. The full-length MIBs in the external memory are periodically transferred to the chip via control bus 94 and are updated before they are written back to the external memory via the control bus.
The full-length MIB counters kept in the external memory can be accessed at any time, either by the external host or by the on-chip MIB engine for updating. Periodically, MIBs that belong to each port are brought into the IMS MIB engine to be updated. A round-robin schedule by port can be used with repetition every 45 msecs. MIB object counts for each port can be transferred from the external memory to the MIB engine for updating as often as every msec. The number of bits kept on-chip for each MIB may be determined according to the worst case situations that can occur within this period.
An advantage of the present invention is that information of statistical interest, i.e., MIB objects, can be accumulated and counted for storage in the external memory through the use of MAC generated MIB reports that contain the necessary information in compressed form. The MIB engine decodes the MIB report data into MIB objects to be accumulated temporarily on-chip and later to be used for updating the external memory. Examples of MIB objects that may be of statistical interest are the following: The number of times a receive packet was dropped due to lack of resources in an IMS port, e.g., receive FIFO overflow. The number of bytes received by a port. The number of valid packets received by a port that are addressed to a broadcast address. The number of valid packets received by a port that are addressed to a multicast address. The number of valid packets received by a port that are not addressed to a multicast address or a broadcast address. The number of valid packets received by a port that are less than 64 bytes long and do not have any error. The number of valid packets received by a port that are less than 64 bytes long and do have an error. The number of received valid packets that are greater than a set maximum length value, typically 516 packets, without error. The number of received valid packets that are greater than a set value with error. The number of times a packet was not transmitted due to lack of resources in an IMS port, e.g., transmit FIFO underrun. The number of bytes transmitted from a port. The number of packets transmitted from a port (with or without errors). The number of valid packets transmitted from a port that are addressed to a multicast address, or to a broadcast address. The number of collisions that occur on a port during transmission attempts. These examples are typical considerations at present and do not comprise an exhaustive catalog. A preferred data structure for the on-chip RAM storage of the MIB objects is exemplified by FIG. 4. The external memory may be similarly structured with a larger capacity sufficient to hold full updated values.
MIR report structures for transmission (xmt) packets and reception (rcv) packets, which are comprised of fewer fields than the number of different stored MIB objects, are exemplified in the following tables.
Example of transmit report structure:
______________________________________Bits Parameters______________________________________0 xmt/rcv5:1 port #16:6 octets18:17 unicast 00; multicast 01; broadcast l019 underrun24:20 number of collisions25 late collision26 deferred transmit27 pause control packet (100 Mb/s)28 tagged port & tagged frame______________________________________
Example of receive report structure:
______________________________________Bits Parameters______________________________________0 xmt/rcv5:1 port #16:6 octets18:17 unicast 00; multicast 01; broadcast 1019 alignment error20 FCS error21 fragment22 jabber23 excessive size24 missed packet25 pause control pkt (100 Mb/s port)26 tagged port & tagged frame______________________________________
Several different kinds of errors are represented by bit locations 19, et sec. Processing and expansion of the MIB report information for updating the MIB objects are performed by the MIB engine 92.
FIG. 5 is a block diagram of the MIB engine 92, shown in FIG. 3. MIB report processor 102 has an input for receiving MIB reports from the MIB report interface. The output of the MIB report processor is connected to 88-bit adder 104. The 88-bit adder has a second input connected to accumulation storage 106. Accumulation storage 106 may comprise registers, such as flip-flop counters that can contain 16.2 μsecs worth of events. The output of 88-bit adder is connected to the input of accumulation storage 106. Temporary register 108 is configured to receive output from accumulation storage 106 and to feed a first input of 32 bit adder 110. A second input to the 32 bit adder is configured to receive input from full MIBs temporary single port store 112. Store 112, which may comprise RAM memory, serves as a buffer mailbox for full length MIBs to be transferred to, or received from, the external memory. Inputs to the 32 bit adder are received from the output of the 32 bit adder and the external memory via DMA control 114.
In operation, a MIB report is received in the MIB engine by the MIB report processor 102. The MIB report processor expands the MIB report into the various MIB objects that make up the MIB set, basically by decoding the bits into internal registers. While some of the fields of the MIB report, as exemplified by the tables above set forth, may be common to the fields of the MIB object structure illustrated in FIG. 4, information from the remaining MIB report packet must be processed for allocation to the stored structure. The following instances serve as examples. The MIB object denoted "RcvUndersize Pkts" in FIG. 4 is derived from the "octets" field and the "fragment" field of the MIB rcv report table. The processor determines that the object is to be incremented if the reported received octets are less than 64 and no fragments have been received. The "ReceiveOversizePackets" object is determined to exist if the number of received packets is greater than a maximum length but not a "jabber." A jabber is indicative of an extremely long stream of data far in excess of maximum packet length. Determination of the "RcvGoodOctets" object is made if the received octets is between 64 and the maximum length and no errors are indicated. Processing of the MIB report for determining the remaining MIB objects occurs in similar fashion, applying the appropriate conditions and relationships among the received report data.
An appropriate row from accumulation storage 106, for the MAC port that corresponds to the received MIB report, is applied to 88-bit adder 104. The processed MIB report data is added to the data retrieved from the accumulation storage and the contents are then written back thereto. While this process is represented in the drawing figure by single lines, a number of MIB additions preferably can be performed in parallel for the particular MIB fields to be updated. The adder can be internally structured to include several adders in parallel to total 88 bit addition. Parallel processing in this manner can accommodate the fast rate at which MIB reports from the plurality of MAC ports are received.
While the capacity of the accumulation storage is limited to conserve chip space, sufficient storage is provided to process several MIB reports. The number of bits kept on-chip for each MIB is determined according to the worst case situations that can occur within the 45 msec MIB report period. Updating can occur as frequently as every 1 msec. As an example of the internal structure of the accumulation storage, four 88 bit rows can be allocated for the data of each port. The length of each segment that accommodates a MIB field may vary in relation to MIB size. The parallel processing of the 88 bit adder thus can direct the MIBs of the row retrieved from accumulation storage to each of the parallel adders within the 88 bit adder.
The external memory is accessed through DMA controller 114. Each time the full-length MIBs of one port are ready to be updated inside the chip, the portion that maps to this particular port is accessed from the external memory and temporarily loaded to single port store 112. This data is read line by line into 32 bit adder 110 to which the accumulated new MIR report data, input from temporary register 108, is added. This addition is applied to one or more MIBs at a time that can be accommodated by the 32 bit width of the adder. The updated values are written back in the temporary single port store before being transferred back to external memory. The contents of the accumulation storage portion allocated to the updated port information is emptied upon updating. The updating process occurs for each port in turn and repeated continually to ensure that the accumulation storage does not overflow.
As thus described, the updating process for the external memory is ongoing during normal operation under the control of the MIB engine. For each updating event, the relevant portion of accumulation storage 106 is cleared to maintain sufficient storage for further accumulation of data without overflow. Various external circumstances may render appropriate a reset of the MIB engine to clear all its logic elements. Such reset is effected in response to a command from the host. For example, the host will retrieve MIB data from the external memory to perform statistical processing. Thereafter, the external memory may be cleared and the MIB engine reset to zero.
In addition, various tests may be performed to check the operation of the major MIB interfaces. Basic tests can then be undertaken, for example, for checking the timings of the control bus, for checking proper operation of the PCI interface, and for checking MIB updating operations. More advanced tests involve introducing multiple MIB reports as fast as possible in back to back fashion and checking for errors in the results read out. These MIB reports may be introduced either by a port or from an external source. Further tests can be performed under varying conditions.
In a test operation, the MIB engine is cleared so that only data monitored during a test period is accumulated in the MIB engine. This data can be directly accessed by the host, without updating the external memory. At the end of the test period, the MIB engine can again be reset to resume normal operation data accumulation. The external memory may or may not need to be cleared during the test period, after which period normal updating of the external memory will continue.
FIG. 6 is a flow chart that illustrates the MIB engine reset operation. Under control of the external host 40, a MID reset packet can be transmitted through the PCI interface to be held in register 96, contained in the PCI control/status registers block 74, illustrated in FIG. 2. The reset packet, illustrated in the register 96 in FIG. 3, contains a significant bit that indicates reset condition in one binary state and non-reset, or normal, operational condition, in the other binary state. Receipt of the packet is represented at step 120. Decision block, step 122, represents a determination of the binary state of the significant bit in the register 96. If the bit does not indicate reset, then normal operation proceeds as indicated at step 124. During normal operation register 96 is continually monitored to determine whether a change in the binary state of the bit has occurred.
If a reset condition is determined in step 122, MIB engine storage and registers are cleared at step 126. The reset operation may clear all such elements in the MIB engine with the possible exception of the temporary single port store 112, as the latter would be completely rewritten during the next external memory update occurrence. The cleared MIB elements will remain in the cleared state until another packet, indicative of termination of the reset condition, is received at register 96.
The duration of the reset condition is dependent upon conditions such as whether external processing is to take place and/or whether the external memory is to be cleared before normal MIB engine operation is to resume. If it is determined at step 128 that the binary state of the significant bit of the register 96, i.e., reset packet, has not changed, the MIB engine is placed in a wait state, as indicated at step 130. During the wait state period, the registered is continuously monitored. When step 128 determines that reset bit has changed, normal operation resumes, as indicated again at step 124. This reset operation occurs independently of other chip elements. Global reset commands, such as at power up of the device, may originate internally or from a source other than the host 40. As the MIB engine should be cleared at power up, packets can be sent to register 96 in response to a global reset condition to effect this same operation.
The present invention thus advantageously provides a multiport switch from which an increased quantity of MIB information may be obtained in fast and efficient manner. A minimum of on-chip space is provided for temporary MIB storage and interaction with external memory for continual updating. MIB reporting is performed by compressing information into a packet at the site of the port and immediately transferred for decompression and accumulation. Reset of the MIB related storage elements is effected independently of other chip logic elements.
Only the preferred embodiment of the invention and but a few examples of its versatility are shown and described in the present disclosure. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.
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|International Classification||H04L12/28, H04L12/18, H04L12/50, H04L13/08, G06F12/00, G06F13/10, G06F13/24, H04J3/24, G06F15/16, H04L12/44, G06F13/00, H04J3/22, G08B5/00, G06F11/26, H04L12/46, H04L12/66, G06F13/16, H04L12/24, H04Q11/00, G06F15/00, H04B7/14, H04Q3/545, H04J3/12, G11C11/412, H04L12/413, H04L12/54, H04L12/933, H04L12/931, H04L12/937, H04L12/879, H04L12/947, H04L12/861, H04L12/863, H04L12/939, H04L12/935, H04J3/02|
|Cooperative Classification||H04Q2213/13162, H04L49/351, H04L49/9084, H04L49/552, H04L49/103, H04L49/901, H04L49/40, H04L49/3027, H04Q3/54591, H04L49/50, H04L12/5693, H04L49/9047, H04L12/1863, H04L49/354, H04L49/201, H04L49/9078, H04L49/30, H04L49/90, G11C11/412, H04L49/255, H04L12/467, H04Q2213/1316, H04L12/4645, H04L47/6225, G06F13/24, H04L49/3009, G06F13/1605, H04L49/9063, H04L49/555, H04L12/4641, H04L49/3054, H04L49/9073, H04L41/0213, H04L49/25|
|European Classification||H04L49/30C, H04L41/02B, G06F13/24, H04L47/62D1, H04L49/90Q3, H04L49/90, H04L49/25E3, H04L49/90R, H04L49/35A, H04L49/30, H04L49/30A, H04L49/90Q, H04L49/35D, H04L49/90M, H04L12/46V, H04L49/90C, H04Q3/545T2, G06F13/16A, H04L49/55C, H04L49/25, H04L49/20A, H04L49/50, G11C11/412, H04L49/10E, H04L49/90Q1A, H04L12/56K, H04L49/55A|
|Jun 8, 1998||AS||Assignment|
Owner name: ADVANCED MICRO DEVICES, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SIMMONS, PHILIP;ERIMLI, BAHADIR;REEL/FRAME:009234/0903;SIGNING DATES FROM 19980421 TO 19980511
|Mar 31, 2003||FPAY||Fee payment|
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|Jun 11, 2003||REMI||Maintenance fee reminder mailed|
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|Apr 22, 2011||FPAY||Fee payment|
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