|Publication number||US6965145 B2|
|Application number||US 10/394,417|
|Publication date||Nov 15, 2005|
|Filing date||Mar 19, 2003|
|Priority date||Mar 19, 2002|
|Also published as||US20030223288|
|Publication number||10394417, 394417, US 6965145 B2, US 6965145B2, US-B2-6965145, US6965145 B2, US6965145B2|
|Inventors||Kyu Hyun Choi|
|Original Assignee||O2Ic, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (31), Referenced by (9), Classifications (5), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present application claims benefit of the filing date of U.S. provisional application No. 60/366,046 filed on Mar. 19, 2002, entitled “Integrated RAM and Non-Volatile DRAM Memory Cell Method And Structure,” the entire content of which is incorporated herein by reference.
The present application is related to copending application Ser. No. 10/394,407, now U.S. Pat. No. 6,798,008, issued Sep. 28, 2004, entitled “Non-Volatile Dynamic Random Access Memory,” filed contemporaneously herewith, assigned to the same assignee, and incorporated herein by reference in its entirety.
The present invention relates to semiconductor integrated circuits. More particularly, the invention provides a semiconductor memory that has integrated non-volatile and dynamic random access memory cells. Although the invention has been applied to a single integrated circuit device in a memory application, there can be other alternatives, variations, and modifications. For example, the invention can be applied to embedded memory applications, including those with logic or micro circuits, and the like.
Semiconductor memory devices have been widely used in electronic systems to store data. There are generally two types of memories, including non-volatile and volatile memories. The volatile memory, such as a Static Random Access Memory (SRAM) or a Dynamic Random Access Memory (DRAM), loses its stored data if the power applied has been turned off. SRAMs and DRAMs often include a multitude of memory cells disposed in a two dimensional array. Due to its larger memory cell size, an SRAM is typically more expensive to manufacture than a DRAM. An SRAM typically, however, has a smaller read access time and a lower power consumption than a DRAM. Therefore, where fast access to data or low power is needed, SRAMs are often used to store the data.
Non-volatile semiconductor memory devices are also well known. A non-volatile semiconductor memory device, such as flash Erasable Programmable Read Only Memory (Flash EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM) or, Metal Nitride Oxide Semiconductor (MNOS), retains its charge even after the power applied thereto is turned off. Therefore, where loss of data due to power failure or termination is unacceptable, a non-volatile memory is used to store the data.
Unfortunately, the non-volatile semiconductor memory is typically slower to operate than a volatile memory. Therefore, where fast store and retrieval of data is required, the non-volatile memory is not typically used. Furthermore, the non-volatile memory often requires a high voltage, e.g., 12 volts, to program or erase. Such high voltages may cause a number of disadvantages. The high voltage increases the power consumption and thus shortens the lifetime of the battery powering the memory. The high voltage may degrade the ability of the memory to retain its charges-due to hot-electron injection. The high voltage may cause the memory cells to be over-erased during erase cycles. Cell over-erase results in faulty readout of data stored in the memory cells.
The growth in demand for battery-operated portable electronic devices, such as cellular phones or personal organizers, has brought to the fore the need to dispose both volatile as well as non-volatile memories within the same portable device. When disposed in the same electronic device, the volatile memory is typically loaded with data during a configuration cycle. The volatile memory thus provides fast access to the stored data. To prevent loss of data in the event of a power failure, data stored in the volatile memory is often also loaded into the non-volatile memory either during the configuration cycle, or while the power failure is in progress. After power is restored, data stored in the non-volatile memory is read and stored in the non-volatile memory for future access. Unfortunately, most of the portable electronic devices may still require at least two devices, including the non-volatile and volatile, to carry out backup operations. Two devices are often required since each of the devices often rely on different process technologies, which are often incompatible with each other.
To increase the battery life and reduce the cost associated with disposing both non-volatile and volatile memory devices in the same electronic device, non-volatile SRAMs and non-volatile DRAMs have been developed. Such devices have the non-volatile characteristics of non-volatile memories, i.e., retain their charge during a power-off cycle, but provide the relatively fast access times of the volatile memories. As merely an example,
EEPROM 18 of non-volatile DRAM cell 10 (
While the invention is described in conjunction with the preferred embodiments, this description is not intended in any way as a limitation to the scope of the invention. Modifications, changes, and variations, which are apparent to those skilled in the art can be made in the arrangement, operation and details of construction of the invention disclosed herein without departing from the spirit and scope of the invention.
In accordance with the present invention, a non-volatile memory device (hereinafter alternatively referred to device) includes a guiding gate that extends along a first portion of the device's channel length and a control gate that extends along a second portion of the device's channel length. The first and second portions of the channel length do not overlap. The guiding gate, which overlays the substrate above the channel region, is insulated from the semiconductor substrate in which the device is formed via an oxide layer. The control gate, which also overlays the substrate above the channel region, is insulated from the substrate via an oxide-nitride-oxide layer.
In some embodiment of the present invention, the thickness of the oxide layer formed above the guiding gate is greater than the thickness of the oxide layer formed above the control gate. In other embodiments, the thickness of the oxide layer formed above the control gate is greater than the thickness of the oxide layer formed above the guiding gate.
The device includes five terminals, namely a source terminal coupled to the device's source region, a drain terminal coupled to the device's drain region, a guiding gate terminal coupled to the device's guiding gate, a control gate terminal coupled to the device's control gate, and a substrate terminal coupled to the semiconductor substrate in which the device is formed.
To program the device, a first voltage is applied between the control gate terminal and the substrate terminal, a second voltage is applied between the guiding gate terminal and the substrate terminal, and a third voltage is applied between the drain and source terminals. The application of these voltages causes two non-overlapping channel regions to be formed in the substrate. Subsequently, a channel connecting the source to drain region is formed in the substrate. As the electrons drift from source to the drain due to the established electric filed, the electrons tunnel through or are injected in the oxide layer and are trapped in the nitride layer due to hot electron injection. The injected electrons remain trapped in the nitride layer even after power is turned off.
To erase the device after it is programmed, a negative voltage is applied between the control gate terminal and the substrate terminal, a positive voltage is applied between the drain and substrate terminals and the guiding gate terminal is left floating or is coupled to the ground potential. The application of these voltages causes the electrons trapped in the nitride layer to tunnel through the oxide layer—due to Fowler-Nordheim tunneling—and return to the substrate 206 and/or holes to tunnel through the oxide layer and be trapped in the nitride layer to neutralize the trapped electrons.
To read the data stored in the device, relatively small voltages are applied to each of the drain, control and guiding gates. The application of these voltages causes a current to flow from the source to the drain region. The size of this current depends on whether the device is programmed or not.
The accompanying drawings, which are incorporated in and form part of the specification, illustrate embodiments of the invention and, together with the description, sever to explain the principles of the invention.
According to the present invention, an improved non-volatile memory device and method is provided. Although the invention has been applied to a single integrated circuit device in a memory application, there can be other alternatives, variations, and modifications. For example, the invention can be applied to embedded memory applications, including those with logic or microcircuits, and the like.
In some embodiments, oxide layer 208 has a thickness ranging from 20 Å to 60 Å, and each of nitride layer 210 and oxide layer 212 has a thickness ranging from 30 Å to 10 Å (
Furthermore, in these embodiments, a second portion of channel length defined between the left vertical edge of drain region 204 and the left vertical edge of nitride layer 210 that is positioned above gate oxide layer 208—shown as distance L2—is less than or equal to the minimum distance allowed by the manufacturing technology. For example, if device 200 is manufactured using 0.18μ CMOS technology, distance L1 may vary from, e.g., approximately 0.06μ to approximately 0.18μ; if device 200 is manufactured using 0.25μ CMOS technology, distance L2 may vary from, e.g., approximately 0.08μ to approximately 0.25μ.
Oxide layer 214 also has a thickness defined by the technology used to manufacture cell 202. For example, oxide layer 214 may have a thickness of 70 Å if 0.35μ CMOS technology is used to manufacture device 200. Similarly, oxide layer 214 may have a thickness of 50 Å if 0.25μ CMOS technology is used to manufacture device 200; oxide layer 214 may have a thickness of 40 Å if 0.18μ CMOS technology is used to manufacture device 200; oxide layer 214 may have a thickness of 20 Å if 0.09μ CMOS technology is used to manufacture device 200.
In some embodiments, oxide layer 308 has a thickness ranging from 20 Å to 50 Å, and each of nitride layer 310 and oxide layer 312 has a thickness ranging from 30 Å to 100 Å (
Furthermore, in these embodiments, a second portion of channel length defined between the left vertical edge of drain region 304 and the left vertical edge of nitride layer 310 that is positioned above gate oxide layer 308—shown as distance L4—is less than or equal to the minimum distance allowed by the manufacturing technology. For example, if device 300 is manufactured using 0.18μ CMOS technology, distance L3 may vary from, e.g., approximately 0.06 μto approximately 0.18μ; if device 300 is manufactured using 0.25μ CMOS technology, distance L4 may vary from, e.g., approximately 0.08μ to approximately 0.25μ.
Oxide layer 314 also has a thickness defined by the technology used to manufacture device 300. For-example, oxide layer 314 may have a thickness of 70 Å if 0.35μ CMOS technology is used to manufacture device 300. Similarly, oxide layer 314 may have a thickness of 50 Å if 0.25μ CMOS technology is used to manufacture device 300; oxide layer 314 may have a thickness of 40 Å if 0.18μ CMOS technology is used to manufacture device 300.
The programming, erase and read operations of device 200 is described below. It is understood that device 300 operates in the same manner as device 200 and thus is not discussed below.
To program device 200, a relatively high first programming voltage in the range of, e.g., 4 to 12 volts is applied between gate 230 and substrate 206, while at the same time a second voltage in the range of, e.g., 0.5 to 1.5 volts is applied between gate 220 and substrate 206, and a third voltage in the range of, e.g., 3 to 5 volts is applied between drain 204 and source 202. The application of these voltages causes n-type channel regions of approximate lengths L1 and L2 to be formed in substrate 206 (not shown). As the electrons drift from source 202 to drain 204 due to the established electric filed (not shown), the electrons tunnel through the oxide layer overlaying substrate 206 and are trapped in nitride layer 210 due to hot electron injection. The injected electrons remain trapped in nitride layer 210 even after power is turned off. The trapped electrons, in turn, increase the threshold voltage of device 200. The relatively high electric field in region 240 of substrate 206 is so adapted as to cause the hot electron injection to occur. Subsequently, an n-type channel is also formed in region 240, thereby causing n-type to connect source 202 and drain 204.
To erase a programmed device, a relatively high negative voltage, e.g., −10 volts is applied to gate 230, approximately 0 to 1 volt is applied to drain region 204, approximately 0 volt is applied to substrate region 206, and guiding gate 220 is left floating or is supplied with 0 or −1 volt. The application of these voltages causes the electrons trapped in nitride layer 210 to tunnel through the oxide layer—due to Fowler-Nordheim tunneling—and return to substrate 206 and/or holes to tunnel through the oxide layer overlaying substrate 206 and be trapped in nitride layer 210 due to hot hole injection so as to neutralize the trapped electrons. The tunneling of trapped electrons back to substrate 206 and/or trapping of holes in nitride layer 210 causes the programmed non-volatile cell 102 to erase. The erase operation causes device 200's threshold to retune to its pre-programming value.
A second way to erase non-volatile device 200 is by injecting hot holes into nitride layer 212. To cause hot hole injection, substrate 206 is pulled to the Vss or a negative voltage, e.g., in the range of −1 to −3 volts. Another voltage in the range of, e.g., 0 to −10 volts is applied to control gate 230. Guiding gate 220 is maintained at the ground or a negative potential, e.g., −1 to −3 volts. A positive voltage pulse of magnitude of 3 to 7.5 is applied to drain terminal 204. Accordingly, a strong depletion region is formed between drain region 204 and substrate region 206. This depletion region causes a relatively narrow region having a high electric field across it. Therefore, band-to-band tunneling takes place causing electrons to tunnel from the surface valence band toward the conduction band, thereby generating holes. The holes so generated drift toward the substrate. Some of these holes gain sufficient energy to inject through the oxide and be trapped in the nitride layer. The injected holes neutralize any electrons that are trapped in the nitride layer, thereby causing the threshold voltage of non-volatile device 52 to return to its pre-programmed (i.e., erased) state.
To read the data stored in non-volatile device 200, a first voltage in the range of, e.g., 1 to 1.5 volts, is applied to drain 204, a second voltage in the range of, e.g., 2 to 3.5 volts is applied to control gate 230, and a third voltage in the range of, e.g., 1 to 3.5 volts is applied to guiding gate 220. The application of these voltages causes a current to flow from source 202 to drain 204. As is known by those skilled in the art, if device 200 is programmed, due to its increased threshold voltage, a relatively small amount or no current flows from source 202 to drain 204. If device 200 is not programmed or erased, a relatively larger amount of current flows from source 202 to drain 204. A sense amplifier (not shown) senses the current that flows from source 202 and drain 204 and by sensing the size of this current determines whether device 200 is programmed or not.
The above embodiments of the present invention are illustrative and not limitative. The invention is not limited by the type of integrated circuit in which the memory device of the present invention is disposed. For example, the memory device, in accordance with the present invention, may be disposed in a programmable logic device, a central processing unit, and a memory having arrays of memory cells or any other IC which is adapted to store data.
While the invention is described in conjunction with the preferred embodiments, this description is not intended in any way as a limitation to the scope of the invention. Modifications, changes, and variations, which are apparent to those skilled in the art, can be made in the arrangement, operation and details of construction of the invention disclosed herein without departing from the spirit and scope of the invention.
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|U.S. Classification||257/326, 257/366|
|Jun 2, 2003||AS||Assignment|
Owner name: O2IC, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHOI, KYU HYUN;REEL/FRAME:014130/0810
Effective date: 20030505
|May 25, 2009||REMI||Maintenance fee reminder mailed|
|Nov 15, 2009||LAPS||Lapse for failure to pay maintenance fees|
|Jan 5, 2010||FP||Expired due to failure to pay maintenance fee|
Effective date: 20091115