|Numéro de publication||US6069817 A|
|Type de publication||Octroi|
|Numéro de demande||US 09/201,694|
|Date de publication||30 mai 2000|
|Date de dépôt||30 nov. 1998|
|Date de priorité||3 déc. 1997|
|État de paiement des frais||Caduc|
|Numéro de publication||09201694, 201694, US 6069817 A, US 6069817A, US-A-6069817, US6069817 A, US6069817A|
|Inventeurs||Dong-won Shin, Jin-woo Lee|
|Cessionnaire d'origine||Samsung Electronics Co., Ltd.|
|Exporter la citation||BiBTeX, EndNote, RefMan|
|Citations de brevets (6), Citations hors brevets (4), Référencé par (9), Classifications (16), Événements juridiques (6)|
|Liens externes: USPTO, Cession USPTO, Espacenet|
The present invention relates to evaluation methods for microelectronic devices, and more particularly, to methods of evaluating ferroelectric devices.
Ferroelectric memory devices typically include one or more arrays of ferroelectric capacitors that are used as data storage elements. A ferroelectric capacitor typically includes a dielectric formed from a ferroelectric material, disposed between respective conductive "plate" and "storage" electrodes. When a sufficient voltage is applied across the electrodes of the ferroelectric capacitor, the ferroelectric material exhibits a persistent polarization wherein the dipoles of the ferroelectric material arrange themselves along in a predetermined direction. This polarization state remains even when the applied electric field is removed. Thus, ferroelectric capacitors can and have been used as data storage devices.
A typical hysteresis characteristic for a ferroelectric capacitor is shown in FIG. 1, in which the horizontal axis represents a voltage applied across the electrodes of a ferroelectric capacitor, and the vertical axis represents polarization of the ferroelectric dielectric of the capacitor. As illustrated in FIG. 1, polarization of a ferroelectric dielectric occurs according to a predetermined hysteresis loop. When a positive voltage applied to the ferroelectric-dielectric film reaches a predetermined magnitude (point B), a positive polarization +Pm is induced. When the voltage applied to the dielectric is decreased to 0V, the ferroelectric dielectric remains positively polarized at a positive remnant polarization +Pr (point C). If the applied voltage is then sufficiently decreased (point D), a polarization reversal is induced, producing a negative polarization -Pm. Then, when the applied voltage is increased to 0V, the ferroelectric dielectric remains negatively polarized at a negative remnant polarization -Pr (point A). If the applied voltage is sufficiently increased (point B), the ferroelectric dielectric will undergo another polarization reversal back to a positive polarization state (point B).
Conventional processes for testing ferroelectric memory devices typically include a direct current (DC) test that tests the operation of input/output protection circuits connected to the ferroelectric capacitor memory array. This DC test typically is followed by an alternating current (AC) test that tests the polarization characteristics of the ferroelectric capacitors, as well as operation of associated peripheral circuits such as sense amplifiers. This AC test typically requires a long time to complete.
In light of the foregoing, it is an objective of the present invention to provide methods for evaluating ferroelectric memory devices that can provide for reduced testing time and improved process efficiency.
This and other objects, features and advantages are provided according to the present invention by methods for evaluating ferroelectric memory devices on a microelectronic substrate, e.g., a semiconductor wafer, in which polarization characteristics are determined for a plurality of test ferroelectric capacitors formed on the same wafer as the memory device, and the polarization characteristics for the test capacitors are used to estimate inputs to the sense amplifiers of the memory device to determine whether the ferroelectric capacitors of the memory device are likely to provide sufficient discrimination to operate correctly with the sense amplifiers of the device. For example, respective mean values and standard deviations for switching and non-switching charge levels of the test capacitors may be determined, and then used to determine an input charge that is compared to a minimum sensing charge for the sense amplifier. The switching and non-switching charges may be determined by a simplified test that can be completed in a shorter time than conventional AC tests, thus providing a way to pre-screen wafers before they are sent on for AC testing or other processing.
In particular, according to the present invention, a ferroelectric memory device formed on a microelectronic substrate is tested. The memory device includes a sense amplifier and a plurality of ferroelectric capacitors that are operatively connected to the sense amplifier to read information stored in the ferroelectric capacitors. A plurality of test ferroelectric capacitors is also formed on the microelectronic substrate. Polarization characteristics are determined for the plurality of test ferroelectric capacitors. An input to the sense amplifier is estimated from the determined polarization characteristics, and the ferroelectric memory device is evaluated based on the estimated input. For example, the estimated input may be compared to an input criterion for the sense amplifier, and the ferroelectric memory device may be either rejected or subjected to further testing device depending on whether the estimated input fails to meet or meets the input criterion.
According to an aspect of the present invention, statistics for a first polarization state response and a second polarization response are generated for the plurality of test ferroelectric capacitors from the determined polarization characteristics. An input is then estimated from the generated statistics, the estimated input representing a median value between a predetermined deviation of the first polarization state response and a predetermined deviation of the second polarization state response. The statistics may comprise a mean first polarization state response, a standard deviation of the first polarization response, a mean second polarization response and a standard deviation of the second polarization response. The estimated input may represent a medial value between a first deviation from the mean first polarization response and a second deviation from the mean second polarization response.
According to yet another aspect of the present invention, a switching voltage and a non-switching voltage are determined for each of the plurality of test ferroelectric capacitors. An input voltage or charge may then be estimated from the determined switching and non-switching voltages for the plurality of test ferroelectric capacitors, and then compared to a minimum sensing voltage or charge for the sense amplifier.
According to another aspect of the present invention, a remnant polarization voltage or charge is determined for each of the plurality of test ferroelectric capacitors. An input voltage or charge may be estimated from the remnant polarization voltage or charge, and compared to a minimum sensing voltage or charge for the sense amplifier.
In another embodiment according to the present invention, a plurality of groups of parallel connected test ferroelectric capacitors is formed on the substrate with the ferroelectric memory device. Respective polarization characteristics are determined for the groups of parallel-connected test ferroelectric capacitors, and used to estimate an input to the sense amplifier that is used to evaluate the ferroelectric memory device.
According to another aspect of the present invention, a memory device that includes a sense amplifier and a plurality of storage capacitors that are operatively connected to the sense amplifier to read information stored in the storage capacitors is evaluated by forming a plurality of test storage capacitors on the same microelectronic substrate as the memory device. Output characteristics for the plurality of test storage capacitors are determined and used to estimate an input to the sense amplifier of the memory device. The memory device may then be evaluated based on the estimated input. Improved memory device testing and fabrication may thereby be provided.
FIG. 1 illustrates a typical hysteresis loop characteristic for a ferroelectric dielectric.
FIG. 2 is a schematic diagram illustrating a cell of a conventional ferroelectric memory device.
FIG. 3 is an equivalent circuit diagram of a test ferroelectric capacitor arrangement according to an embodiment of the present invention.
FIGS. 4A-4B illustrate waveforms for determining testing polarization characteristics of a ferroelectric capacitor.
FIG. 5 is a flow chart illustrating operations for evaluating a ferroelectric memory device according to an aspect of the present invention.
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
A typical configuration of a ferroelectric memory cell is provided in FIG. 2, including a ferroelectric capacitor Cf, an access transistor TA, word line WL, bit line BL, sense amplifier SA and a reference cell RC. The ferroelectric capacitor Cf has a storage electrode connected to a source (or drain) of the access transistor TA, and a plate electrode connected to the plate line PL. A gate and a drain (or source) of the access transistor TA are connected to the word line WL and the bit line BL, respectively. The bit line BL is connected to one of two inputs of the sense amplifier SA, and the other input of the sense amplifier SA is connected to the reference cell by another bit line BLr. The sense amplifier SA amplifies the difference between the voltages of the bit lines BL, BLr, and outputs information accordingly. For accurate determination of data stored in the ferroelectric capacitor Cf, the voltage difference between the bit lines BL and BLr generally must be greater than a sensing limit of the sense amplifier SA, e.g., a minimum sensing voltage. A parasitic capacitance Cbl of the bit line BL typically is much larger than the capacitance Cf. Exemplary operations for ferroelectric memory devices are described in U.S. Pat. No. 5,835,400 to Jeon et al., assigned to the assignee of the present invention and incorporated by reference herein in its entirety.
FIG. 3 is a schematic diagram of an exemplary ferroelectric capacitor test pattern or group 320 according to an embodiment of the present invention. The pattern 320 is formed on the same microelectronic substrate 300 as a ferroelectric memory device 310, e.g., a device having a memory cell structure such as that illustrated in FIG. 2. The pattern 320 includes a plurality of test ferroelectric capacitors Cf1 -Cfn that are connected in parallel. Plate electrodes and storage electrodes of the test ferroelectric capacitors are connected to a plate line PL and a bit line BL, respectively. It will be appreciated that the pattern 320 may have a construction similar to that of the ferroelectric device 310, i.e., access transistors such as the access transistor TA of FIG. 2 may be interposed between each of the storage electrodes of the test capacitors Cf1 -Cfn and the bit line BL. However, for purposes of testing polarization characteristics of the test capacitors Cf1 -Cfn, access transistors need not be formed. A capacitor Cbln having a capacitance n times the parasitic capacitance associated with a respective bit line of the ferroelectric memory device 310 may be connected between the bit line BL and a signal ground. The capacitor may be formed on the substrate 300, or may be an external capacitor positioned within external test equipment.
FIGS. 4A and 4B illustrate exemplary operations for determining polarization characteristics for a test ferroelectric capacitor pattern such as the pattern 320 of FIG. 3. In particular, FIG. 4A illustrates input voltages Vin applied to the plate line PL of the test pattern 320, while FIG. 4B illustrates output voltages Vout at the bit line BL of the test pattern 320. The test capacitors Cf1 -Cfn, are first initialized to a first polarization state by sequentially applying a positive pulse signal +Vm and a negative pulse signal -Vm to the plate line PL, such that each ferroelectric capacitor has a negative remnant polarization -Pr (see FIG. 1) after the negative pulse signal -Vm is removed.
A positive pulse signal +Vm is then applied to the plate line PL, while the output voltage Vout, of the bit line BL is measured. The positive pulse signal +Vm produces a polarization switch in the test capacitors Cf1 -Cfn, and a switching voltage Vsw on the bit line BL, e.g., a voltage corresponding to a logical switching of a ferroelectric memory element from a logic "0" to a logic "1". The plate line PL is then taken to signal ground while the bit line voltage Vout is again measured to determine a positive remnant polarization voltage V2Pr (corresponding to the polarization difference between points A and C of FIG. 1). Subsequently, while a positive pulse signal +Vm is again applied to the plate line PL, the voltage of the bit line BL is measured to determine a non-switching voltage Vnsw corresponding to the amount of charge difference between a positive maximum polarization +Pm and the positive remnant polarization +Pr (see FIG. 1). The polarization characteristics, e.g., the switching voltage Vsw, the non-switching voltage Vnsw, and the maximum remnant polarization voltage V2Pr, may be converted into a corresponding switching charge Qsw, non-switching charge Qnsw and maximum remnant polarization 2Pr, respectively, using the bit line capacitance Cbl to integrate the output voltage Vout.
The polarization characteristics described above are determined for a plurality of such test patterns 320 formed on the substrate 300, thus producing a number of sets of polarization characteristics corresponding to the number of test patterns. The number of cell test patterns must be at least two, and preferably is greater than 5 in order to obtain statistically reliable results.
Those skilled in the art will appreciate that either the switching voltage Vsw and the non-switching voltage Vnsw, or the maximum remnant polarization voltage V2Pr, may be used to determine the logic state of a ferroelectric memory element, depending on the operational characteristics of the sense amplifier circuits used in the ferroelectric memory device 310. For example, a sense amplifier of the memory device 310 may sample the bit line when the "read" voltages +Vm are applied to a ferroelectric memory cell of the device 310, e.g., the sense amplifier may sample voltages corresponding to the switching and non-switching voltages Vsw, Vnsw. Alternatively, a sense amplifier may sense the bit line voltage after the read voltage is deasserted, thus reading a voltage corresponding to difference between the positive remnant polarization +Pr and the negative remnant polarization -Pr.
Exemplary operations for estimating a sensing margin of a sense amplifier of a ferroelectric memory device will now be described. For a memory device having a sense amplifier that senses the bit line voltage while a read signal pulse is applied to the plate electrode of the cell, an estimated input Don to the sense amplifier may be determined as: ##EQU1## where Qsw,mean and Qnsw,mean represent respective mean switching and non-switching charges for the test ferroelectric capacitor patterns determined as described above, and σQsw and σQnsw represent respective standard deviations for the switching and non-switching charges.
The estimated input DON of equation (1) represents a worst case estimate of the charge applied to a sense amplifier of a ferroelectric memory device. The multiplier χ preferably is set to provide a close correlation between the test capacitor patterns and the actual ferroelectric memory storage capacitors of the device under evaluation. The sensing margin of the sense amplifier of a memory device formed on the same substrate as the test capacitor patterns represents a difference between the estimated input DON and the minimum sensing charge of the sense amplifier, obtained by multiplying the minimum sense voltage of the amplifier (obtained, for example by simulation) by bit line capacitance Cbln. Thus, comparison of the estimated input charge DON and the minimum sensing charge of the sense amplifier of a memory device can provide a high-reliability indication of whether the ferroelectric memory device will exhibit sensing errors.
For memory devices having a sense amplifier that senses the bit line voltage after the read pulse signal is de-asserted, an estimated input DOFF into the sense amplifier can be provided by:
DOFF =(2Prmean -χσ2Pr)-(Prmean +χσPr), (2)
where 2Prmean represents the mean remnant polarization 2Pr for the test ferroelectric capacitor patterns determined as described above and σ2Pr represents the standard deviation of the remnant polarization 2Pr for the test patterns, and Prmean and σ2Pr correspond to halves of the mean value 2Prmean and standard deviation σ2Pr, respectively. Similar to the estimated input DON described above, DOFF represents a "worst case" estimate of the input to a sense amplifier of a memory device that samples the bit line voltage after de-assertion of a read pulse. The estimated input charge DOFF may be compared with the minimum sensing charge of the sense amplifier to determine whether the device is likely to exhibit sensing errors.
FIG. 5 illustrates exemplary operations 500 for evaluating a ferroelectric memory device according to an embodiment of the present invention. A DC test is performed on the ferroelectric memory device (Block 1). Polarization characteristics are then determined for a plurality of test ferroelectric capacitors formed on the same substrate as the memory device, e.g., switching charges, non-switching charges and/or remnant polarization charges for a plurality of test patterns such as the pattern 320 of FIG. 3 (Block 3). An estimated input, e.g., DON or DOFF, is then computed and compared to the minimum input charge of the sense amplifier of the ferroelectric memory device (Block 5). If the estimated input charge is greater than the sensing limit of the sense amplifier, the device is subjected to further testing, e.g., an AC test (Block 7). If the estimated input charge is less than the minimum sensing charge, the device is rejected and further testing or other fabrication processing is not carried out.
According to the present invention, a ferroelectric memory device is evaluated using tests on a plurality of ferroelectric capacitors formed on the same substrate as the device. Using the test capacitors, the likelihood of the device exhibiting data sensing errors can be quickly determined without protracted AC testing. Thus, devices that have a high likelihood of exhibiting read errors can be identified before AC testing and other processing, offering potential improvements in manufacturing efficiency. Testing test capacitors can also more quickly reveal fabrication abnormalities, allowing for quicker repair of defects in the fabrication process.
The present invention is not limited to the above embodiment, and further modifications and alterations will occur to those skilled in the art. For example, the present application is also applicable to testing a device such as a dynamic random access memory (DRAM), which utilizes storage capacitors as memory storage elements. In such an embodiment, statistics for first and second logic state outputs or responses may be generated for a plurality of test storage capacitors formed on the same substrate as the DRAM under evaluation, and used to generate, for example, an estimated input voltage that will be provided to a sense amplifier of the DRAM. This estimated input may be used to determine the likelihood of read errors in the DRAM.
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
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|Classification aux États-Unis||365/145, 365/201|
|Classification internationale||G11C29/02, G11C29/50, G11C11/22, G11C29/12, H01L21/66|
|Classification coopérative||G11C29/50, G11C2029/5004, G11C11/22, G11C29/02, G11C29/026|
|Classification européenne||G11C29/02F, G11C29/50, G11C29/02, G11C11/22|
|30 nov. 1998||AS||Assignment|
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHIN, DONG-WON;LEE, JIN-WON;REEL/FRAME:009660/0312
Effective date: 19981123
|15 sept. 2003||FPAY||Fee payment|
Year of fee payment: 4
|20 sept. 2007||FPAY||Fee payment|
Year of fee payment: 8
|9 janv. 2012||REMI||Maintenance fee reminder mailed|
|30 mai 2012||LAPS||Lapse for failure to pay maintenance fees|
|17 juil. 2012||FP||Expired due to failure to pay maintenance fee|
Effective date: 20120530