Error Tolerant Caches Using Two-Dimensional Error Coding
Tuesday November 20, 2007
Hamerschlag Hall D-210
This is a practice talk for MICRO-40.
Carnegie Mellon University
In deep sub-micron ICs, growing amounts of on-die memory and scaling
effects make embedded memories increasingly vulnerable to reliability
and yield problems. As scaling progresses, soft, hard, and variability
errors in the memory system will increase in frequency and scope, and
single error events are more likely to cause large-scale multi-bit
errors. However, conventional memory protection techniques can neither
repair many defects nor detect and correct large-scale multi-bit errors
due to high VLSI overheads.
In this talk, I will present two-dimensional (2D) error coding in
embedded memories, a scalable multi-bit error protection technique to
improve memory manufacturability and reliability. The key innovation is
the use of vertical error coding across words that is used only for
error correction in combination with conventional per-word horizontal
error coding. 2D error coding can tolerate high-density defects and
large-scale multi-bit errors in embedded memories with significantly
smaller performance, area, and power overheads than conventional techniques.
Jangwoo Kim is a PhD candidate advised by Professor Babak Falsafi in
Electrical and Computer Engineering at Carnegie Mellon University. His
research interests include fault tolerant computer system and full