SANTA CRUZ, Calif. Sequence Design has announced four new patents that cover key analysis and optimization technology, according to the company. The patents cover clock tree insertion, circuit optimization, zero-skew buffer insertion, and match delay buffer insertion.
US patent 6,698,006, "Method for balanced-delay clock tree insertion," lets designers construct a clock tree with delay and skew values that can meet tighter timing constraints. US patent 6,701,505, "Circuit optimization for minimum path timing violations," describes technology that optimizes delay insertions for reducing a timing violation in a timing path.
US patent 6,701,507, "Method for determining a zero-skew buffer insertion point," computes a position for a zero-skew driver insertion point in an area occupied by nodes driven by the driver. US patent 6,701,506, "Method for match delay buffer insertion," is a technique that can add delays at a node without changing the input capacitance of the node as seen by the upstream node.
With the latest awards, Sequence Design has a total of 18 patents. The newly patented technologies are used in the company's PhysicalStudio and CoolTime products.