Alpha and Omega Semiconductor Inc.
|Alpha and Omega Semiconductor Inc. Patent applications|
|Patent application number||Title||Published|
|20130119394||Termination Structure for Gallium Nitride Schottky Diode - A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.||05-16-2013|
|20130119393||Vertical Gallium Nitride Schottky Diode - A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current.||05-16-2013|
|20130075808||Trench MOSFET with Integrated Schottky Barrier Diode - A Schottky diode includes a semiconductor layer formed on a semiconductor substrate; first and second trenches formed in the semiconductor layer where the first and second trenches are lined with a thin dielectric layer and being filled partially with a trench conductor layer and remaining portions of the first and second trenches are filled with a first dielectric layer; and a Schottky metal layer formed on a top surface of the semiconductor layer between the first trench and the second trench. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in each of the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.||03-28-2013|
|20130075746||Lateral PNP Bipolar Transistor with Narrow Trench Emitter - A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.||03-28-2013|
|20130075741||Lateral PNP Bipolar Transistor Formed with Multiple Epitaxial Layers - A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance.||03-28-2013|
|20120299569||Constant On-Time Switching Regulator Implementing Light Load Control - A control circuit for a switching regulator implements constant on-time control scheme with synchronous rectification and applies an integrated standard and light load control loop to improve light load efficiency and enhance transient response. In one embodiment, the control circuit includes a reference voltage selection circuit configured to select, based on a low-side current signal, a first reference voltage for standard load condition and a second reference voltage for light load condition as a selected reference voltage. The second reference voltage is greater than the first reference voltage. The control circuit further includes a control loop configured to generate a control signal to turn on the main switch when the feedback voltage is below the selected reference voltage and the minimum off-time duration has expired.||11-29-2012|
|20120205737||SHIELDED GATE TRENCH MOSFET DEVICE AND FABRICATION - A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.||08-16-2012|
|20110089492||High voltage semiconductor device with JFET regions containing dielectrically isolated junctions and method of fabricating the same - A high-voltage field-effect device contains an extended drain or “drift” region including an embedded stack of JFET regions separated by intervening layers of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and the floor and ceiling of each JFET region is lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region.||04-21-2011|
Patent applications by Alpha and Omega Semiconductor Inc.