BENGALURU, India A team of researchers at the Indian Institute of Technology in Kharagpur have developed new approach for testing digital modules embedded in mixed-signal VLSI circuits.
The team's methodology was based on analog backtrace, a technique that uses analog blocks themselves to test digital blocks. The methodology stresses the controllability of the inputs of the digital block by exploiting the analog block.
In a paper presented in the VLSI Design and Test 2007 held here, the team said its results were based on work done at the transfer function level. However, transistor-level simulation of analog circuits must be performed for a more realistic study, and it is on this aspect that the team is now working, the researchers said.
The investigators contend that, although problems in automatic testing and test pattern generation for digital circuits have been solved, directly applying and observing test patterns and responses is not possible when digital blocks are embedded in between analog blocks, as in mixed-signal ICs.
The team developed a methodology that enables it to exploit the analog circuits themselves to test embedded digital blocks with as little overhead as possible. They addressed the first problem in testing digital modules in mixed-signal circuits (treating the analog blocks as ideal). Next, parameter variations in the analog block were considered for developing an effective test solution. The effectiveness of the technque were verified by simulation of some analog benchmark circuits.
"Recent improvement in fabrication technology has made possible the realization of ICs containing both analog and digital functions on the same silicon. The problem of testing digital cores in the circuits is, however, more complicated than that of testing purely digital cores," the researchers said.
Because the analog blocks have direct access to the digital cores through quantizers, and because the team controlled the analog block directly, discrete Fourier transform overheads were minimized, the researchers said. "Our proposed test methodology emphasizes the controllability of the input of the digital block by exploiting the analog block."
The team said their results obtained were encouraging when work was carried out at the transfer function level. Transistor-level simulation of analog circuits will be carried out next. The algorithm also needs to include nonideal analog/digital interfaces.