|Publication number||US7410813 B1|
|Application number||US 10/948,857|
|Publication date||Aug 12, 2008|
|Filing date||Sep 23, 2004|
|Priority date||Sep 23, 2004|
|Publication number||10948857, 948857, US 7410813 B1, US 7410813B1, US-B1-7410813, US7410813 B1, US7410813B1|
|Original Assignee||National Semiconductor Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Classifications (9), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates to fault analysis of defective semiconductor devices. In particular it relates to parallel lapping of a semiconductor die.
Whenever a defect occurs in a semiconductor device it is desirable to be able to locate the source of the problem, thereby allowing the problem to be addressed. Numerous techniques have therefore been developed for locating defects in a die in the x-y plane as shown in
According to the invention there is provided a method of lapping a semiconductor die if the region of interest is located near an edge or corner of the die, comprising securing additional semiconductor material adjacent the region of interest. Preferably the semiconductor material placed adjacent the region of interest is of the same material as the die itself and are preferably obtained from the same wafer as the die. The additional semiconductor material may be secured to the die, for example, by means of an adhesive such as a heat curable resin. Instead the additional semiconductor material may be secured to a common surface as the die such as a sample holder. In the latter situation, the additional semiconductor material may abut the die. The additional semiconductor material may consist of one or more pieces of semiconductor material. Preferably the size and location of the additional piece or pieces of semiconductor material is chosen so that the region of interest is located nearer the center of the combined semiconductor material of the die and additional semiconductor material. Thus, the size of the additional semiconductor material may be chosen so that it extends outward from the region of interest by a distance that is at least half the width of the die and may be equal to the width of the die. Where the region of interest is near a corner of the die, the additional semiconductor material may for instance comprise a half die and a quarter die from the same wafer, that are placed around said corner.
Furthermore, the wheel 200 typically includes an upper layer made of a flexible compound, e.g., rubber with an abrasive upper surface for lapping or grinding away the die. The effect is shown in exaggerated fashion in
Where the region of interest is located at or near the edge of the die, especially the outer edge, the excessive lapping makes it difficult to control the removal of semiconductor material in these regions for purposes of analysis. Excessive lapping therefore often results in destruction of the very portion of the die that is of interest.
The present invention therefore proposes adding additional pieces of semiconductor material adjacent the edge of the die in situations where the region of interest, i.e., the defect region has previously been pinpointed in the x-y plane as being located at or near the edge of the die. This is illustrated in
In the embodiment shown, the piece 702 comprised half a rejected die from the same wafer, while piece 704 comprised a quarter of a rejected dir from the same wafer. Making use of simple shapes as those shown for pieces 702 and 704 make it easy to either cut or break an existing rejected die while providing dimensions that would cause the defect 720 to be located nearer the middle of the newly defined semiconductor structure as defined by the die 700 and pieces 702, 704. It will be appreciated that if the defect to be analyzed is located not at a corner as in
It will also be noted that in the embodiment of
While the embodiment discussed above secured the additional semiconductor pieces to the die 700 under test, another embodiment involved simply attaching the die and additional semiconductor pieces to the sample holder of the lapping system by means of wax. In fact it was found that excessive lapping along the edges of the die due to the flexing of the lapping wheel surface could be avoided even if the die and additional semiconductor pieces were not actually abutting each other. The additional semiconductor pieces nevertheless redistributed the force exerted by the wheel on the die, thereby avoiding the excessive bowing effect of the wheel surface at the edge of the die.
While specific embodiments were discussed above, it will be appreciated that the invention will apply equally to other configurations of the added semiconductor material and in conjunction with other lapping devices that cause uneven lapping of dies.
|Cited Patent||Filing date||Publication date||Applicant||Title|
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|US5664987 *||Sep 4, 1996||Sep 9, 1997||National Semiconductor Corporation||Methods and apparatus for control of polishing pad conditioning for wafer planarization|
|US5972798 *||May 29, 1998||Oct 26, 1999||Taiwan Semiconductor Manufacturing Company, Ltd.||Prevention of die loss to chemical mechanical polishing|
|US6110806 *||Mar 26, 1999||Aug 29, 2000||International Business Machines Corporation||Process for precision alignment of chips for mounting on a substrate|
|US6248001 *||Aug 6, 1999||Jun 19, 2001||Micron Technology, Inc.||Semiconductor die de-processing using a die holder and chemical mechanical polishing|
|US6461941 *||May 31, 2001||Oct 8, 2002||Hyundai Electronics Industries Co., Ltd.||Method of forming capacitor on cell region including forming dummy pattern around alignment key|
|US6661102 *||Jan 18, 2002||Dec 9, 2003||Advance Micro Devices, Inc.||Semiconductor packaging apparatus for controlling die attach fillet height to reduce die shear stress|
|US6683379 *||Jan 11, 2002||Jan 27, 2004||Matsushita Electric Industrial Co., Ltd.||Semiconductor device with reinforcing resin layer|
|WO1996039275A1 *||Apr 19, 1996||Dec 12, 1996||Minnesota Mining & Mfg||Coater die grinding and finishing method|
|U.S. Classification||438/4, 257/E21.001, 438/459, 438/455, 438/977|
|Cooperative Classification||Y10S438/977, B24B37/042|
|Sep 23, 2004||AS||Assignment|
Owner name: NATIONAL SEMICONDUCTOR CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GAO, GENGYING;REEL/FRAME:015838/0832
Effective date: 20040921
|Feb 13, 2012||FPAY||Fee payment|
Year of fee payment: 4