by James A. Vincent, G1PVZ (email G1PVZ) Copyright James A. Vincent, 1993
Voice link over spread spectrum radio was originally published in the September and October 1993 issues of ELECTRONICS WORLD + WIRELESS WORLD. Thanks to James Vincent and the editor of EW+WW for giving permission to reprint the article on the World-Wide Web and the TAPR Spread Spectrum pages.
The article contains two parts:
Until quite recently spread spectrum techniques were almost exclusively
in the military domain. Their use in GPS and the latest cellular phones
will be followed by many other civil applications. This article, the first
of [two] parts, examines the technology by describing an experimental direct
sequence voice transmission system as a worked example.
Spread spectrum radio is now used extensively for both military and
civilian communications. James Vincent describes the circuitry for a fully
functional experimental voice link.
1:Basic PrinciplesMost Communication Engineers are used to minimising transmission bandwidths. The trend has been to use narrower bandwidths, as with the transition from double sideband to single sideband modulation. It is quite obvious that narrower bandwidths permit more communication channels to be packed into a defined frequency band.
However the rationale of using the very wide bandwidths required by Spread Spectrum systems needs explanation. Claude Shannon produced a ground breaking paper on the mathematical theory of communication in 1949. Shannon's resulting theorem can be expressed as:
where C = data rate in bits per second, W = bandwidth (Hz), S = average signal power (W), N = mean white gaussian noise power (W). It can be seen from the equation that the only options available to increase a channel's capacity are to increase either the bandwidth (W) or the signal to noise ratio (S/N).
An increase in the signal to noise ratio requires an increase in transmitter power as the noise within the channel is beyond our control! Thus we can either trade power or bandwidth to achieve a specified channel data rate. Because of the logarithmic relationship, increasing the power output is often unrealistic. However if frequency allocation constraints permit, the bandwidth can be increased. An appreciable increase in data capacity or signal to noise ratio (for a fixed data rate) can then be achieved.
Spread spectrum systems utilise very wide bandwidths and low signal to noise ratios. From Shannon's theorem:
By logarithmic expansion
In a spread spectrum system the signal to noise ratio (S/N) is typically small, much less than 0.1
From the derived relationship it can be clearly seen that a desired signal to noise ratio for a fixed data rate C, can be achieved by increasing the transmission bandwidth.
For example, assume a data rate of 32 Kbits-1 and a signal to noise ratio of 0.001 (-30 dB)
So for a data rate of 32 Kbits-1, operation at the very low S/N ratio of -30db is achievable by spreading the signal over a bandwidth of 22 MHz. By using a very much wider bandwidth than that of the original data it is possible to maintain data capacity without increasing the transmitter output power. It is an extreme example of a power-bandwidth trade off.
Two criteria (see Dixon) for a spread spectrum system are:
- that the transmitted bandwidth is much greater than the bandwidth or rate of the information being sent; and
- that some function other than the information being sent determines the resulting radio frequency bandwidth.
However should the receiver not be synchronised to the transmitter or a conventional receiver be used, nothing will be heard unless the transmitter hops onto the receiver's tuned frequency. As a frequency hopping transmitter typically hops over tens to thousands of frequencies per second (the hop rate), the time it stays on a particular channel (the dwell time) is very short and as a result the signal would appear as a burst of interference.
The other major spread spectrum technique is known as direct sequence or pseudo-noise. In this technique a pseudo-random code directly phase shift keys the carrier increasing its bandwidth (see Figure 2). In a typical direct sequence system a double-balanced mixer (DBM) is driven by the PN code to switch a carrier's phase between 0 degrees and 180 degrees. This is known as biphase shift keying (BPSK) or sometimes phase reversal keying (PRK). Unlike a frequency hopping transmitter where the pseudo-random sequence commands a synthesiser to change frequency, the direct sequence signal is directly generated by the pseudo-random sequence.
The receiver despreads this wideband signal by using an identical synchronised pseudo-random code to that in the transmitter. As with the frequency hopper, the receiver must use a circuit to adjust its clock rate so that the receiver's pseudo-random code is at the same point in the code as the transmitter. A tracking circuit is necessary to maintain synchronism once it has been attained.
Obviously some modulation formats are less suitable than others. Amplitude modulation and its derivatives are the least desirable as their use will destroy the signal's uniform power spectral density. This constant carrier envelope is very desirable for spread spectrum systems designed for covert usage.
Frequency modulation (frequency shift keying for data) is often used in frequency hopping systems, but is infrequently used in direct sequence systems. This is because when a direct sequence signal passes through a squaring or frequency doubling circuit, a carrier at twice the signal's centre frequency is produced. This twice frequency narrowband carrier will contain any modulation impressed on the direct sequence signal. Thus with analogue modulation it is possible for the signal to be demodulated without any prior knowledge of the pseudo-random spreading code.
One of the commonest modulation techniques used in conjunction with direct sequence is known as code inversion or modification. The digitised voice or digital data is exclusive ORed with the PN spreading code. This will invert the PN code sequence if the data is a "1" or pass the PN code unmodified if it is a "0". Provided that the data stream is synchronised with the PN code, the correlation properties of the code are unaffected.
Assuming synchronisation at the receiver, the unmodified code despreads the direct sequence signal. This produces a narrowband signal which is still biphase shift modulated, but this time with the data or digitised speech. This signal can then be demodulated by a conventional biphase shift demodulator such as a squaring or Costas loop demodulator.
This code modification modulation is simple to implement in the transmitter and relatively easy to demodulate in the receiver. It also has the advantage of providing message privacy which the analogue modulated direct sequence signal does not have. It should be noted that it is possible to directly demodulate uncorrelated spectral components of an analogue modulated direct sequence signal should the demodulating receiver be very close to the transmitter. In addition the code modification technique preserves the constant power envelope of the direct sequence signal.
One disadvantage of code modification is that voice or other analogue signals require digitisation. As in any system design, the selection of the digitisation technique is very important. The technique selected must use the lowest possible data rate as data rate is inversely proportional to the process gain of the system. The technique selected for the system described uses a enhanced form of delta modulation to digitally encode the voice into a serial data stream.
At the receiver, the transmitted pulses are integrated and passed through a low-pass filter to remove unwanted high frequency components. The output consists of the original analogue signal together with some additional noise somewhat similar to quantisation noise.
Continuously Variable Slope Delta Modulation (CVSD) takes advantage of the fact that voice signals do not change abruptly and that there is only a small change from one sample to the next. A reasonably good reproduction can be obtained by transmitting in a given interval whether the output signal should increase or decrease. A linear delta modulated system has the undesirable feature that there is one input level which maximises the signal to noise ratio. In CVSD this is overcome by compressing the large amplitude in the signals relative to the smaller ones prior to encoding using a compressor circuit. In this way the input level to the encoder can be maintained close to the value which gives the maximum signal to noise ratio.
The receiver decodes the delta modulated binary stream and passes the analogue signal through an expander to counteract the effects of the transmitter compressor. Companding is optimised for the human voice. CVSD is considerably more effective than standard delta modulation and also exhibits less serious sound degradation in the presence of digital noise interference than PCM.
The system is described in functional blocks. First, the transmitter direct sequence modulator. The exciter's clock frequencies are provided by a master 4 MHz crystal oscillator and a divider. Power-up reset (with manual override) is configured around a Schmidt-trigger.
A shift register and exclusive OR gates are configured as a 4 MHz 127 chip (code bit) long maximal pseudo-random code generator (see section pseudo-random codes and generation).
Microphone audio is amplified by the VOGAD (Voice Operated Gain Adjusting Device) to the optimum level for the input of the delta modulator. The delta modulator converts the audio into a 32 Kbits-1 serial data stream (see column sending data with spread spectrum). This serial binary data stream must be coded into a format which is polarity insensitive because the receiver demodulator cannot recover the de-spread data's absolute phase. Only data transitions are recovered at the receiver, hence there is no way of determining whether the output data stream is inverted or not.
The digitised audio is converted from a non return to zero (NRZ) format into a polarity insensitive diphase (biphase-mark) data stream. This sub-circuit produces a diphase signal (Figure 4), where a logic 1 has start, mid-bit and end transitions and a logic 0 has only start and finish transitions.
In addition to providing phase insensitive data transmission the format also makes clock recovery at the receiver relatively easy, as unlike NRZ even a continuous stream of diphase encoded 0's results in many start and finish data cell transitions. The diphase encoded delta modulated digital voice signal is ex-ORed with the pseudo-random code producing a code modified PN spreading code.
The data modified PN code from the output of the exclusive-OR gate provides a balanced drive (plus or minus 24 mA as an AC logic family device has equal sink and source currents) via a coupling capacitor and 50 ohm matching pad, to a double balanced mixer (DBM) configured as a biphase shift keyer.
The PN code output alternately sinks and sources current, causing the diodes in the DBM to alternately switch on and off producing 180 degree phase reversals in the 435 MHz carrier signal (see Figure 5). The output spectrum consists of a series of symmetrical sidebands which have a Sinc2x distribution due to the many frequency components of the pseudo-random code.
As the spreading code has a pseudo-random character, the occurrence of a particular frequency is pseudo-random in time and the direct sequence output appears as noise on a spectrum analyser. The spread spectrum signal has a main lobe bandwidth of 8 MHz (twice the PN code clock rate for BPSK). This is amplified by a MAR8 MMIC (monolithic microwave integrated circuit) and further amplified to around 100 mW by a Motorola CA4812 Class A Amplifier module. Helical band pass filtering is used to ensure that the output signal is within the permitted bandwidth before free-space transmission.
BWRF = 3dB bandwidth of the transmitted spread spectrum signal (Hz). Rinfo = data rate of the information transmitted (bits per second).
For a direct sequence signal, BWRF is assumed to be equal to the 3 dB bandwidth of the spectrum (which is 0.88 times the pseudo-random code clock rate for a biphase shift keyed direct sequence system). For a frequency hopping system BWRF is equal to m times the channel bandwidth where m is the number of frequency channels available.
Jamming Margin. Although the process gain is directly related to the interference rejection properties a more indicative measure of how a spread spectrum system will perform in the face of interference is the jamming margin (Mj). The process gain of a system will always be greater than its jamming margin.
Lsystem = system implementation losses (dB); Gp = process gain (dB); (S/N)out = signal to noise ratio at the information output. (dB)
A spread spectrum system with a 30 dB process gain, a minimum required output signal to noise of 10 dB and system implementation loss of 3 dB would have a jamming margin of 30-(10+3) dB which is 17 dB. The spread spectrum system in this example could not be expected to work in an environment with interference more than 17 dB above the desired signal.
Power Spectral Density. By nature of the spreading process, the output power of the spread spectrum transmitter is spread over typically many megahertz of bandwidth. The spectral density is the number of Watts of radio frequency power present per Hertz of bandwidth. Thus for a direct sequence transmitter of 1W output and a spread bandwidth of 8MHz the power spectral density is:
For a conventional AM transmitter, power spectral density is around
some 31dB greater.
The advantage to the military user is that the signal strength apparent to a conventional narrowband receiver is very, very low and would probably not be recognised as a communications signal, hence the expression "Low Probability of Intercept" and "Low Probability of Recognition".
Auto-correlation: This is a measure of similarity between a signal and a time shifted replica of itself. Auto-correlation is a special case of cross-correlation. The auto-correlation function is the fundamental theoretical basis of spread spectrum communications.
Biphase Shift Keying (BPSK): A phase shift keying technique where the carrier phase changes between 0 degrees and 180 degrees (0 and pi radians) under the control of a binary code. BPSK is frequently used to generate direct sequence spread spectrum signals, where the binary code is a pseudo-random sequence.
Chip: A single element of the spreading code. This may be one or more of the PN code bits, depending on the modulation technique used. For BPSK one chip represents one code bit, whereas for quadrature phase shift keying (QPSK) one chip represents two code bits.
This is because there are four states for QPSK (0, 90, 180 and 270 degrees) and only two states for BPSK (0 and 90 degrees). Obviously two binary bits are required to represent four states and only one bit for two states.
Code: The term code usually refers to the pseudo-random code used to control the modulation technique used to spread the carrier.
Code Division Multiple Access (CDMA): A multiplexing technique where each user is given a different pseudo-random spreading code. To communicate with a particular user, the sender must select the code assigned to that user.
If the CDMA codes are carefully selected to ensure good correlation properties, then unwanted CDMA transmissions will not be correlated and hence rejected as wideband interference (up to the limit of the jamming margin Mj of the system). This technique can permit many users to operate simultaneously on the same frequency.
Correlator: A device to measure the similarity of two signals. Sometimes referred to as a de-spreader in direct sequence systems.
Costas Loop: A compound phase locked loop sometimes called an I-Q (In-phase/Quadrature phase) loop. It is used for demodulating double-sideband suppressed carriers (DSBSC) which is the modulation format of a biphase phase-shift keyed signal.
Cross-correlation: This is a measure of the similarity of two signals.
Delay Locked Loop: A tracking circuit which ensures the direct sequence receiver PN clock tracks (follows) any variation in the transmitter's PN clock rate once synchronisation has been achieved. (See column The Delay Locked Loop).
Delta Modulation: A analogue to digital conversion technique (see column Sending Data with Spread Spectrum).
Diphase (biphase-mark): A polarity-insensitive waveform, where a transition occurs at the beginning of every data period. A logic 1 is represented by a transition one half period later. There is no second transition for a logic 0.
Direct Sequence (ds): A spread spectrum modulation technique where a pseudo-random code directly phase modulates a carrier, increasing the bandwidth of the transmission. The resulting signal has a noise-like spectrum. The signal is despread by correlating with a pseudo-random code identical to and in synchronism with the code used to spread the carrier at the transmitter.
Frequency Hopping (fh): A spread spectrum modulation technique where the transmitter frequency hops from channel to channel in a predetermined but pseudo-random manner. The signal is de-hopped at the receiver by a frequency synthesiser controlled by a pseudo-random sequence generator synchronised to the transmitter's pseudo-random generator.
Jamming Margin (Mj): A measure of a spread spectrum system's resistance to jamming or un-intentional interference, (see column Spread Spectrum Terminology).
Linear Codes: Pseudo-random codes generated using only modulo-2 addition or subtraction,(see column Pseudo-random Codes and their Generation).
Maximal Code: A maximal code is the longest that can be generated with a feedback type pseudo-random generator (see column Pseudo-random Codes and Generation).
Process Gain (Gp): The measure of the gain or signal-to-noise improvement exhibited by a spread spectrum system by nature of the spreading and de-spreading process.
Pseudo-noise: Code sequences which have noise-like properties. The term pseudonoise (pn) is often used for direct sequence systems which use such codes to spread the carrier.
Sinc x: Sinc x is the mathematical term for the following expression:
A BPSK spread spectrum has a Sinc2x power spectrum.
Squaring Loop: A BPSK (or DSBSC) demodulator which regenerates the suppressed carrier through a frequency squaring (or doubling) process. This doubling process produces a twice frequency unmodulated carrier, which when divided by two can be multiplied with the input BPSK signal to recover the data.
2: Detailed CircuitryPseudo-random codes can be categorised as being linear or non-linear codes. Linear codes are generated using linear operations (which for binary pseudo-random codes is solely modulo-2 addition or subtraction). This essentially means only ex-OR gates are used in the shift register feedback path. A pseudo-random generator which does not use such techniques is termed non-linear.
The most commonly used group of pseudo-random sequences used in spread spectrum are the maximal linear code sequences (sometimes called M-sequences or PN -- pseudo-noise -- codes). Maximal codes are the longest codes that a shift register of specified length can produces and have mathematical properties well suited to spread spectrum communications.
A maximal shift register pseudo-random generator consists of a shift register with selected outputs being exclusive-ORed and fed back into the shift register input. The circuit goes through a number of states (determined by the bits in the shift register at each clock pulse) before it repeats itself after a set number of clock pulses. The maximum number of states for a shift register of length m is 2m, ie for a 7-stage shift register 27 = 128 states. However the all-zero state is not allowable as the pseudo-random generator would lock-up as ex-ORing two logic 0 results in yet another logic 0 at the input. Therefore a maximal length pseudo-random code generator can produce a pseudo-random sequence 2m-1 bits long before repeating itself.
To obtain a maximal sequence, the correct shift register outputs (tap points) must be found. These could be found be experimentation but this would be very time consuming! However tables of feedback connections are available.
A 7-stage (ie seven flip-flop) shift register can produce a maximal code of length 27-1 = 127 bits (known as chips in spread spectrum terminology) long. The feedback tap points may be taken from the following stages:
[7,1] [7,3] [7,3,2,1] [7,4,3,2] [7,6,4,2] [7,6,3,1] [7,6,5,2] [7,6,5,4,2,1] and [7,5,4,3,2,1]As the simplest circuit implementation is often desired, the first option of tapping the seventh and first stages is selected.
To avoid the all zero-lock up problem, inverting stages are inserted before the shift register input and at the output of the shift register. When the shift register is switched on, a reset pulse is initiated. This pulse initiates all shift register outputs to logic 0. This would normally lock up the pseudo-random sequence generator. However the input inverter injects a logic 1 so that the maximal sequence can commence. The output inverter ensures that maximal code output is inverted negating the effect of the anti-lock-up inverter at the input. The maximal code is also available at the output (A) of the modulo-2 adder, but the second inverter output is normally used to permit direct drive of the DBM in a direct sequence system.
The 435 MHz direct sequence (ds) signal is first amplified by a low noise amplifier2 followed by a helical filter and further amplification by a low noise amplifier block (MAN1-LN) and a MAR8. The ds signal is mixed with a 7 dBm 365 MHz local oscillator in a down-converter. The ds signal now centred on an intermediate frequency of 70 MHz is amplified (MAR8) and bandpass filtered (PIF-70), before being resistively split into three identical signal paths. In each signal path (late, on time or early) the 70 MHz signal is amplified by a further MAR6 amplifier. A DBM configured as a biphase shift keyer is driven by an early, on time or late pn code. The DBM is buffered by 50 ohm pads and driven by an AC logic buffer as with the DBM used as a BPSK modulator in the transmitter.
Assuming synchronism the despread output is injected into a NE605 low power FM IF integrated circuit. The second local oscillator at 64 MHz in conjunction with the on-chip mixer downconverts the despread signal (which contains the data in a BPSK format) to 6 MHz. The NE605 further amplifies the 6 MHz signal and provides filtering using 6 MHz ceramic filters originally designed for television sound strips.
A RSSI (received signal strength indicator) is available from each NE605 with a 90 dB range logarithmic output. The RSSI outputs from the early and late channels go to the delay locked loop circuit. The despread data output from the on time (punctual) channel is further amplified by a MAR8 amplifier before being frequency doubled in a Mini Circuits RK3 doubler. As previously discussed the despread data signal has a biphase shift keyed (BPSK) format. The BPSK frequency spectra is similar to that of a double sideband suppressed carrier and as for DSBSC, carrier recovery is required to demodulate the signal. It can be shown mathematically3 that by squaring or doubling a BPSK signal a twice frequency carrier is obtained. After passing the doubled signal through a 12 MHz crystal used as an exceptionally narrow bandpass filter, the signal is applied to a synchronous oscillator. This versatile circuit (see section The Synchronous Oscillator) free runs at 6 MHz and on application of the 12 MHz signal synchronously locks to half of the input frequency, effectively regenerating the 6 MHz carrier reference. This locked 6 MHz output is buffered and amplified to produce a logic level 0, +5v output, which together with the signal output from the on-time (punctual) NE605 IC is injected into a DBM configured as a phase detector. The voltage output of the phase detector is amplified, level shifted and using a voltage comparator converted into 0, +5v logic levels.
The output from this squaring loop BPSK demodulator does not recover the original data polarity as the original phase of the signal is lost in the doubling process. This is why the data was diphase encoded at the transmitter so that the correct data polarity could be recovered at the receiver.
An edge detector configured from an exclusive-OR gates produces a negative pulse for both positive and negative edges of the comparator's diphase data stream output. The edge detector output triggers monostable A, one half of a dual monostable. (Note: all monostables are non-retriggable). Monostable A is set to produce a positive output pulse with a duration of 75% of the diphase bit cell period. The Q output of monostable A triggers monostable B which produces a positive output pulse of duration 25% of the diphase bit cell period.
In turn the negative going edge of monostable B output triggers monostable C which produces a positive pulse with a duration of 50% of the diphase bit cell period. D-type flip-flop D1 is clocked by the /Q output of monostable C and flip-flop D2 by the Q output.
The positive edge of the Q and /Q outputs of Monostable C occur before and after any mid-bit transition. Thus when D1 and D2 are clocked, their outputs will be different if the diphase encoded bit represents a one, or the same if the diphase encoded bit represent a zero. If D1 and D2 outputs are exclusive OR-ed then the instantaneous NRZ data is obtained. The clock is recovered at the Q output of Monostable A. It can be seen that missing or corrupted diphase data could cause monostable A to trigger on a mid-bit transition rather than a 'start' transition. This false synchronisation will be corrected on the next diphase encoded zero as monostable A will not be triggered.
The recovered clock and NRZ data is delivered to the delta modulator integrated circuit where it is converted back into audio and amplified to a loudspeaker.
The delay lock loop and code generation circuitry permits code correlation, synchronisation and tracking. The difference amplifier has its inverting and non-inverting inputs respectively connected to the early and late channel RSSI outputs. The difference amplifier is followed by a summing amplifier used to adjust the quiescent frequency of the voltage controlled crystal oscillator and a low pass filter. The output of the inverter drives the control input of the voltage controlled oscillator. The VCXO consists of a high stability AT cut crystal in a discrete transistor based oscillator with varicap frequency control. The oscillator's low voltage output is amplified by approximately 10,000 by the linear biased HC logic gate. This hard limits the buffer's output to standard logic levels. The VCXO provides a highly stable, repeatable output which has a 2 kHz tuning range centred on 8 MHz for a tuning voltage of 0 to 6V.
The VCXO output is divided by two to produce a 4 MHz clock. This clock signal drives the 127 chip maximal PN generator. The output of this PN generator is re-clocked through a shift register by the original 8 MHz clock. By extracting the three outputs from neighbouring outputs three identical PN codes are available (early, on-time and late) but with a half clock cycle difference between them. Thus the early code is one clock cycle (or "chip" in spread spectrum terminology) ahead of the late code. Each PN code generator output drives the relevant correlator (de-spreader). See section Delay Locked Loop.
In operation the VCXO is offset to a slightly higher frequency than the crystal clock in the transmitter, effectively producing a sliding correlator. Assuming that the receiver is in range and unsynchronised, the receiver code will slide past the transmitter code. At one point in time the two codes will match. This will result in correlation and the direct sequence signal will be despread. The early channel will be despread before the late channel and the early RSSI value will be considerably higher than the late uncorrelated channel. This difference signal after filtering steers the VCXO output towards the frequency of the transmitter clock. When the receiver and transmitter clocks and PN codes are synchronised the RSSI outputs from the early and late channels will be identical and the difference amplifier output will be zero. Should the receiver clock be retarded greater energy will in the late channel than the early channel, and the VCXO will be driven by the difference amplifier to increase its frequency. If the receiver clock is advanced greater energy will be in the early channel than the late channel and the VCXO will be driven by the difference amplifier to decrease its frequency. Thus the delay locked loop will maintain synchronism once the sliding correlator has caused the receiver to lock. The frequency offset is selected such that it will cause rapid synchronisation but remain within the capture range of the loop.
The direct sequence transmitter and receiver were constructed on a combination of Veroboard and double-sided printed circuit boards. The radio-frequency circuits were built on the double-sided pcbs, with the usual RF design techniques employed. The photograph of the completed transmitter-exciter and receiver shows the combination of construction techniques used. (See August EW+WW).
The system is designed around easily obtainable components and all inductors and filters are selected from either the Toko or Mini-Circuits range to avoid the difficulties of winding coils.
The set-up of the receiver requires a functioning exciter as a source of a direct sequence signal, hence the exciter is adjusted first. This involves setting the master 4 MHz crystal oscillator with the aid of a frequency counter.
Now the receiver can be directly connected (with a suitable attenuator in-line to prevent overload) to the exciter output. Initially the 64 MHz second local oscillator should be adjusted on frequency. The VCXO's frequency is set using the centre frequency adjust potentiometer, to be slightly higher or lower than twice the measured frequency of the transmitter's master clock.
The resonant circuit of the synchronous oscillator (SO) has to be adjusted until it free-runs at 6 MHz. It is important to ensure that the SO oscillates at 6 MHz (ie not a harmonic) and the input level potentiometer is set to the minimum input level which permits reliable operation.
The gain and comparator reference point potentiometers should be adjusted such that the phase detector recovers the diphase data stream with HC logic compatible levels.
The VCXO frequency is slowly adjusted, until the sliding correlator and delay locked loop lock to and track the transmitter. If a spectrum analyser is available, a narrowband despread BPSK data signal will can be detected at the input to the PIF-70 filter. A dual channel oscilloscope can be used to monitor and compare the transmitter and receiver (punctual) PN codes. If the receiver has synchronised then the two PN codes will line up and the receiver code will be seen to track the transmitter's code. If all is correctly adjusted then the synchronous oscillator will regenerate the 6 MHz carrier with the data recovery circuit and delta-modulator i.c. recovering the audio. Various waveforms are shown on the circuit diagram to aid trouble shooting.
After this initial procedure the power and pre-amplifiers can be added for free-space checks (provided radio regulations permit). Some minor adjustments particularly of the VCXO frequency may be required to ensure reliable acquisition and locking. If the VCXO frequency offset is too great then the receiver will initially acquire the signal , but will be unable to track it. A degree of trial and error may be necessary to arrive at a receiver clock offset which provides rapid synchronisation and reliable tracking performance. The prototype took less than two seconds from power-up to synchronise and would remain in lock provided the signal was not lost.
The Radiocommmunications Agency (the UK radio regulatory authority) granted special authority to the author to experiment with spread spectrum techniques on the 70 cm band under his amateur radio service licence.
At present the UK amateur radio licence does not permit the use of spread spectrum modulation. It is hoped that in the future the standard UK licence will permit spread spectrum modes of operation as is allowed in the USA by the Federal Communications Commission.
The design and circuitry in this article is held in copyright by James A. Vincent, 1993.
TUF1, RK3 and MAR series devices are manufactured by Mini-Circuits (from Cirkit in the UK and Dale Electronics, Camberley) FX609J from Consumer Microcircuits, Witham, Essex, England. Crystals are available from IQD Ltd, Crewkerne, Somerset, England. RFFM2 DBM comes from Walmore Electronics, London, England.
1. Convert NRZ to Biphase. John T. McGaughey. Electronic Design April 12 1990
2. High Performance 70cm Pre-Amp. Timothy Edwards. Radio and Electronics World March 1982
3. Appendix 4 - Multiplication of Direct Sequence Signals. Spread Spectrum Systems Second Edition Robert C. Dixon. Wiley Interscience.
4. Communication in the Presence of Noise. C.E. Shannon. Proc.IRE, vol.37, No1,(pp10-21) Jan 1949.
5. The Synchronous Oscillator: A Synchronisation and Tracking Network. Vasil Uzunoglu & Marvin H. White. IEEE Journal of Solid-State Circuits. Vol. SC-20, No.6 December 1985.
6. Synchronous and the Coherent Phase-Locked Synchronous Oscillators: New Techniques in Synchronisation and Tracking. Vasil Uzunoglu & Marvin H. White. IEEE Transactions on Circuits and Systems. Vol.36, No7, July 1989.
7. A Practical Direct-Sequence Spread Spectrum UHF Link. Andre Kesteloot, N4ICK. QST magazine. [ Re-printed in the ARRL Spread Spectrum Handbook (pp 8-47 - 8-54) The American Radio Relay League. ].
8. United States Patents: 4 335 404, 4 274 067 and 4 356 456.
Spread Spectrum Systems Second Edition. Robert C Dixon, Wiley Interscience, ISBN 0-471-88309-3.
The ARRL Spread Spectrum Sourcebook. Editors Andre‚ Kesteloot N4ICK and Charles Hutchinson K8CH. The American Radio Relay League. ISBN 0-87259-317-7.
Spread Spectrum Communications Volume 1, 2 and 3. Marvin K Simon, Jim K Omura, Robert A Scholtz and Barry K Levitt. Computer Science Press. ISBN 0-88175-017-7 (Set).
Coherent Spread Spectrum Systems Jack K Holmes. Wiley Interscience. ISBN 0-471-03301-4.
Digital Communication by Satellite. James J. Spilker Jr. Prentice-Hall. ISBN 0-13-214155-8.
Auto-Correlation and Cross-CorrelationThe main basis of spread spectrum communications is the correlation function, a measure of the similarity between functions. For the autocorrelation function:
A time dependent function (such as Sinwt) is compared with an identical replica time shifted by a magnitude and summed (integrated) for all values of t. This function has a maximum at = 0 which shows that (obviously) a function is most similar to itself when it has not been time-shifted. For periodic functions, further maxima appear for a multiple of this period.
The response of the correlation function at other values than = 0 determines how well the original function f(t) can be found again by variation of the time shift tau. It is also possible to compare various functions f(t) and g(t) using the cross-correlation function:
This cross-correlation function is a measure of the degree of agreement between functions. Since the functions to be compared are different may never achieve the maximum value of . It is an indication that the functions are different when a certain threshold (-1 in the case of a binary) is not exceeded.
In the correlation of binary code sequences, the result for cross-correlation will be +1 if the functional values coincide and -1 if they do not. The integration then forms a summing of all bits of the code. The correlation value for a certain phase-shift can therefore be simply calculated by placing the bits over another and comparing them bit by bit. The correlation rate is the sum of agreements and disagreements.
For example, the maximal code sequence 1110010 is compared with itself in the seven possible phase-shifts.
shift sequence agreements disgreements agreements minus disagreements 0 1110010 - - - 1 0111001 3 4 -1 2 1011100 3 4 -1 3 0101110 3 4 -1 4 0010111 3 4 -1 5 1001011 3 4 -1 6 1100101 3 4 -1 7 1110010 7 0 +7As can be seen the auto-correlation function value is always -1, except for the case of coincidence, where it is a maximum. The greater the length of the code, the higher the auto-correlation amplitude and the greater the code discrimination or cross-correlation response. The auto-correlation function for maximal and non-maximal codes are shown in the drawing below. As shown in the figure, maximal codes have only one auto-correlation maximum, whereas non-maximal codes have side maxima as well.
When non-maximal codes are used it is important to ensure that a sufficiently large spacing exists between the main and side maxima. Despite these disadvantages, non-maximal codes are used to exploit their main advantages of rapid synchronisation and message security.
The Delay Locked LoopAfter initial acquisition, the spread spectrum receiver must maintain synchronisation by tracking changes in the transmitter's PN code clock. The circuitry required is known as a tracking loop, as it tracks the transmitter's code clock frequency variations. Without a tracking loop synchronisation will be lost as the transmitter and receiver PN code clocks will tend to drift apart.
In a delay locked loop two identical pseudo-random or PN despreading codes are delayed with respect to each other. Each PN code is used in separate correlators (early and late) to despread (correlate) the received direct sequence signal. The result of correlation between an incoming direct sequence signal and the receiver PN code is a triangular function two chips (code bits) wide. Assuming synchronisation two correlated signals (each with a triangular correlation waveform) are produced with their correlation peaks separated by the delay between the early and late receiver PN codes. If the two correlation signals are summed in a difference amplifier and filtered, then a composite correlation function is produced. This composite correlation function has a linear region between its maximum and minimum values.
If this composite correlation function is used to control the receiver's code clock frequency (for example by driving a voltage controlled oscillator) then the receiver will track the transmitter's code clock at a point halfway between the maximum and minimum values of the composite correlation function.
An optimum solution is to have a third on-time (punctual) PN sequence correlator channel for signal recovery, with early and late correlators simply providing tracking to keep the on-time channel in the middle of the correlation window. Such an approach provides an optimally correlated (despread) output signal for subsequent data demodulation.
The Synchronous OscillatorThe synchronous oscillator is an elegant but little known circuit which can be used to advantage where a phase-locked loop (PLL) would normally be employed. The SO is a free-running oscillator which oscillates at a frequency determined by its LC tank with no signal applied to its input.
When a signal is applied within the SO's acquisition bandwidth the oscillator synchronises and tracks the input signal. The SO output amplitude is constant when locked to and tracking an input signal. A decrease in the input carrier-to-noise ratio reduces the SO's tracking bandwidth to maintain a constant signal-to-noise ratio at the SO's output. This characteristic allows a SO to acquire and track very noisy signals.
The SO can also act as a frequency multiplier or divider. In the direct sequence receiver, the SO locks to a noisy 12 MHz signal and provides a stable 6 MHz output. This function could be achieved using a PLL but the SO has many advantages5,6,7,8 and, as it is based on only two transistors, is much simpler to implement.
A simplistic explanation of the SO operation is that the upper transistor acts as a Class C oscillator. The upper transistor only conducts for a very brief period of time; when the upper transistor conducts, there is a voltage across the lower transistor biasing it allowing it to conduct. At this time the input signal can then be injected to synchronise the oscillator. During the rest of the oscillator cycle input noise is unable to enter the oscillator as the lower transistor is reverse biased. This arrangement produces coherent amplification which is why the SO can extract signals from very low signal-to-noise inputs.
Copyright James A. Vincent, 1993