|Publication number||US5008723 A|
|Application number||US 07/458,590|
|Publication date||Apr 16, 1991|
|Filing date||Dec 29, 1989|
|Priority date||Dec 29, 1989|
|Publication number||07458590, 458590, US 5008723 A, US 5008723A, US-A-5008723, US5008723 A, US5008723A|
|Inventors||Leonard A. van der Have|
|Original Assignee||Kopin Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (1), Non-Patent Citations (2), Referenced by (33), Classifications (14), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to a method for fabricating microelectronic circuits and in particular metal-oxide-semiconductor (MOS) transistor circuits
An MOS transistor which combines selected features of prior art MOS devices made on bulk silicon is illustrated in the prior art drawings of FIGS. 1-6. It should be noted that no such device probably exists in all the details shown in these drawings. Instead, the surface geometry has been made as close as possible to the preferred embodiments of the present invention, in order to emphasize the similarities and dissimilarities between the "prior art" structure and the present invention.
The transistor is an NMOS type transistor and consists of an N-doped or P-doped silicon single crystal bulk substrate 12, which is part of a wafer 15 (only a portion of which is shown) and upon which a thin P-doped epitaxial film 9 is deposited by well-known techniques such as chemical vapor deposition (CVD).
Islands of device regions are formed in the film 9 by converting the volume around the device regions into thick regions of what is called field oxide 4.
The epitaxial film 9 is commonly grown to be the same type as is the choice for the base wafer 12 and then is converted to P-type (if necessary) for the P-well (or body) as required to operate the NMOS transistor. The transistor is formed by a source region 2 a drain region 1 a polysilicon gate 3, polysilicon oxide spacers 5a thin gate oxide 5, a polysilicon interconnect to the drain 6 a silicide strap 7 for contacting the drain to its polysilicon interconnect 6 and body contact opening 8 to body 9. Thick field oxide regions 4 are shown as the result of a trench and refill process in FIGS. 1-5, while FIG. 6 shows the corresponding cross-section of the conventional NMOS drain (taken along V--V of FIG. 2) if made with a conventional LOCOS process Note that in FIG. 6, the interface wall 100 of the field oxide 40 is tapered. FIG. 3 is cross section III--III illustrating the inclusion of lightly doped region 13 around each of the source and drain regions as this is a common practice with contemporary manufacturing techniques for NMOS transistors.
The thick field oxides 4 enable conductive interconnect pathways (not shown) on the surface of the wafer to pass from one MOS transistor to another on the wafer without causing surface inversion in the wafer's silicon-to-oxide interface. Should this field oxide not be amply thick charge inversion in the silicon surface directly below these interconnect pathways will occur which result in the creation of undesired MOS transistor conducting channels which pass electrical currents between pairs of MOS transistors as a function of the voltage difference applied between the interconnect pathways and the silicon surface regions.
Present-day fabrication methods commonly use a field oxide for separating transistors. The field oxide has a thickness greater than the minimum thickness at which the maximum applied integrated circuit operating voltage difference will not cause charge inversion in the silicon surface below any pathway interconnecting transistors. The basis for this determination are well understood by those skilled in the art, and are dependent on silicon surface doping concentrations and of course, electric field strengths in the surface oxides which are directly proportional to applied voltage and inversely proportional to field oxide thickness.
In addition to field oxides conventional MOS transistors also require a thin oxide gate layer 5 to separate the polysilicon gate electrode 3 from the source region 2 and drain region 1 on either side of the gate 3.
In all cases of known process implementations the field oxides are thicker than the oxides 5 used to form the gates of the MOS transistors themselves Of course it is in these gate oxide regions where a conducting "channel" in the silicon surface is desired This difference in oxide thicknesses thereby enables the circuit designer to precisely determine the physical location of each MOS transistor's conducting channel while permitting the interconnection of a plurality of transistors together over field oxides without creating a network of undesired conducting channels which are function of the final transistor-to-transistor layout. As a result designers are able to utilize design automation systems to fully predict the performance of a proposed design before the chip layout is done which greatly simplifies the design process for circuits requiring more than 100 transistors.
Two advanced methods for forming thick field oxides are employed: local oxidation of silicon or LOCOS or the formation of oxide-filled trench regions between transistors. LOCOS is more commonly employed. Both methods customarily use a heavy concentration of P type dopant (such as boron) to (a) assist in the rapid formation of thick field oxides, and (b) to electrically stabilize the silicon-to-oxide interface for the purpose of reducing leakage currents of any P-N junctions which meet these interfaces. The use of boron in this manner enables the reduction of separation distances between devices, as well as minimizing leakage currents in P-N junctions. These leakage currents become primary considerations for power dissipation minimization for integrated MOS circuits requiring greater than 100,000 transistors.
It is with these very-large-scale-integrated (VLSI) circuits that either LOCOS or trench-type oxidations are employed to prevent undesired conduction between pairs of transistors. Either of these oxidations use a P type dopant in the process which results in the formation of a heavily-doped P type or P+ layer 10 between the thick field oxide and the epitaxial film 9.
In the case of NMOS transistors, this P type layer 10 creates a P-N junction to the heavily-doped N type regions or N+ commonly used for the NMOS source 2 and drain 1 regions. This N to P junction is required to stabilize a VLSI circuit for low leakage currents and is commonly formed in the prior art methods and defines the dominant coupling capacitance of each N+ source and drain region to the NMOS transistor's P type body region.
This invention reduces most of the N to P capacitances occurring in conventional transistor formation while permitting the use of standard MOS process fabrication technologies. In accordance with the invention the MOS transistor is formed on a semiconductor on insulator (SOI) substrate.
For convenience the preferred embodiments herein will illustrate the invention with respect to an SOI structure consisting of an epitaxial or large grain silicon film formed on an insulator consisting of silicon oxide formed on a Si wafer. The silicon film is preferably formed by seeded recrystallization of an amorphous or polysilicon Si film formed on the SiO2 resulting in the formation of a buried SiO2 insulator. (See U.S. 4,670,088 and 4,371,421.) However, it is to be understood that other structures and methods for forming buried insulators are contemplated such as silicon-on-sapphire substrates and semiconductor materials such as GaAs or other III-V material on insulator or Ge on insulator are contemplated.
The method includes the formation of a selective lightly doped drain (LDD) region which extends from the conventional N type drain region to an underlying surface of the buried insulator.
This reduces parasitic NMOS drain to substrate capacitance by approximately one order of magnitude This capacitance reduction improves the electronic speed performance of MOS memories and complex (more than 1000 gates) logic arrays.
This new deep N type drain causes the doping of the silicon regions below and on a minimum of two, or optimally, three of its four sides to become N type where these sides meet these oxides rather than for the N type drain to meet with various P type regions as is the case with conventional NMOS transistors. The N+ drain becomes N type contiguously to the buried insulating oxide, as well as to the sidewall oxides (fabricated by either a LOCOS or a trench filled with oxide) on the two lateral sidewall interfaces which border the N+ drain region. It is optional that this conversion from P to N occur at the end of the N+ drain (a third side opposite the side where the drain faces the active channel).
As a result of the method of the invention, the bottom and two (or three) of the four sidewall P-N junction interfaces of the N-type drain region are replaced with N-type to oxide interfaces. This change results in the elimination of associated P-N junction capacitances and the inclusion of capacitances which are the result of the sidewall and buried oxides to other devices and the substrate wafer region below the buried insulating oxide. These added oxide-related capacitances are between 20 and 200 times lower per unit area than are the capacitances per unit area for the P-N junctions formed in the conventional NMOS transistor drain region. This results in a reduction of the overall capacitance parasitically coupling an NMOS transistor's drain region to other regions in the wafer, producing higher obtainable operating speed, particularly in circuits where a plurality of NMOS drains are electrically connected together; since in conventional NMOS circuits coupling of drains together, such capacitance is additive.
A further important aspect of the present invention is that the new deep lightly doped, N type drain which extends to the buried insulator is selectively formed only in the drain region and no such similar extension is permitted in the source region. This permits the volume under the conventional shallow N type source region to be used as a pathway to electrically connect the transistor body to circuit ground potential, thereby conserving the use of surface real estate, which is so important in integrated circuit design.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of preferred embodiments, as illustrated in the accompanying drawings. These drawings use reference characters which refer to similar parts throughout the various views, except that a prime has been added in FIGS. 7-12 to denote the parts which belong to the present invention and not the prior art. The drawings are not necessarily to scale, while emphasis is placed upon illustrating the principles of the invention.
FIG. 1 is a plan view of a conventional prior art NMOS transistor geometry, as seen from the surface of the wafer.
FIG. 2 is a diagonal view of the NMOS transistor shown in FIG. 1, according to the prior art.
FIG. 3 is a cross-sectional view along lines III--III of FIG. 2.
FIG. 4 is a cross-sectional view along lines IV--IV of FIG. 2.
FIG. 5 is a cross-sectional view along lines V--V of FIG. 2.
FIG. 6 is a cross-sectional view along lines V--V of FIG. 2 as if it were manufactured using a LOCOS process in accordance with the prior art.
FIG. 7 is a plan view of an NMOS transistor according to the preferred embodiment as seen from the surface of the wafer.
FIG. 8 is a partially exploded diagonal view of the same NMOS transistor shown in FIG. 7 according to the preferred embodiment.
FIG. 9 is a cross-sectional view along lines IX--IX of FIG. 8.
FIG. 10 is a cross-sectional view along lines X--X of FIG. 8.
FIG. 11 is a cross-sectional view along lines XI--XI of FIG. 8.
FIG. 12 is a cross-sectional view along lines XI--XI of FIG. 8 as if it were manufactured using a LOCOS process to fabricate the thick field (or "sidewall") oxides. FIGS. 7-11 show these oxides as though they were formed with a trench and refill process, which is the preferred embodiment of this invention.
In the preferred embodiment an NMOS transistor is used for illustration, but the invention is useful for PMOS devices as well.
A portion of an integrated circuit wafer 15' wafer is shown in each of FIGS. 7-12 in which one of a plurality of MOS field-effect transistors is formed. An N+ drain region 1' an N+ source region 2', are formed in a monocrystalline epitaxy layer 9'. A polysilicon gate layer 3' is formed on a thin layer of insulating oxide 5' which is formed on top of epitaxial layer 9'. Oxide 5' separates the source and drain regions of the transistor. The gate oxide also includes the formation of oxide spacers 5a' on the sidewalls of the polysilicon layer 3' which serve to reduce capacitance between the gate 3' and each of the drain 1' and source 2' regions. Thick field oxides 4' are formed by a trench and refill process and form an insulating lateral boundary encompassing the various active regions of the NMOS transistor, i.e., regions 1', 2', 9' and 14'. Note that as an alternate to the trench and refill process, a so-called mesa-isolation structure may be employed in which the trench is not filled in. This has the advantage of a reduction in process steps with the attendant disadvantage of loss of surface planarity. However, if the silicon film is sufficiently thin, then the surface planarity loss can be accommodated.
A buried oxide layer 11' is also included to act as a bottom insulating boundary for the various NMOS transistor regions 9' and 14'. This buried oxide layer 11' resides on top of an Si wafer substrate identified as region 12' in FIGS. 7-12. On top of the buried oxide layer 11' is a mono-crystalline Si epitaxy layer 9', which has been lightly doped to be P-type and which forms the P-well (or body) of the NMOS transistor.
Silicide strap 7' of a refractory metal silicide, such as titanium silicide, is used to provide an electrically conductive contact region to pass current from the N+ drain region 1' directly to a polysilicon strip 6', which may optionally be used for gates or electrical interconnect to other devices elsewhere on integrated circuit wafer 15'. Also, silicide contact 8' (FIG. 8) is optionally used to provide for the simultaneous, low-impedance electrical contact of the N+ source region 2' and the P-well (or body) region 9'. These regions may then later be connected to the circuit's ground potential (Vss, usually by way of a metal film not shown here) as required for predictable, stable gain and highest current delivery of the NMOS transistor depicted in each of FIG. 7-12. Note that use of the silicide strap greatly reduces the amount of area required to make ohmic contact to both source and body regions and also reduces the main remaining cause of undesirable parasitic capacitance which would otherwise be present using conventional prior art contact techniques.
Insulating thick field oxides 4', formed by either a trench and refill process, or a local oxidation process, cause the removal of epitaxy 9' and form insulating oxides 4' aided by the use of a P-type implant or diffusion. This implant or diffusion increases the rate of conversion of epitaxy to oxide in regions 4' and results in the formation of a thin P+ layer 10' in the sidewalls of the remaining epitaxy regions 9'. In addition, a thin layer 10a' of P+ is optionally provided in the bottom of the epitaxy regions 9' . The P+ layer 10a' can be formed by using a high energy P type (boron) implant in the SOI wafer, such that the peak in the concentration of implanted boron is nominally set to be at a depth equal to the plane which forms the interface between epitaxy 9 and insulator 11. The implantation is followed by a high temperature anneal or charge activation, which is such that the P+ 10a' layer is formed in the bottom of epitaxy 9. Thin layer 10 a', together with the P+ sidewall layer 10', creates a beneficial, low-leakage N+ to P+ type of P-N junction at all points where the N+ source and drain regions 1', 2', 13' and 14' meet the oxide regions 4' and 11'. Without the formation of the P+ layers 10' and 10a' then N to P- P-N junctions would be formed at all points where the N+ regions 1', 2', 13' and 14' meet the oxide regions 4' and 11'. This type of N+ to P- junction has been shown to exhibit high leakage current under electrical reverse bias conditions due to charge trapping in the fabrication of sidewall oxide to epitaxy interfaces.
To prevent the high leakage currents, this new structure of the invention provides for N+ to P+ junctions at a plurality of oxide sidewall interfaces while also minimizing the area of these junctions, which are characterized by a relatively high capacitance per unit area. Region 14' is a deep, lightly doped-drain (LDD), which is implanted or diffused as N+ in the area of the transistor's drain only, as shown in FIG. 7-12. This region is fabricated to be deeper in the epitaxy when compared with the N+ drain 1' or source 2' regions, and is also deeper than other optional standard lightly-doped drain regions, such as depicted by region 13' encompassing the source region 2' and, in fact, extends to insulator 11' below. This selective, deep LDD is designed to cause complete conversion of epitaxy region 9' and the P+ layer 10' in the sidewalls and P+ layer 10a' in the bottom of epitaxy 9' to become N+, which then meets the oxides in regions 4' and 11'. Region 16' is a mask feature, which is processed after the polysilicon gate 3' is fabricated, so that the polysilicon gate 3' also acts as a mask boundary to the formation of region 14', as shown in FIGS. 9 and 8. In this manner self-alignment of the LDD region 14' with the channel is achieved.
FIG. 12 illustrates the changes in the sidewalls of oxide regions 4' as a result of using a conventional LOCOS process, as compared to the preferred embodiment illustrated by FIG. 11. Each of these figures show the cross-section of the NMOS transistor's drain region along lines XI--XI of FIG. 8. Oxides formed by a trench and refill process (FIG. 11), for example, result in a straight and perpendicular sidewalls to regions 4', while the LOCOS process (FIG. 12) results in sloping or angled sidewalls 100' to the thick field oxides 4''. The disadvantage in using a LOCOS process over the preferred embodiment is the requirement for a larger area required to accommodate the field oxides. These oxides are fabricated to a depth such that (regions 4' meet with the top of the buried oxide layer 11', as required to form a complete oxide perimeter around completely N type regions 1' and 14' (See FIGS. 11 and 12) along the cross-section XI--XI of FIG. 8.
It is important to note that the body region directly under the gate 3' of the NMOS transistor remains in ohmic contact with the circuit ground potential made at the silicide contact 8'. This is due to the fact that by the organization of this NMOS transistor structure, the P type well (or body) region 9' is contiguous from the channel region under gate 3' to contact 8'. This organization insures that the body region under the gate 3' remains at ground potential at all times. This would not be possible if the source 2' were to be modified by a deep LDD 14', as is the drain 1'. Therefore, it is necessary that the deep LDD 14' be selectively patterned over drain 1' only, so that the body can be connected to ground by a pathway that uses the area under the source in the epitaxy 9'. Therefore no area penalty results from this organization as is commonly the case with conventional NMOS device designs.
It is also important to note that the organization of the NMOS transistor, according to the preferred embodiment in FIGS. 7-12, does not utilize the more conventional method used in bulk Si structure for making a P-well body contact. In the conventional organization the body contact is placed nearby the source and drain regions of the transistor and is separated by body epitaxy at the surface without the use of a thick field oxide. If that conventional method were applied to an SOI structure, the P-well (or body) region would have to be extended outward from the channel (directly below the gate 3' in epitaxy 9') in either of the two available orthogonal directions parallel to the surface of the wafer 15 If this were done, then the P-well epitaxy o would also have to extend some additional area underneath the polysilicon gate 3' when compared with the preferred embodiment of FIG. 8. This conventional organization would cause an increase in transistor input capacitance without a corresponding increase in transconductance, thereby resulting in a reduced bandwidth for the gain of the transistor in most circuit configurations. This organization would also result in the formation of one or two inside corners to the sidewall oxides 4', such that the junction boundary of the N type lightly-doped-drain 14' would become a function of (mask alignment of gate 3' to oxides 4', resulting in widely varying capacitances of the NMOS transistor's drain to the P-well (or body) 9' and P+ sidewall layers 10' as a result of such fabrication.
Collectively, this new NMOS transistor structure causes the following electrical and physical improvements to be realized:
(1) Two of the four lateral sides (i.e, the sides parallel to IX--IX of FIG. 8) of the overall N-drain region 1' and 14' meet the thick field oxides in region 4'. Also, the bottom of the deep LDD region meets the buried oxide region 11'. This results in the formation of very low coupling capacitances through the thick oxides to other neighboring structures and the bottom substrate region 12'. The P+ layer 10' is converted to N+ at the oxides interfaces on a minimum of the two lateral sides (parallel to IX--IX), as well as the bottom, as shown in FIG. 8. If this is done, then it is not necessary that the third lateral side (at the end of the drain region 1') be converted to N+ at the oxide, as the remaining P+ and P type well regions (as shown) act to form a larger capacitance coupling the N type drain regions which is in series with the smaller capacitance already formed and electrically isolated by the thick lateral oxide regions 4' to other devices on integrated circuit 15' (not shown). As a result, this structure effectively reduces drain coupling capacitances, dominated by the N+ to P+ junctions required to prevent high leakage currents, through the reduction of the net area of these junctions when compared to an NMOS transistor of equal surface dimensions produced with a conventional NMOS technology (See FIGS. 1-6 and the discussion of the prior art).
(2) As a result of the use of extended lightly doped drain region in combination with an insulating buried oxide layer 11', the adverse effect of hot-electron induced injection of minority carriers, otherwise collected in the substrate region in conventional NMOS transistor structure, is greatly reduced. This is an important consideration in the fabrication of small short-channel transistors for application in very large scale integrated (VLSI) circuits, in which case, the electric fields in the surface region of the channel (directly below the gate 3') are typically high (˜105 volts/cm) and non-uniform, particularly on the drain side of the channel. This hot-electron induced collection by the substrate in conventional VLSI results in large currents in the substrate which are difficult to control in fabrication or by circuit design. These substrate currents result in higher static power dissipation or latch-up both of which are eliminated by this invention.
(3) The physical organization of the NMOS transistor's N+ source 2', N+ drain 1' and deep LDD 14', and P-well (or body) 9' regions, in accordance with FIGS. 7-12 minimizes the area required to fabricate an NMOS transistor as a result of making contiguous the P-well (body) region 9' below the source 2' to a place where a silicide contact 8' is used to make contact (to circuit ground potential) simultaneously to the N+ source 2' and the P-well 9'. This is an important improvement where the use of sidewall and buried oxides results in limited access to the transistor's channel region (directly below the gate 3'). As a result, a separate dedicated contact for the P-well (or body) region 9' is not required, which would otherwise increase the area required to produce an NMOS transistor as in prior art implementations which use sidewall oxides (such as LOCOS).
An integrated circuit has been developed, by computer simulation, following the principles outlined above for the preferred embodiment. This example is taken from a high-speed static random access memory designed to have 262,144 bits of storage capacity. This design utilizes a six-transistor cell, which includes the use of PMOS transistors in the calculations. It is understood that the invention can be applied to other types of memory designs (one, two and four transistor cell designs), as well as other circuits in which a plurality of NMOS transistor drain regions are electrically connected together. The values discussed below are not critical to the success of the present invention, they being variable for the development of other types of integrated circuits, as well.
Tables 1-6 below record the actual calculated design parameters o an NMOS transistor which has been employed in a computer simulated memory design where 512 of these transistor's drains are electrically connected together by a conductive interconnect "bit line" used to perform electronic read/write operations to/from each memory cell. Listed are the preferred embodiment device parameters which were used in sizing, junction depths, oxide thicknesses, operating conditions, and capacitance-related information defining the drain region of each transistor. Parameters are numbered from 1-51. Some entries are listed as "N/A" for not applicable for each case.
TABLE 1______________________________________NMOS Transistor Lateral Feature Sizes(Preferred Embodiment Example)______________________________________1. NMOS Transistor N+ Drain Length 1.6 μm2. NMOS Transistor N+ Drain Width 1.0 μm3. NMOS Transistor N+ Source Length 1.6 μm4. NMOS Transistor N+ Source Width 1.0 μm5. NMOS Transistor N+ Polysilicon 1.0 μm Gate Length6. N+ Polysilicon Oxide Spacer Width 0.10 μm7. P+ Isolation Sidewall Out- 0.00 μm Diffusion Into N+ Drain8. P+ Isolation Out-Diff along 0.15 μm Bottom/Sides of N+ Drain______________________________________
TABLE 2______________________________________NMOS Transistor Junction Depths(Preferred Embodiment Example)______________________________________9. N+ Source/Drain Diffusion Depth 0.18 μm10. N+ Lightly-Doped Drain Depth 0.10 μm Into Channel11. N+ Lightly-Doped Drain Depth 0.45 μm Below N+ Drain*12. N+ Lightly-Doped Drain Depth 0.22 μm Below N+ Source13. P.Well Region Epitaxy Thickness 0.35 μm Over Buried Oxide14. P+ Isolation Up Diffusion Into 0.05 μm N+From Buried Oxide15. Gate Oxide Thickness 20 μm16. Sidewall Isolation Oxide 1.0 μm Average Width17. Buried Oxide Thickness to 2.0 μm Substrate18. P+ Channel Implant Depth 0.10 μm______________________________________ *Design depth if no buried layer was present.
TABLE 3______________________________________NMOS Transistor Doping Concentrations(Preferred Embodiment Example)______________________________________19. N+ Source/Drain Surface 1.2 × 1020 atoms/cm3 Concentration20. N+ Source/Drain Avg. 8.0 × 1019 atoms/cm3 Sidewall Concentration21. N+ Source/Drain Bottom 5.0 × 1019 atoms/cm3 Concentration22. LDD Sidewall Avg. Concen- 1.0 × 1018 atoms/cm3 tration Source/Drain23. LDD Bottom Concentration, 1.0 × 1018 atoms/cm3 Drain Only24. LDD Bottom Concentration, 1.0 × 1018 atoms/cm3 Source Only25. P+ Isolation Sidewall & 3.0 × 1018 atoms/cm3 UP-Diff Concentration at Oxide Interface26. P+ Channel Implant Surface 3.0 × 1017 atoms/cm3 Concentration27. P-Well Epitaxy Concen- 5.0 × 1018 atoms/cm3 tration______________________________________
TABLE 4______________________________________NMOS Transistor Operating Parameters(Preferred Embodiment Example)______________________________________28. Device Temperature 27.0 ° C.29. Device Drain to Source Bias 1.45 volts Voltage30. Device Gate to Source Bias 5.00 volts Voltage31. Device Threshold Voltage Vt 0.75 volts32. Device Effective Channel Length 0.82 μm33. Device Drain to Source Current: 349 μA______________________________________
TABLE 5______________________________________NMOS Transistor Drain Capacitances/Area(Preferred Embodiment Example)______________________________________34. N+ Drain Bottom to P-Well Body N/A ff/μm235. N+ Drain Sidewall to P+ 0.930 ff/μm2 Channel Implant36. N+ Drain Sidewall to P-Well Body 0.426 ff/μm237. N+ Drain Sidewall to P+ N/A ff/μm2 Isolation Sidewall38. N+ Drain Bottom to P+ N/A ff/μm2 Isolation Sidewall39. N+ Drain Region Bottom & Side 1.656 ff/μm2 Edges to P+ Isolation40. N+ Drain Region to Sidewall 0.035 ff/μm2 Oxide41. N+ Drain Region to Bottom Oxide 0.017 ff/μm242. N+ Drain Region to Polysilicon 1.727 ff/μm2 Gate______________________________________
TABLE 6______________________________________Areas for NMOS Transistor Drain Region(Preferred Embodiment Example)______________________________________43. N+ Drain Bottom to P-Well Body N/A μm244. N+ Drain Sidewall to P+ 0.10 μm2 Channel Implant45. N+ Drain Sidewall to P-Well Body 0.30 μm246. N+ Drain Sidewall to P+ N/A μm2 Isolation Sidewall47. N+ Drain Bottom to P+ N/A μm2 Isolation Sidewall48. N+ Drain Region Bottom & Side 0.17 μm2 Edges to P+ Isolation49. N+ Drain Region to Sidewall 1.47 μm2 Oxide50. N+ Drain Region to Bottom Oxide 1.60 μm251. N+ Drain Region to Polysilicon 0.09 μm2 Gate______________________________________
The NMOS transistor drain capacitance, resulting from taking the sum of the products for the capacitances per unit area listed in Table 5 and their respective drain areas listed in Table 6, above, is 0.7364 femto-farads (ff). This is the overall parasitic capacitance of the drain to the wafer substrate and neighboring devices, and this calculation does not include the capacitances of conductive interconnects to the drain.
Tables 7-12 below summarize a similar prior art NMOS transistor, where changes in device parameters pertinent only to the methodology of this invention are listed. These changes pertain to differences regarding the formation of a deep N+ lightly doped drain region which is selectively patterned around the N+ drain region only. As a result, the benefits of capacitance reduction by having the drain region border on a buried oxide layer in the wafer substrate no longer exist. Many of these changes are summarized below. Note, also, that to make a more valid comparison, the computer calculations assume that the prior art device shown in FIG. 1 has been modified, in accordance with the invention, to utilize a silicide strap terminal 8', as shown in FIG. 7.
TABLE 7______________________________________NMOS Transistor Lateral Feature Sizes(Prior Art Example)______________________________________Parameters 1-6, and 8 are identical in this exampleto those listed in Table 1. The difference in thisexample for the prior art is:7. P+ Isolation Sidewall Out- 0.05 μm Diffusion Into N+ Drain______________________________________
TABLE 8______________________________________NMOS Transistor Junction Depths(Prior Art Example)______________________________________Parameters 9, 10, 12, 15, 16 and 18 areidentical in this example to those listed in Table11. N+ Lightly-Doped Drain Depth 0.22 μm Below N+ Drain13. P-Well Region Epitaxy Thickness 1.00 μm Over Buried Oxide14. P+ Isolation Up Diffusion Into N/A μm N+ From Buried Oxide17. Buried Oxide Thickness to N/A μm Substrate______________________________________
TABLE 9______________________________________NMOS Transistor Doping Concentrations(Prior Art Example)______________________________________Parameters 19-27 are identical in this example tothose listed in Table 3.______________________________________
TABLE 10______________________________________NMOS Transistor Operating Parameters(Prior Art Example)______________________________________Parameters 28-33 are identical in this example tothose listed in Table 4.______________________________________
TABLE 11______________________________________NMOS Transistor Drain Capacitances/Area(Prior Art Example)______________________________________34. N+ Drain Bottom to P-Well Body 0.420 ff/μm235. N+ Drain Sidewall to P+ 0.930 ff/μm2 Channel Implant36. N+ Drain Sidewall to P.Well Body 0.426 ff/μm237. N+ Drain Sidewall to P+ 3.157 ff/μm2 Isolation Sidewall38. N+ Drain Bottom to P+ 3.157 ff/μm2 Isolation Sidewall39. N+ Drain Region Bottom & Side N/A ff/μm2 Edges to P+ Isolation40. N+ Drain Region to Sidewall N/A ff/μm2 Oxide41. N+ Drain Region to Bottom Oxide N/A ff/μm242. N+ Drain Region to Polysilicon 1.727 ff/μm2 Gate______________________________________
TABLE 12______________________________________Areas for NMOS Transistor Drain Region(Prior Art Example)______________________________________43. N+ Drain Bottom to P-Well Body 1.39 μm244. N+ Drain Sidewall to P+ 0.09 μm2 Channel Implant45. N+ Drain Sidewall to P-Well Body 0.45 μm246. N+ Drain Sidewall to P+ 0.73 μm2 Isolation Sidewall47. N+ Drain Bottom to P+ 0.41 μm2 Isolation Sidewall48. N+ Drain Region Bottom & Side N/A μm2 Edges to P+ Isolation49. N+ Drain Region to Sidewall N/A μm2 Oxide50. N+ Drain Region to Bottom Oxide N/A μm251. N+ Drain Region to Polysilicon 0.09 μm2 Gate______________________________________
The total NMOS transistor drain region capacitance, resulting from the sum of the products from Tables 11 and 12, above, is 4.623 femto-farads. This capacitance is 6.27 times higher than that derived from the example for the preferred embodiment.
In summary, the implementation of this method in this example shows that by providing for a deep N+ lightly doped drain (parameters nos. 11 and 13), as well as causing a complete inversion of the P-well to N+ border along the two lateral sides of the N+ drain to the sidewall and buried oxides (so that the drain end is either fully inverted or electrically isolated from the P-well body (controlled by parameters nos. 11 and 13 Specifically, 11 must be designed to be deeper than 13), the elimination of certain capacitance terms by this invention is achieved (parameters nos. 34, 37, 38 and 43, 46, 47). While other capacitance terms (parameters nos. 39, 40, 41 and 48, 49, 50) not found in the prior art are included their values do not outweigh the excluded terms. It is clear that the merits of this invention, which cause the elimination of selected high-value capacitance terms and the inclusion o other lower-value capacitance terms, result in a much lower overall capacitance of the drain region to the substrate, body, and neighboring devices on a common wafer.
The preferred embodiment NMOS transistor has been applied by computer simulation in the manufacture of a 256K-bit static random access memory SRAM integrated circuit using silicon-on-insulator (SOI) wafer substrates. In this case, a six-transistor memory cell design was used, where each of the four NMOS transistors in each memory cell were manufactured in accordance with the preferred embodiment. Also, 512 of these cells were connected together along the direction of the bit access lines Predicted bit-line response time of 1.87 nano-seconds was shown. This compares favorably with the bit-line response times ranging between 5 and 15 nano-seconds which have been reported for other prior art SRAM designs which utilized similar device feature sizes, junction depths and doping concentrations when compared to the preferred embodiment.
Those skilled in the art will recognize, or be able to ascertain, employing no more than routine experimentation, many equivalents to the specific structures, steps, functions and materials described specifically herein, and such equivalents are intended to be encompassed within the scope of the following claims. For example, while the LDD region in the example has a doping level of 1×1018 atoms/cm3, the term "lightly doped" is intended to cover a dopant level sufficient to cause inversion of the P type body in the region where the LDD is desired, but not higher than the shallow N+ surface drain region. Keeping the dopant level of the LDD region below that of the surface drain region permits the electric fields to spread out over a larger region. A preferred range of dopant level for the LLD region is about 1×1017 to 1019 atoms/cm3, while the N+ surface drain region should preferably be less than about 1019 atoms/cm3.
Other methods of active area isolation are contemplated, such as the so-called SIMOX process, which uses oxygen ion bombardment. Silicon on Sapphire (SOS) structures may be used in place of SOI wafers. Wafer bonding and DI wafers are also contemplated.
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|U.S. Classification||257/386, 257/507, 257/E29.147, 257/E29.279, 257/E29.04|
|International Classification||H01L29/786, H01L29/45, H01L29/08|
|Cooperative Classification||H01L29/458, H01L29/0847, H01L29/78624|
|European Classification||H01L29/786B4B2, H01L29/08E2, H01L29/45S2|
|Mar 1, 1990||AS||Assignment|
Owner name: KOPIN CORPORATION, A CORP. OF DE, MASSACHUSETTS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:SILICON DYNAMICS, INC.;REEL/FRAME:005270/0891
Effective date: 19900221
Owner name: SILICON DYNAMICS, INC., 4917 UTAH DRIVE, AMES, IOW
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:VAN DER HAVE, LEONARD A.;REEL/FRAME:005262/0672
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Owner name: SILICON DYNAMICS, INC., AN IA CORP., IOWA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:VAN DER HAVE, LEONARD A.;REEL/FRAME:005262/0672
Effective date: 19900221
|May 5, 1992||CC||Certificate of correction|
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|Oct 11, 2002||FPAY||Fee payment|
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