Impact of Line Edge Roughness on Tri-Gate Bulk MOSFET Performance
Xin Sun, Tsu-Jae King Liu and Nattapol Damrongplasit
Integrated Modeling Process and Computation for Technology (IMPACT)
The effect of Gate Line-Edge Roughness on the performance of Planar and Tri-Gate Bulk MOSFET structures has been studied via 3-D device simulation. The result shows that Tri-Gate Bulk MOSFET structure shows less gate-LER-induced variation in performance.