|Publication number||US7436861 B2|
|Application number||US 10/268,056|
|Publication date||Oct 14, 2008|
|Filing date||Oct 9, 2002|
|Priority date||Oct 9, 2002|
|Also published as||US20040071151|
|Publication number||10268056, 268056, US 7436861 B2, US 7436861B2, US-B2-7436861, US7436861 B2, US7436861B2|
|Inventors||Ian W. Jones|
|Original Assignee||Sun Microsystems, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Non-Patent Citations (1), Classifications (12), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to the design of circuits that operate asynchronously. More specifically, the present invention relates to an asynchronous control circuit with symmetric forward and reverse latencies.
2. Related Art
As computer system clock speeds become progressively faster, it is becoming increasingly harder to synchronize the actions of computer system components with reference to a centralized system clock. To deal with this problem, computer system designers are beginning to investigate the use of asynchronous circuits that operate in a self-timed manner, without having to adhere to the constraints imposed by a centralized system clock.
Asynchronous circuits often make use of “control queues” to coordinate the movement of data between asynchronously controlled latches. Note that a control queue can be constructed using GasP modules, see “GasP: A minimal FIFO control,” by Ivan Sutherland and Scott Fairbanks, Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 46-53, IEEE Computer Society Press, March 2001. See also, U.S. Pat. No. 5,937,177 to Molnar and Fairbanks and U.S. Pat. No. 6,356,117 to Sutherland, et al. concerning asP* and GasP circuits, respectively.
Each of these control queue modules is known as a decision-wait module and can be constructed from a pair of GasP Join modules as is illustrated in
A decision-wait module is well known in the field of asynchronous design.
Control queues and FIFOs that have a longer forward latency and shorter reverse latency tend to be used in application where it is desirable to operate in a mode where the queue or FIFO is more than half full. They also offer better matching between control and data flow in FIFOs: a bundling constraint is that control must never progress ahead of its associated data. Control circuits that have less forward latency and longer reverse latency are often favored in applications where queues or FIFOs are operating closer to empty and thus each item input will propagate more quickly to the output. However, it is often difficult to match such control to the movement of data in a FIFO because the data movement tends to be the limiting delay in forward latency.
Each of the above described control queues can be useful for certain applications that have different latency requirements for item flow and bubble flow. However, in some applications it is desirable to provide equal latency for item flow and bubble flow. Hence, what is needed, is an apparatus and a method that facilitates controlling an asynchronous circuit using a control queue with equal item flow and bubble flow latencies.
One embodiment of the present invention provides a control queue for an asynchronous circuit that includes a number of control modules coupled together linearly to form the control queue. These control modules include a prior module, a present module, and a next module. The present module is configured to receive one or more forward-going inputs from the prior module and one or more reverse-going inputs from the next module. The present module asynchronously generates one or more forward-going outputs to the next module and one or more reverse-going outputs to the prior module. The modules within the control queue are constructed so that the latency of the forward-going signals through the control queue is equal to the latency of the reverse-going signals through the control queue.
In a variation of this embodiment, the present module is configured to asynchronously perform a decision-wait function on the one or more forward-going inputs received from the prior module and the one or more reverse-going inputs received from the next module. This decision-wait function asynchronously generates the one or more forward-going outputs to the next module and the one or more reverse-going outputs to the prior module when sufficient of the inputs to the decision-wait function are asserted.
In a further variation, the control signals between modules alternate in polarity. For example, an assertion of a forward-going signal is encoded as a high voltage between the prior module and the present module, and is encoded as a low voltage between that present module and the next module.
In a further variation, successive modules in the control queue alternate between 2-4 GasP modules and 4-2 GasP modules.
In a further variation, the control queue is coupled to a number of successive stages of latches that operate under control of corresponding control modules in the control queue.
In a further variation, the latency of forward-going control signals and reverse going control signals through the control queue are each an odd number of gate delays.
In a further variation, the average latency of forward-going control signals and reverse going control signals through the control queue are each three gate delays.
In a further variation, the average latency of forward-going control signals and reverse going control signals through the control queue are each five gate delays.
Control circuits that have equal forward and reverse latencies offer advantages in systems where queues and FIFOs operate closer to half-full, such as are common in buffers between processing modules, and between memory systems and processing modules. In this scheme as in the prior art schemes, the sum of the forward and reverse latencies is the same. E.g., with the 4-2 GasP control circuit family, we can now offer forward latencies of two, three, or four units of delay per stage with corresponding four, three, or two units of reverse latency, respectively. In all three versions, the sum of the forward and reverse latencies is six units of delay.
The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
GasP Module with Three Units of Delay in Each Direction
FIFO With 3-3 Control Queue
FIFO With 5-5 Control Queue
We denote a GasP module by means of a rectangular box with an arrow inside that indicates the forward direction and a series of connections. The input and output signal connections denote the events that are associated with the GasP module.
Each control signal connection between GasP modules is implemented as a tri-state wire with a keeper, also known as a “state conductor.” A tri-state wire is a wire that is either “driven HI”, “driven LO”, or “not driven.” To avoid clutter, connections in schematics appear as lines between GasP modules, and keepers are frequently not shown. When a connection is driven HI or LO, the connection will be driven for a short period only, a period that is long enough to set the keeper and wire HI or LO. The keeper will then keep the state of the connection when the wire is not driven. Using the GasP implementations of
In order for these implementations to work correctly, all transistors must be properly sized. Here, this means that all gates must have the same step-up ratio, i.e., the ratio between each gate's drive strength and output load is the same. When properly sized, each gate has about the same delay, and thus we can justifiably speak about units of delay between any two events.
In an implementation we indicate the initial state of each connection by either filling in or not filling in the input triangles of the modules. A connection with a filled in triangle is initially asserted, that is, the connection is initialized LO when it is a forward-going input, and initialized HI when it is a reverse-going input.
The above descriptions are for the 4-2 GasP family of modules that have a forward latency of four units and a reverse latency of two units. The same circuit techniques and principles can be applied to GasP circuit families such as 6-4 GasP and 8-6 GasP.
The foregoing descriptions of embodiments of the present invention have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the present invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present invention. The scope of the present invention is defined by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5386585 *||Nov 18, 1993||Jan 31, 1995||Intel Corporation||Self-timed data pipeline apparatus using asynchronous stages having toggle flip-flops|
|US6356117 *||Sep 29, 2000||Mar 12, 2002||Sun Microsystems, Inc.||Asynchronously controlling data transfers within a circuit|
|US6700410 *||Jul 23, 2002||Mar 2, 2004||Sun Microsystems, Inc.||Method and apparatus for asynchronously controlling a high-capacity domino pipeline|
|US6958627 *||Sep 21, 2001||Oct 25, 2005||Trustees Of Columbia University In The City Of New York||Asynchronous pipeline with latch controllers|
|1||Publication entitled "GasP: A Minimal FIFO Control," by Ivan Sutherland and Scott Fairbanks, 2001 IEEE, Proceedings of Seventh International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 46-53.|
|U.S. Classification||370/546, 326/93, 713/400|
|International Classification||G06F5/08, H04L5/00, H04L12/56, H03K19/00, H04L25/30, H04J99/00|
|Cooperative Classification||G06F2205/067, G06F5/08|
|Oct 9, 2002||AS||Assignment|
Owner name: SUN MICROSYSTEMS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JONES, IAN W.;REEL/FRAME:013381/0188
Effective date: 20021007
|Mar 14, 2012||FPAY||Fee payment|
Year of fee payment: 4
|Dec 16, 2015||AS||Assignment|
Owner name: ORACLE AMERICA, INC., CALIFORNIA
Free format text: MERGER AND CHANGE OF NAME;ASSIGNORS:ORACLE USA, INC.;SUN MICROSYSTEMS, INC.;ORACLE AMERICA, INC.;REEL/FRAME:037303/0349
Effective date: 20100212