|In the previous OQPSK Simulink Exercise
the carrier phase was assumed known.
In practice, the carrier phase is unknown and must be estimated from the
received signal using a carrier phase estimator.
In this exercise, you will design a carrier phase synchronizator for
Offset-QPSK based on a discrete-time phase-locked loop.
The system will be used to process the data contained in the file
The carrier phase error detector for non-offset QPSK possessed a 90-degree phase ambiguity. For Offset-QPSK, the carrier phase error detector possesses a 180-degree phase ambiguity. However, for Offset-QPSK, an additional ambiguity exists. It will not be known which sample index corresponds to the inphase component and which sample corresponds to the delayed quadrature component. Thus a differential encoder/encoder must account for this additional ambiguity. In this exercise, such a differential encoding is used.
modulation: OQPSK pulse shape: HS average energy: 2 Watt-seconds normalized symbol rate: 1/20 symbol/sample normalized carrier frequency: 0.3 cycles/sample carrier phase: unknown symbol clock offset: 0 sec input file: oqpskcrdata.mat ambiguity resolution: differential encoding (described below) packet format: SYNC = 00 00 00 00 00 00 00 00 DATA = 434 symbols (868 bits)
This packet is repeated approximately 3 times
b(1) b(2) b(3) b(4) ... b(n) b(n+1) ...where the Matlab convention of starting with index 1 (instead of index 0) has been used. Without differential encoding, data bits b(1) and b(2) select the first OQPSK symbol, data bits b(3) and b(4) select the second OQPSK symbol, and so on. Let the differentially encoded bits be
d(1) d(2) d(3) d(4) ... d(n) d(n+1) ...where the differential encoding rule is
d(n) = b(n) XOR ~d(n-1) d(n+1) = b(n+1) XOR d(n)for odd values of n where ~d(n-1) means the logical complement of d(n-1). The differentially encoded bits are now used to select the OQPSK symbol as illustrated by the bit-to-symbol mapping above. d(1) and d(2) select the first OQPSK symbol, d(3) and d(4) select the second OQPSK symbol, and so on.
b(n) = d(n) XOR ~d(n-1) b(n+1) = d(n+1) XOR d(n)for n odd. (As before, ~d(n-1) means the logical complement of d(n-1).)
Note that unlike the detector in the previous exercise, that inphae and quadrature matched filter outputs are both sampled at 2 samples/symbol.
The detector requires a commutator which can be thought of as a serial-to-parallel converter. The data samples arrive at the input at a rate equivalent to 2 samples/symbol and are output in two parallel streams at a symbol rate equivalent to 1 sample/symbol. The commutator may be constructed in Simulink using a pair of downsample blocks with different sample offsets as shown below.
Note that the loop filter and DDS operate at 2 samples/symbol. Since the phase detector operates at 1 sample/symbol, the phase detector output is upsampled by 2 (by inserting a zero) prior to being filtered by the loop filter.
Design the phase detector and loop filter using blocks form the Simulink, Communications, and DSP Blockset libraries. I used the following settings in my design (these values are normalzed to the symbol rate):
normalized bandwidth: 0.05 damping factor: 1
Important Hint: Care must be taken to ensure that the commutators outputs are properly aligned with the indices required by the phase error detector and the decision subsystem.
Start time 0.0 Stop time (8+434+2)*20*3 Solver options Fixed-step discrete (no continuous states) Fixed-step size: 1