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Recent Integration, the VLSI Journal Articles
Recently published articles available on ScienceDirect.
Young-Ho Seo | Ji-Sang Yoo | Dong-Wook Kim
In this paper, we propose a hardware (H/W) architecture to find disparities for stereo matching in real time. After analyzing the arithmetic characteristic of stereo matching, we propose a new calculating...
David Watson | Ali Ahmadinia
Multiprocessor System on Chips (MPSoCs) are quickly becoming the mainstay in embedded processing platforms due to their hardware and software design flexibility. This flexibility increases the design...
A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology
In this paper, a new leakage-tolerant domino circuit is presented which has lower power consumption and higher noise immunity without significant delay increment for wide fan-in gates. The main idea...
Elias Kougianos | Saraju P. Mohanty
Optimization of leakage power is essential for nanoscale CMOS (nano-CMOS) technology based integrated circuits for numerous reasons, including improving battery life of the system in which they are...
Jimson Mathew | Rajat Subhra Chakraborty | Durga Prasad Sahoo | Yuanfan Yang | Dhiraj K. Pradhan
Memristor is an exciting new addition to the repertoire of fundamental circuit elements. Alternatives to many security protocols originally employing traditional mathematical cryptography involve novel...
Sabooh Ajaz | Hanho Lee
This paper presents a novel multi-Gb/s multi-mode LDPC decoder architecture and efficient design techniques for gigabit wireless communications. An efficient dynamic and fixed column-shifting scheme...
Ying Zhang | Sui Chen | Lu Peng | Shaoming Chen
Recent experimental studies reveal that FinFET devices commercialized in recent years tend to suffer from more severe NBTI degradation compared to planar transistors, necessitating effective techniques...
Due to the limit of available layers and the existence of obstacles in a routing region, single-layer obstacle-aware routing becomes an important issue for substrate interconnections. In this paper,...
Available online 26 July 2015
Kan Xu | Eby G. Friedman
Power supply noise in three-dimensional integrated circuits (3-D ICs) considering scaled CMOS and through silicon via (TSV) technologies is the focus of this paper. A TSV and inductance aware cell-based...
Available online 22 July 2015
Laura Micconi | Jan Madsen | Paul Pop
In this paper we propose a system-level synthesis for MPSoCs that integrates multiple Application Specific Instruction Set Processors (ASIPs). Each ASIP is customized for a specific set of tasks. The...
Available online 21 July 2015
Yaniv Ben-Itzhak | Israel Cidon | Avinoam Kolodny
We present a novel methodology for analysis of the average end-to-end latency and link utilization of wormhole NoCs with heterogeneous link capacities and heterogeneous number of virtual channels per...
Available online 17 July 2015
I. Bastos | L.B. Oliveira | J. Goes | J.P. Oliveira | M. Silva
In this paper we present a balun low noise amplifier (LNA) in which the gain is boosted by using a double feedback structure. The circuit is based on a conventional balun LNA with noise and distortion...
Available online 13 July 2015
J. Funke | S. Hougardy | J. Schneider
We present a new algorithm designed to solve floorplanning problems optimally. More precisely, the algorithm finds solutions to rectangle packing problems which globally minimize wirelength and avoid...
Available online 8 July 2015
Salma Elabd | Waleed Khalil
The impact of CMOS technology scaling, on the tuning range and phase noise performance of mm-wave LC voltage controlled oscillators (LC-VCOs) is presented. As a preliminary step, the fundamental LC-VCO...
FPGA-based test bed for measurement of AM/AM and AM/PM distortion and modeling memory effects in RF PAs
Available online 2 July 2015
José Cruz Núñez-Pérez | José Ricardo Cárdenas-Valdez | Katherine Montoya-Villegas | J. Apolinar Reynoso-Hernández | José Raúl Loo-Yau | Christian Gontrand | Esteban Tlelo-Cuautle
Using a field-programmable gate array (FPGA) development board, a digital signal processor (DSP) builder, and the phase-to-amplitude conversion principle, a low-cost system for measuring the amplitude-to-amplitude...
Available online 26 June 2015
João Casaleiro | Luís B. Oliveira | Igor M. Filanovsky
In this paper the capacitive coupling in quadrature RC-oscillators is investigated. The capacitive coupling has the advantages of being noiseless with a small area penalty and without increasing the...
A wideband RF receiver with extended statistical element selection based harmonic rejection calibration
Available online 14 June 2015
Renzhi Liu | Lawrence Pileggi | Jeffrey A. Weldon
In this paper we present a wideband harmonic rejection (HR) RF receiver design. Both gain mismatch and phase mismatch of the HR mixer have been calibrated using a design and calibration method called...
Available online 14 June 2015
A. Saberkari | Sh Kazemi | V. Shirmohammadli | M.C.E. Yagoub
In this paper, an ultra-wideband (UWB) CMOS low noise amplifier (LNA) utilizing an active inductor-based input matching network is presented. The proposed 0.18µm CMOS LNA consists of three stages; a...
Available online 12 June 2015
S.R. Hasan | W. Gul | O. Hasan
3D Stacked IC (3D-SIC) technology is becoming increasingly popular due to its improved design density and performance. However, single global clock distribution to a 3D-SIC can be very challenging and...
Available online 5 June 2015
Zhiting Yan | Guanghui He | Weifeng He | Shuaijie Wang | Zhigang Mao
In this paper, a high performance parallel turbo decoder is designed to support 188 block sizes in the 3rd generation partnership (3GPP) long term evolution (LTE) standard. A novel configurable quadratic...
Masoud Daneshtalab | Nader Bagherzadeh | Hamid Sarbazi-Azad
Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures
Carlo Condo | Maurizio Martina | Massimo Ruo Roch | Guido Masera
Modern iterative channel code decoder architectures have tight constrains on the throughput but require flexibility to support different modes and standards. Unfortunately, flexibility often comes at...
Xiaohang Wang | Baoxin Zhao | Terrence Mak | Mei Yang | Yingtao Jiang | Masoud Daneshtalab
Design of future many-core chips is experiencing a paradigm shift to the so-called power-budgeting design, due to the widening gap between instantaneous power consumption and the allowed maximum power,...
A design space exploration methodology for customizing on-chip communication architectures: Towards fractal NoCs
A. Chariete | M. Bakhouya | J. Gaber | M. Wack
Recent studies have shown that On-Chip Interconnects (OCI) architecture represents one of the most important component that determines the overall performance of future System-on-Chip (SoC). In order...
Ramin Bashizade | Hamid Sarbazi-Azad
Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC...
Mehdi Modarressi | Nasibeh Teimouri | Hamid Sarbazi-azad
Reducing the NoC power is critical for scaling up the number of nodes in future many-core systems. Most NoC designs adopt packet-switching to benefit from its high throughput and excellent scalability....
G.B. Vece | M. Conti | S. Orcioni
The increasing complexity of VLSI digital systems has dramatically supported system-level representations in modeling and design activities. This evolution makes often necessary a compliant rearrangement...
Chunhong Chen | Ran Xiao
Reliability is becoming one of increasingly critical issues for design of modern integrated circuits, due to the continuous scaling of CMOS technology and emerging nano-scale devices. This paper presents...
A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20nm FinFET technologies
Mohammad Ansari | Hassan Afzali-Kusha | Behzad Ebrahimi | Zainalabedin Navabi | Ali Afzali-Kusha | Massoud Pedram
In this paper, a 7T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed 5T cell...
Pasquale Corsonello | Fabio Frustaci | Stefania Perri
Ultra-Low-Power circuits demand has dramatically increased in the last few years. One of the main challenges in designing these circuits is that transistors often run in the sub-threshold regime and...
Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling
Rajit Karmakar | Santanu Chattopadhyay
This paper addresses the issue of power-aware test scheduling of cores in a System-on-Chip (SoC). While the existing approaches either use a fixed power value for the entire test session of a core or...
Ahmet Unutulmaz | Günhan Dündar | Francisco V. Fernández
In this paper, it is shown that the area optimization problem of a compact slicing floorplan may be formulated as a convex optimization problem when the areas of the analog components are modeled with...
Three-dimensional switchbox multiplexing in emerging 3D-FPGAs to reduce chip footprint and improve TSV usage
Marzieh Morshedzadeh | Ali Jahanian | Payam Pourashraf
Three-dimensional integration technology is proposed to break down long wires and increase integration level of emerging complex designs. However, efficiency of this technology heavily depends on the...
Sotiris Matakias | Yiorgos Tsiatouhas | Angela Arapoyanni | Themistoklis Haniotakis
Although IDDQ testing has become a widely accepted defect detection technique in CMOS ICs, its effectiveness in nanometer technologies is threatened by the increased leakage current variations. In this...
Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFET technologies due to atmospheric radiation
G. Hubert | L. Artola | D. Regis
This paper investigates the impact of terrestrial radiation on soft error (SE) sensitivity along the very large-scale integration (VLSI) roadmap of bulk, FDSOI and finFET nano-scale technologies using...
Prakash Harikumar | J. Jacob Wikner
This paper presents the design of a 10-bit, 50MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65nm CMOS process....
Hooman Farkhani | Ali Peiravi | Farshad Moradi
In this paper, a new write assist technique for SRAM arrays is proposed. In this technique, to improve the write features of the SRAM cell, a negative voltage is applied to one of the bitlines in the...
Rapid estimation of the probability of SRAM failure via adaptive multi-level sliding-window statistical method
Zhenyu Wu | Changhao Yan | Xuan Zeng | Sheng-Guo Wang
Statistical analysis of SRAM has emerged as a challenging issue because the SRAM cell failure probability is extremely small. In this paper, we develop a novel efficient sampling, searching and estimating...
Pooria M. Yaghini | Ashkan Eghbal | Nader Bagherzadeh
Efficient on-chip communication is necessary for exploiting enormous computing power available on a many-core chip. Routing algorithms play a major role for the communication quality and performance...
Available online 18 May 2015
A. Sallem | P. Pereira | M. Helena Fino | M. Fakhfakh
This paper proposes a hybrid methodology for the evaluation of integrated inductors sensitivity against technological/geometrical parameters variation. The obtained results are used in an optimization-based...
Available online 8 May 2015
R. Póvoa | I. Bastos | N. Lourenço | N. Horta
Typically the design of a Radio-Frequency (RF) circuit is difficult, time-consuming and often based around an iterative process. In this manuscript, an automatic synthesis of three typical blocks of...
Available online 23 April 2015
Atefeh Salimi | Rasoul Dehghani | Abdolreza Nabavi
In this paper, a novel digital predistortion assisted supply modulator is presented. The proposed modulator is suitable for envelope tracking power amplifiers. In this topology, a digitally controlled...
Available online 17 April 2015
Daniel Grissom | Christopher Curtis | Skyler Windh | Calvin Phung | Navin Kumar | Zachary Zimmerman | Kenneth O‘Neal | Jeffrey McDaniel | Nick Liao | Philip Brisk
This paper describes a publicly available, open source software framework designed to support research efforts on algorithms and control for digital microfluidic biochips (DMFBs), an emerging laboratory-on-a-chip...
Post-process die-level electromagnetic field analysis on microwave CMOS low-noise amplifier for first-pass silicon fabrication success
Available online 24 March 2015
Farshad Eshghabadi | Fatemeh Banitorfian | Norlaili Mohd Noh | Mohd Tafir Mustaffa | Asrulnizam Abd Manaf
In this study, the die-level electromagnetic interaction between components and parasitic interconnection extraction are evaluated with the measurement results of a 0.13μm radio-frequency CMOS low-noise...
Synthesis of biochemical applications on digital microfluidic biochips with operation execution time variability
Available online 13 March 2015
Mirela Alistar | Paul Pop
Microfluidic-based biochips are replacing the conventional biochemical analyzers, and are able to integrate all the necessary functions for biochemical analysis. The digital microfluidic biochips are...
Anupama R. Subramaniam | Janet Roveda | Yu Cao
Timing characterization of sequential elements, such as latches and flip-flops, is one of the critical steps for timing closure in the pipelined design. Traditional characterization of setup and hold...
Xiao Zhao | Huajun Fang | Tong Ling | Jun Xu
A proposed transconductance enhanced method for low-voltage bulk-driven input stage is presented in this paper. The basic idea is to use current–shunt auxiliary amplifier to improve the voltage gain...
Hardware implementation of a spatio-temporal average filter for real-time denoising of fluoroscopic images
M. Genovese | P. Bifulco | D. De Caro | E. Napoli | N. Petra | M. Romano | M. Cesarelli | A.G.M. Strollo
An electronic system for the real-time denoising of fluoroscopic images is proposed in this paper. Fluoroscopic devices use X-rays to obtain real-time moving images of patients and support many surgical...
Synthesis-based design and implementation methodology of high-speed, high-performing unit: L2 cache unit design
Mozammel Hossain | Chirag Desai | Tom Chen | Vikas Agarwal
We propose a physical design methodology for synthesis using soft hierarchy, interior pin placement, pre-placing critical logic, and routing techniques on a very timing- and area-challenged unit, the...