I recently ran into this unusual article written by Joe Fjelstad and published on the Global SMT & Packaging Web site. The article discusses the possibility of building hybrid chips using a brick-and-mortar approach as advocated by a joint paper published in 2007 by researchers from the University of Washington in Seattle and the University of Michigan in Ann Arbor. Essentially, the “mortar” is a silicon interposer, which may or may not have active elements on it. The bricks are small, single-function chips bonded to the interposer. In this way, you can assemble a more complex chip using a variety of IC process technologies as appropriate for each “brick.”
Here’s an illustration from the article to clarify:
Fjelstad amusingly refers to this assembly technique as a “dis-integrated” circuit.
The stated advantages of this approach are that it may enable the creation of a less expensive device than an FPGA or an ASIC that combines all of the mortared functions. Certainly, this approach permits the use of a variety of process nodes and varied IC processed (RF, analog, high-voltage, Flash, DRAM, etc.) that you cannot easily combine or cannot economically combine on one monolithic IC. Conceptually, this assembly technique can trace its roots back to 1953 (58 years!) and a US Navy Bureau of Aeronautics effort to develop an automated way of making modular electronics assemblies called Project Tinkertoy. That’s how far back this idea reaches. Of course, the first ICs were developed at TI and Fairchild only six years later and the rest is now IC history. Project Tinkertoy is scarcely remembered.
Perhaps this “bricks and mortar” approach to IC assembly was a somewhat revolutionary concept in 2007 when the paper was published. Today, it looks to me very much like the 2.5D tiling approach Xilinx is taking to the creation of large FPGAs based on its Virtex 7 generation. (See “3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?”)