VCTA: A Via-Configurable Transistor Array regular fabric
Document typeConference report
PublisherIEEE Computer Society Publications
Rights accessOpen Access
Layout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity must be pushed to the limit to deal with severe systematic process variations in future technology nodes. With this objective, we propose and evaluate a new regular layout style called Via-Configurable Transistor Array (VCTA) that maximizes regularity at device and interconnect levels. In order to assess VCTA maximum layout regularity tradeoffs, we implement 32-bit adders in the 90 nm technology node for VCTA and compare them with implementations that make use of standard cells. For this purpose we study the impact of photolithography proximity and coma effects on channel length variations, and the impact of shallow trench isolation mechanical stress on threshold voltage variations. We demonstrate that both variations, that are important sources of energy and delay circuit variability, are minimized through VCTA regularity.
CitationPons, M. [et al.]. VCTA: A Via-Configurable Transistor Array regular fabric. A: VLSI System on Chip Conference. "18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC)". Madrid: IEEE Computer Society Publications, 2010, p. 335-340.
- ARCO - Microarquitectura i Compiladors - Ponències/Comunicacions de congressos 
- Departament d'Arquitectura de Computadors - Ponències/Comunicacions de congressos 
- Departament d'Enginyeria Electrònica - Ponències/Comunicacions de congressos 
- HIPICS - High Performance Integrated Circuits and Systems - Ponències/Comunicacions de congressos