Issue No.01 - January/February (1986 vol.3)
H.s. Fung , GTE Laboratories, Inc.
S. Hirschhorn , GTE Laboratories, Inc.
This article discusses design for testability automation for the Silc silicon compiler under development at GTE Laboratories,Inc. Our modular design for testability uses both built-in self-test and scan-path techniques for Slic's full custom VLSIdesigns. A test controller coordinates the testing of the chip's modules. Testability evaluation is performed using controllability/observabilitymethods, and using a method based on information theory. A testable-by-construction approach is followed in order to synthesizeblocks of testable logic. A testability ?expert? manages testability knowledge during the synthesis process and makes theultimate testability decisions.
H.s. Fung, S. Hirschhorn, "An Automatic DFT System for the Silc Silicon Compiler", IEEE Design & Test of Computers, vol.3, no. 1, pp. 45-57, January/February 1986, doi:10.1109/MDT.1986.294938