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In this paper, a comparative analysis of existing architecture for flip-flops along with proposed designs is made. Flip-flops are the most essential element in the design of sequential circuits. Due to continuing increase in integration of transistors and growing needs of portable equipments, low power design with high performance is of prime importance. The proposed designs have better power delay product than the existing architectures and also occupy lesser area. Simulation has been done in the IBM 130nm technology using TSpice.