Adding More Assembly Lines
The end result is IA-64 and its EPIC technology, which lets a chip process more instructions in parallel. Jason Waxman, a performance marketing manager at Intel, explains the concept behind EPIC by comparing microprocessing to a traditional assembly line. "Rather than just crank up the speed of the assembly line, we've used EPIC to put multiple assembly lines into the same chip," he says.
Existing chips can occasionally execute multiple instructions in parallel, but the chips themselves typically use valuable resources to decide which instructions are conducive to parallel processing. With EPIC, software compilers make these decisions ahead of time, and the code arrives at the processor preformatted for multiple assembly lines. "The compiler becomes the intelligence behind the processor in terms of scheduling resources," says Krewell. "In the past, the hardware had to control this intelligence." The compiler not only relieves the chip of these duties but is better at performing them, allowing more work to be done in parallel.
IA-64 also makes use of predication (to remove branches in the code, further improving the level of parallelism) and data speculation (to anticipate what data an instruction is going to need, limiting processor wait times and memory latency). And it includes an enormous number of registers128 integer and 128 floating-pointreducing the number of times the chip is forced to access memory.
Originally, Merced was scheduled to introduce IA-64 to the world in the middle of 1999, butas is often the case with high-end microprocessorsits debut was long delayed. "Building a mainframe-class processor is like a mini moon launch," explains Krewell. "It's such a large and complex project, you're susceptible to delays."
After renaming it Itanium, Intel officially announced the chip this past May. The chip's die includes 32K of Level 1 cache and 96K of Level 2 cache. The Itanium sits on a cartridgemuch like cartridges used by the Intel Xeon processorsthat holds either 2MB or 4MB of Level 3 cache running in tandem with the processor's main clock. At the moment, the chip is available at either 733 or 800 MHz, and when paired with Intel's new 460GX chip set, it uses a 266-MHz bus, providing 2.1 GBps of bandwidth.
Being the first IA-64 chip, the Itanium doesn't quite fulfill the platform's potential, but it more than holds its own against competing RISC processors. Conclusive comparative performance evaluations are nonexistent, since applications ported to the new architecture are still works in progress, but preliminary performance data is intriguing. PC Magazine will be testing the chip extensively, but we can get some clues to its performance from some early testing done by Intel, ourselves, and others.
For e-commerce, Intel's SSL security performance and OLTP (online transaction processing) tests showed that the Itanium was faster than similarly configured UltraSPARC chips. In secure Web transactions per second, an Itanium/800 was about six times as fast as a similarly configured UltraSPARC II/400.
In terms of online transaction processing, the Itanium/800 was about 30 percent faster than a 750-MHz UltraSPARC III. On Linpack 1000, a calculation test that measures floating-point performance for technical computing, the Itanium really shone, with nearly twice the performance of an UltraSPARC III/750 processor. On the STREAM test, a measure of system memory bandwidth, the Itanium had about a 60 percent lead over the UltraSPARC III/750. Finally, when Nastran was used to test MCAE performance, the Itanium had up to four times the speed of the UltraSPARC II/400.
Of course, these are test scores publicized by Intel, so it's no wonder the Itanium comes out on top by a good margin. We did test an early build of a four-processor Dell PowerEdge 7150 server, and our results were consistent with Intel's scores.
For now, suffice to say that the IA-64 architecture will benefit those who are running servers with large databases or want security integrated into a back-end server. Workstation users will benefit if their applications rely heavily on floating-point calculations, or if they are designing complex systems and assemblies. For a complete comparison, we will need new cross-platform tests that use many different applications.
Until then, the Standard Performance Evaluation Corp. (SPEC) has developed 64-bit versions of its well-respected SPEC CPU2000 benchmark tests: SPECint2000, which measures performance using integer-based code, and SPECfp2000, a more rigorous test that examines not only floating-point performance but the performance of memory and cache.
According to Krewell, the chip's integer scores were unimpressive relative to the leading RISC processors, but its floating-point performance was outstanding. "The SPEC INT numbers are competitive but nothing exciting," he says. "But the SPEC FP numbers are just phenomenal, much better than those of UltraSPARC, Alpha, and PA-RISC. They just blew everybody away."
The platform isn't inherently deficient when it comes to running integer code. Krewell says that integer performance should be much better with the IA-64 follow-on to the Itanium, code-named McKinley: "McKinley will solve a few of the Itanium's problemsvarious pipeline bottlenecks and insufficient processing resourcesand it will have a much faster bus." When the Itanium was first being developed, 2.1 GBps was a lot of bandwidth for a front-side bus, but today it's subpar. The Pentium 4, for instance, has 3.2 GBps.
But even in its current incarnation, the chip will provide a significant boost to enterprise software, including ERP applications, large databases, and scientific and engineering toolsprovided, as we said, that these applications have been ported to the new platform. The 32-bit versions of the SPEC benchmark tests bear out the fact that the chip performs very poorly under x86 code.