PLease solve both a and b fullyImage text transcribed for accessibility: Logic using 3-state buffers Connect the outputs of three 3-state buffers together, and add additional logic to implement the function. Assume that C, D, and are data inputs to the buffers, and A and B pass through logic that generates the enable signals. Is your design in part (a) free of three-state output conflicts? If yes, state the reasons. If not, change the design if necessary to be free of such conflicts.