PORTLAND, Ore. Advances in the design and fabrication of semiconductors were unveiled here this week at the International Symposium on Physical Design (ISPD, April 13-16, 2008, Portland, Ore.). As the premier forum for sharing leading-edge results in chip-design methodologies, the ISPD also identifies future research trends years before they become commercialized. This year, topics ranged from the need for collaboration among chip makers at the 32-nanometer node, how logic-synthesis is solving problems with physical-synthesis, how radio-frequency interconnection strategies could enhance standard CMOS, to how the Taiwanese beat both the U.S. and Europeans in the ISPD Global Routing Contest.
The keynote address was given by Antun Domic, senior vice president and general manager at Synopsys Inc. (Mountain View, Calif.) According to Domic, all the major semiconductor makers--except Intel--need collaborative help to be successful in manufacturing at the 32-nanometer node.
"I'm not saying that Texas Instruments or NXP or the others will have to go fabless. What I'm saying is that instead of doing 32-nanometer themselves, they will need to share that process development with others, and then transfer the finished process to their own fabs. Of course, I don't think Intel needs help, but the IBM-led consortium [with Samsung Electronics, Infineon Technologies, ST Microelectronics, Chartered Semiconductor, Freescale, and Toshiba] is an example of what every semiconductor maker, except Intel, needs to do to get to the 32-nanometer node," said Domic.
Apparently verifying Domic's prediction, IBM and its partners recently claimed their jointly developed 32-nanometer process will use high-k dielectrics to trump the rest of the industry in speed and power consumption.
Of course, not all predictions made at ISPD have come to pass. In fact Domic begged to differ with past-ISPD keynote speaker, Magma Design Automation chief executive officer Rajeev Madhavan, who predicted "The Death of Logic Synthesis" in his 2005 address. Madhavan's point was that the preliminary circuits cast by logic synthesis could not accurately simulate the problems that would have to be faced when the circuit was physically implemented during the physical-design step, thus the solution to more and more problems were being delayed until physical design. If that trend continued, Madhavan argued, logic synthesis would eventually disappear into physical design. But, according to Domic, just the opposite has happened.
"What we are seeing today is a revival of logic synthesis," said Domic. "Physical synthesis is not just place-and-route anymore, but is being used together with logic synthesis. The two are becoming interleaved, along with design-for-manufacturability issues, giving designers more leverage."
The "Best Paper" award seemed to confirm Domic's thesis, by rewarding University of Michigan professors Igor Markov and Valeria Bertacco for their work on interleaving logic- and physical-synthesis. Markov and Bertacco showed how to use functional simulation and logic restructuring in a way that improves delay times without iterative design optimizations.
"Today, poor scaling in interconnects often necessitates many design optimizations to meet performance specifications due to the difficulty of estimating delays," said Markov. "Our solution to this problem is to identify interconnects amenable to optimization through logic restructuring and to use an algorithm to show which placed subcircuits hold the greatest promise for interconnect reduction."