Design and verification of new digital hardware blocks is becoming increasingly challenging. Today, designers are confronted with a host of issues, including growing design and verification complexity, time-to-market pressures, power goals, and evolving design specifications.
To tackle these challenges, customers are beginning to make a significant change in design methodology, by moving to SystemC transaction-level models (TLM) as the design entry point, and by leveraging high-level synthesis (HLS) in combination with IP reuse. This article presents our experience in working with Fujitsu Semiconductor Ltd. to adopt this new methodology using Cadence® C-to-Silicon Compiler on a data access controller design, and presents the very promising results they reported at a recent C-to-Silicon user group meeting in Japan. The selection of the design, modeling work, and results analysis described in this paper were performed by Fujitsu Semiconductor with some assistance from Cadence.
Motivation for Moving to a New Approach
While Fujitsu Semiconductor’s design groups are very experienced at design, verification, and synthesis at the register-transfer level (RTL), they have found that this approach has many limitations that have become an increasing problem as design and verification complexity increases.
Some of the key limitations with the RTL entry approach include:
- Very limited ability to perform algorithmic and architecture exploration, and thus a very limited ability to optimize area, power, and performance. This is because RTL designs are too detailed, and are not functional soon enough, to enable this type of exploration.
- Limited ability to build configurable models that can be reused in different environments. This is because the detailed structure of the design at the RT level is largely fixed.
- Inefficient verification. This is because the complexity of the RTL makes for increased chances for bugs, and it also makes debugging and isolating problems more difficult.
- Long design and verification times, delaying time to market.
Fujitsu Semiconductor expected to address these challenges by moving hardware design and verification to the SystemC transaction level, along with adopting high-level synthesis. TLM are more abstract than RTL models because they are focused on modeling the behavior of blocks, and they use function calls to model the transaction communication between blocks. HLS tools such as the Cadence C-to-Silicon Compiler use IEEE 1666-2011 SystemC TLM as their input, and automate many design tasks such as operation scheduling.
Fujitsu Semiconductor was looking to realize the following benefits by moving to TLM and HLS:
- Greater ability to perform algorithmic and architecture exploration and optimization, since the design model is much easier to change and is functional much sooner.
- Greater ability to build configurable models, by taking advantage of the powerful modeling capabilities in C++, and automatically generating the application-specific implementation with HLS.
- Much more efficient verification, since there is less chance for the designer to make mistakes, and also because debugging at the TLM level is easier.
- Shorter design and verification times, because of the above benefits.
- Ability to reuse the model for the hardware block in SystemC TLM2 virtual platform models for embedded systems, thus enabling hardware models and software components to be designed and verified in a more unified process.
For the TLM and HLS approach to be successfully adopted in production, it was necessary that the new approach meet Fujitsu Semiconductor’s quality of results (or "QoR") targets. In particular, the area, power, and performance of the hardware created via the TLM approach had to be nearly equal to, or better than, what is achievable via the hand-written RTL approach. Fortunately, their experience with Cadence C-to-Silicon Compiler has shown that they can exceed the QoR of hand-written RTL designs.