Farooqui, Aamir A. and Oklobdzija, Vojin G. and Sait, Sadiq M. (2003) AREA-TIME OPTIMAL ADDER WITH RELATIVE PLACEMENT GENERATOR. In: IEEE International Symposium on Circuits and Systems'', Bangkok, Thailand.
ABSTRACT This paper presents design of an adder generator, for the production of area-time-optimal adders. A unique feature of the proposed generator is its integrated synthesis and layout environment achieved by providing relative placement information to the synthesis tool. Adders produced by this generator are dynamically configured for a given technology library, wire-load model, delay, and area goal. The adder architecture used in this generator is a hybrid of Brent & Kung, carry select, and ripple carry adders. When compared with standard cell fast adders, a 20%-50% reduction in area with comparable delays is achieved. The reduction comes from a judicious selection of ripple carry or carry select adders based on computation of delays. When performance is being met, the carry select adders are replaced with ripple carry adders. The proposed generator has been integrated into a commercially available high-performance datapath design tool.
|Item Type:||Conference or Workshop Item (Other)|
|Date:||01 May 2003|
|Divisions:||College Of Computer Sciences and Engineering > Computer Engineering Dept|
|Creators:||Farooqui, Aamir A. and Oklobdzija, Vojin G. and Sait, Sadiq M.|
|Email:||firstname.lastname@example.org, UNSPECIFIED, email@example.com|
|Deposited On:||25 Feb 2008 09:34|
|Last Modified:||12 Apr 2011 13:06|
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