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In this work an efficient approach is used to optimize the power and delay of the global interconnects. The low swing method is optimized and used for various lengths of the global interconnects. Current mode driver and receiver (CMDR) technique are presented. Additionally, a random search algorithm known as Simulated Annealing (SA), improved by an intelligent fashion using a piecewise linear and logarithmic cost function, has been employed to optimize power and delay of the long global interconnects. For verification purposes, several circuits are designed and simulated with Hspice for 0.13 mum technologies. The simulation results show a 25% reduction in power and a 28% reduction in delay with respect to previous designs in the literature.