Omnivision patent application US20090302358 discloses a technique to increase the photodiode full well capacity in 4T pixel. The proposal is to reduce a transfer gate sidewall spacer closest to the photodiode, as shown on the figure below:
One may ask how this increases the full well of photodiode? Here is the explanation:
In the conventional process for fabricating a CIS, after the gate layer has been formed, the PD region is implanted next to the gate of the transfer transistor. After the PD region is implanted, but before the sidewall spacers of the transfer transistors are formed, the pinning layer is implanted. This order of fabrication provides pinning under the sidewall spacers, which helps to reduce dark current and white pixels. However, the thermal processing for sidewall spacer formation also causes the P type dopants of the pinning layer to diffuse, resulting in a less abrupt p-n junction and therefore a lower full-well-capacity.
In the Omnivision's proposal the abrupt junction of pinning layer is achieved by reordering the implanting pinning layer step to be after formation of sidewall spacers. To compensate for process reordering, thinned sidewall spacer is thinned relative to regular sidewall spacer. Sometimes the thinned sidewall spacer could be entirely removed.