Workshop on Modeling, Benchmarking and Simulation
Held in conjunction with the 33rd Annual International Symposium on Computer Architecture
With few exceptions, simulation is the quantitative foundation for virtually all computer architecture research and design projects – from microarchitectural exploration to hardware and software trade-offs to processor and system design. However, its continued efficacy is limited by problems such as increasing complexity, additional critical constraints (e.g. power consumption, reliability, etc.), an ever expanding design space, benchmark suite quality and coverage, and radical changes in processor architectures to compensate for technological changes (i.e. reduced transistor widths, etc.).
The primary goals of this workshop are to accelerate the development of simulation technologies that are necessary to support the research of future generation architectures – in particular, processors built with nanotechnology – and to encourage the advancement of “under-researched” areas in computer architecture measurement, such as multiprocessor simulation methodology; modeling; benchmark implementation and benchmark suite construction; and formal methods of design space exploration and performance analysis.
Topics of interest include, but are not limited to:
· New or efficient techniques to model performance, power, reliability, etc.
· Reduced simulation time techniques
· Simulation methodologies for multiprocessor simulation
· Development of parameterizable, flexible benchmarks
· Formal methods for benchmark suite construction or benchmark suite sub-setting
· Techniques to measure the characteristics (dissimilarity, coverage, etc.) of a benchmark suite
· Efficient processor modeling techniques
· Alternatives to cycle-accurate, execution-driven simulation
· Statistically-rigorous performance analysis techniques
· Analytical and statistical models
This workshop places a special premium on novelty and on preliminary work.
The authors should submit a 200 word or less
abstract by (CST)
Full Paper Submission:
Final Version Due:
Workshop Date: June 18, 2006
Joshua J. Yi, Freescale Semiconductor (firstname.lastname@example.org)
David I. August,
Pradip Bose, IBM Research T.J. Watson
Gabriel Loh, Georgia Tech
Peter S. Magnusson, Virtutech
Gokhan Memik, Northwestern University
Olivier Temam, INRIA
Call For Papers