A high performance class-D amplifier with cascaded sigma-delta modulators
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The focus of this thesis is on analysis, simulation and board level implementation of the proposed Class-D power amplifier architecture. The structural design consists of two Sigma-Delta Modulator (SDM) stages in cascade with an intermediate decimation-filter between them. Noise and high tone introduced at the first- stage is filter out through the decimation filter. The signal is converted to a 1-bit Pulse Duration Modulation (PDM) signal by the second stage SDM. The H-Bridge is made part of the SD loop, which enables not only the noise shaping of the quantization noise but also stabilizes the output power switching stage. Output of the H-Bridge is converted to a digital signal using a comparator and latch circuitry and is fed back. To further increase the linearity and performance, high frequency ripples introduced at the H-Bridge is quantized by using a 4-bit SD Analog-to-Digital Converter (ADC) in the feedback loop. Due to the intermediate digital stage and the feedback control at the output stage, the proposed structure has high efficiency and linearity and still is very compact making it possible for wide range of applications.