Sample and hold circuits are remarkable elements. Picking off a voltage and holding it is kind of nice, but may not be all that remarkable. Uses may not even come to mind. But let me tell you, they can do some very, very interesting things.
The most rudimentary voltage S&H is a switch and capacitor. (Yes, you could make a current S&H using an inductor and a switch across it to hold the current, but voltage and capacitance are far more common in electronic practice, and generally easier to use.)
Let the input have a voltage Vin, an impedance Zin, and the output have the voltage Vo and load Zo. When the switch is turned on, it is clear that, if Vo ≠ Vin, a current Ichg = ΔV / Zin flows, charging the capacitor. When Zo >> Zin, the capacitor charges arbitrarily close to Vin in a few time constants, τ ∝ C*Zin. When the switch is turned off, the capacitor (charged to Vo ≈ Vin initially) discharges with current Io = Vo / Zo over a period proportional to C*Zo. When Zin = 0 and Zo → ∞, we have idealized S&H behavior: the voltage is captured in infinnitessimal time, while the voltage is held for an infinite period of time without change.
This circuit works in reality, and we will encounter it later, but it has some nasty shortcomings: namely, the near-perfect impedances required to get high speed precision from it. A natural solution to this sort of problem, in many instances, involves putting it in a loop.
With the switch off, the op-amp can't change the capacitor, so regardless of the input voltage (and what the op-amp wants to do with its output), the capacitor remains fixed. When the switch turns on, the op-amp suddenly enters the loop and, if the output voltage is different from the input (a typical op-amp might reach for the power supply rails in just a few milivolts), the maximum charge rate is Ichg = ΔV / Rsw, where ΔV = Vo - Vsat (going down) or Vo - (Vcc - Vsat) (going up), where Vsat is the op-amp's saturation voltage (more or less) and Vcc is the supply voltage. (I'm assuming "Vee" is ground, but you can figure what it should be otherwise.) Within a few milivolts, the voltage settles to the input voltage in a typical settling transient, with time depending on accuracy, gain and the RC time constant formed by the op-amp's output impedance, the switch's resistance and the hold capacitor.
On the right side, there is the output buffer (gain of +1, let's say), which draws an input bias current Io, which must be very small. The capacitor, too, needs to have low leakage, as well as dielectric absorbtion. It's literally left to itself, so small changes in voltage resulting from whatever effects will distort the output. In terms of practical circuits, we can quite readily dig up parts capable of picoampere leakage, which is sufficient for a lot of applications.
Closed-loop sample and hold, realized. Note the catch diodes, which prevent the op-amp from saturating when disengaged, reducing capture time. The input op-amp can be bipolar or FET, while the output follower is typically a JFET or MOSFET type with extremely low leakage. Typical input bias currents are 50pA for LF353 and 20pA for TL072, increasing several orders of magnitude at maximum operating temperature. The TLC272, a MOSFET op-amp, is down around 0.6pA, and under 1nA over full ratings. You can also use a discrete JFET or MOSFET source follower, getting similar leakage in one component, at the expense of accuracy. The analog switch JFET can be a 2N3819, MPF102 or whatever. A MOSFET can also be used, but certain precautions must be covered: namely, if the substrate isn't taken out to a pin (it often isn't), you have to make the op-amp saturate negative, which works, but is an ugly hack.
When the HOLD wire is high (5V or so), the BJT is turned on and current is pulled from the op-amp, cutting off the JFET if the held voltage is high enough. When HOLD is low, the BJT is off and its collector swings up to the JFET's drain, turning it on. Current flows through its channel resistance, charging the capacitor. When HOLD goes high again, the JFET turns off and the input and output are once again disconnected. Caveat: notice Cg-s, the parasitic gate-source capacitance of the JFET. When the BJT pulls down, some charge is injected into the holding capacitor C, causing a slight error. This error depends on the voltage change, so it's a gain and offset type of error. Balanced switches, such as the topology used in the venerable 4066 CMOS bilateral switch, have more uniform coupling and on-resistance characteristics.
...So naturally, here's one of my ugly hacks! The four transistors on the top left make a rudimentary op-amp. Looking in my scratch book, I originally used a 10k resistor for the tail, not a 6mA CCS, and a 470 ohm resistor in series with the 100pF compensation capacitor. When holding, the diode to the inverting input forces the diff amp to saturate to +V (more or less), so the leakage through the switch MOSFET is its channel leakage. When sampling, the 2N4401 at the bottom turns off and its collector voltage rises. The diff amp comes back into play, while the switch MOSFET turns on. According to my notes, the period is about 3μs long from the instant the HOLD line goes low until the amp comes out of saturation (with a correspondingly large blip on the output!), it rings down and settles to within, oh, a few percent. The turn-off glitch was apparently a single cycle, implying something ringing, or perhaps a cascaded reaction (e.g., the diff amp's delayed response). With the parts shown installed on a solderless breadboard, I watched it hold for a whole minute, not seeing any change in the waveform. That's approximately a trace width out of 2V/div, so I might estimate it around 1/20th div, or 0.1V let's say. Out of 1nF and 60s, ≤0.1V gives I = C*dV/dt ≤ 1nF * 0.1V / 60s ≤ 1.7pA, not bad at all. With the three components (the two MOSFETs and the capacitor) wired point to point inside an electrostatic shield grounded to the output (thus isolating and diverting any external leakage), all that would be left is the intrinsic leakage of the components themselves.
This is one of the most interesting things to do with samplers, and yet, one of the simplest. Its operation is so wonderful it may be confusing, but I hope not. There aren't many blocks to it, and it has no overall feedback, so it should be pretty easy to explain. I don't have room for a full sized schematic, but a block diagram should suffice for this one anyway. (The full schematic, in discrete parts, counts 28 transistors and 1173x648 pixels, more than I have space to display in a web page, and only adds extra clutter to my explanation.)
This is a S&H circuit (top right block) which samples the input after a voltage-controlled delay. The delay is synchronized to the input waveform with a comparator (on the left), which is set to flip at some trigger level. When it crosses, the edge triggers a one-shot, non-retriggerable ramp (timebase) generator. (That is, it continues its ramp until it resets itself. Then it is able to be triggered again. If the input one-shot is longer than the ramp, then you get trigger holdoff, necessary for sampling over multiple cycles.) At any given point along the ramp, a voltage corresponds linearly to a time delay, so a voltage-variable time delay can be produced very easily. To vary the delay, a free-running sawtooth generator, which runs at a low audio frequency, perhaps 100Hz, generates horizontal sweep. When the ramp crosses the sweep voltage, a second comparator turns those voltages into a timing signal. The second comparator's edge is fed to a one-shot timer, which runs just long enough for the S&H circuit to settle. Once settled, it shuts off and the voltage is held until the next input cycle arrives. The result? A relatively fast waveform (up to perhaps 500kHz with discretes) gets chopped up into small pieces, and reconstructed at the sweep frequency. The result is a waveform which can be viewed on the slowest of displays: you could even slow down the sweep to 0.1Hz or so and plot it on graph paper with an X-Y plotter.
The unremarkable part about this is, the trigger circuits all need to be rather fast -- they have to accommodate the input signal's bandwidth and make use of it, after all. The S&H needs to acquire its signal very quickly. But the tantalizing part is that it can potentially touch those absurdly fast signals, in the GHz range, that are simply impossible to view on a CRT directly. And there are ways around bandwidth: for instance, you can build a synchronized oscillator that tracks harmonics (or subharmonics, or hetrodyned products) on the input. The timer only needs to run as fast as the timebase, which can be a few times slower than the input, in order to display a few cycles.
In another interesting twist of coming full circle, this circuit returns to the crudest first approximation. It's another thing about electronics that small, simple, compact circuits are capable of much faster operation. It follows that such a design would be used here. (In fact, I'm told that this general type of circuit, sampled with extremely fast snap recovery diodes, is the basis of all the high speed sampling oscilloscopes available today, extending out to 100GHz. That's near the beginning of far infrared!) This circuit uses the fastest diodes available, schottky RF mixer diodes, to act as dynamic resistances. When reverse biased (in this circuit, a total of -6V, able to accommodate a +/-3V peak input), little signal is passed, while when forward biased, the input (which must be low impedance, but that fortunately is not hard to come by) is connected to the output through the diodes' dynamic resistance (tens of ohms or less, typically), with current capacity up to that of the pulse applied.
Here is the sampling head as built, minus a few components. (I later added a 47 ohm termination resistor at the input (corresponding to a Thevenin impedance of about 24 ohms, a reasonably low value for dealing with things) and soldered coax cable directly to the board. Matter of fact, none of the hookup wires are on, in this picture...) Note the background circuit, which should look familiar! As this thing requires a balanced pulse to sample, I made a 1:1 balun, connected it to the output of my pulse generator and ran twisted pair (plus a ferrite bead to further improve balance) to the sampling head.
Bottom side. Note the ground plane filling unused space, reducing the distance any AC currents have to flow. The input and output cables are soldered to this plane. Not shown, I later added jumpers across the ground plane, between where the bias resistors and coupling capacitors connect to the diode bridge.
Coincidentially, this is my first PCB ever etched. I drew it with Sharpie marker, and etched in ferric chloride (prepared variously by dissolving rust in hydrochloric acid, which is just something I do). After rinsing generously in flowing water, I removed the resist with isopropyl alcohol, sanded the copper and tinned it before adding parts. Overall, I am impressed how easy this method is, compared to the intensive mechanical routing of bare perfboard or pad-per-hole assembly. A downside is, it is harder to change.
After much trouble setting it up and trying to get it to sync (both syncing the trigger to the input, and the pulse generator to my timing signal), I finally managed to obtain some on-screen displays. These were produced by plotting X-Y on the screen of voltage (right off the sampler, buffered by 1/2 LF353) versus sweep voltage, which corresponds to time as I said. This edge here corresponds to the lazy, arcing response produced by my function generator, which is about 50ns.
To illustrate ultimate capability, this is the highspeed jack on my function generator. The edge is clearly slew-rate-limited, which would be due to the falling edge of the avalanche pulse, I believe. This edge is about 10ns wide, as measured on my scope. This result is pretty close, despite being completely uncalibrated. I think I've got pretty reasonable slew rate capacity here.