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L3264PM3–723ISC3C LEGEND 32x64 PC133 SDRAM Performance Technology L3264PM3–723ISC3C 32x64 PC133 SDRAM FEATURES • PC133 compliant • JEDEC-standard 168-pin, dual in-line memory module (DIMM) • Unbuffered • 256MB non-ECC • Single +3.3V ±0.3V power supply • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal SDRAM banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8 or full page • Auto and Self Refresh capability • 4,096 cycle refresh (64ms) • LVTTL-compatible inputs and outputs • Infineon HYB39S256800CT-75 • Serial presence-detect (SPD) GENERAL DESCRIPTION The Legend L3264PM3–723ISC3C is a high-speed access operation. The modules are designed to CMOS, dynamic random-access 256MB memory operate in 3.3V, low-power memory systems. An module. The module consists of 8 Infineon auto refresh mode is provided, along with a power- HYB39S256800CT-75 DRAMS in TSOP-II 400-mil saving, power-down mode. All inputs and outputs packages, surface mounted to a 168-pin FR-4 are LVTTL-compatible. SDRAM modules offer printed circuit board. Read and write accesses to significant operating performance enhancement the SDRAM modules are burst oriented; accesses over asynchronous DRAM, including the ability to start at a selected location and continue for a synchronously burst data at a high data rate with programmed number of locations in a programmed automatic column-address generation, the ability to sequence. The address bits registered coincident interleave between internal banks in order to hide with the READ or WRITE command are used to precharge time and the capability to randomly select the starting column location for the burst change column addresses on each clock cycle access. The modules provide for programmable during a burst access. These dual inline memory READ or WRITE burst lengths of 1, 2, 4 or 8 modules are intended for mounting into 168-pin locations, or the full page. The modules use an edge connector sockets and offer a range of internal pipelined architecture to achieve high- operating frequencies suitable for a variety of high speed operation. Precharging one bank while bandwidth, high performance memory system accessing one of the other three banks will hide the applications precharge cycles and provide high-speed, random- SERIAL PRESENCE-DETECT OPERATION The module incorporates serial presence-detect be programmed by Legend to identify the module (SPD). The SPD function is implemented using a type and various SDRAM organizations and timing 2,048-bit EEPROM. This nonvolatile storage parameters. device contains 256 bytes. The first 128 bytes can ABSOLUTE MAXIMUM RATINGS* Voltage on Inputs, NC or I/O Pins Relative to VSS -0.3V to +4.6V Operating Temperature, T A (ambient) 0°C to +70°C Storage Temperature (plastic) -40°C to +120°C Power Dissipation 16W *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Page 1 Legend reserves the right to change products of 1 or specifications without notice. L3264PM3–723ISC3C LEGEND 32x64 PC133 SDRAM Performance Technology DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS PARAMETER/CONDITION SYMBOL MIN MAX UNITS INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2 VDD+0.3 V INPUT LOW VOLTAGE: Logic 0; All inputs VIL -0.3 0.8 INPUT LEAKAGE CURRENT: Any input 0V<VIN<VDD II(L) -80 80 (All other pins not under test = 0V) uA OUTPUT LEAKAGE CURRENT: IOZ -80 80 DQs are disabled; 0V<VOUT<VDD OUTPUT LEVELS: VOH 2.4 Output High Voltage (IOUT = -4mA) V Output Low Voltage (IOUT = 4mA) VOL 0.4 SPECIFICATIONS AND CONDITIONS PARAMETER/CONDITION SYMBOL PC133 UNITS OPERATING CURRENT: t CK = t CK(MIN.) ICC1 2720 All banks operated in random access, all banks operated in ping-pong manner. PRECHARGE STANDBY CURRENT: Power-Down Mode; ICC2P 24 CKE = LOW; All banks idle PRECHARGE STANDBY CURRENT: Active Mode; S0#-S3#=HIGH; CKE=HIGH; All ICC2N 720 banks active after tRCD met; No accesses in progress mA NO OPERATING CURRENT: t CK = min., CS = VIH (MIN.), CKE =VIH(MIN.) ICC3N 800 active state (max. 4 banks) CKE =VIL(MAX.) ICC3P 160 BURST OPERATING CURRENT: Read command cycling. ICC4 1760 AUTO REFRESH CURRENT: tRC=t RC(MIN) ICC5 4000 SELF REFRESH CURRENT: CKE<0.2V ICC6 24 SDRAM COMPONENT AC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL MIN MAX UNITS CL = 3 tAC 5.4 Access time from CLK (pos. edge) CL = 2 tAC 6 Address hold time tAH 0.8 Address setup time tAS 1.5 CLK high-level width tCH 2.5 CLK low-level width tCL 2.5 CL = 3 tCK 7.5 Clock cycle time CL = 2 tCK 10 CKE hold time tCKH 0.8 CKE setup time tCKS 1.5 CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 ns Data-in hold time tDH 0.8 Data-in setup time tDS 1.5 Data-out high-impedance time tHZ 3 7 Data-out low-impedance time tLZ 1 Data-out hold time tOH 3 ACTIVE to PRECHARGE command tRAS 45 120,000 ACTIVE to ACTIVE command period tRC 67 ACTIVE to READ or WRITE delay tRCD 20 Refresh period (4,096 cycles) tREF 64 PRECHARGE command period tRP 20 ACTIVE bank A to ACTIVE bank B command tRRD 15 Transition time tT 0.3 1.2 WRITE recovery time tWR 2 CLK SELF REFRESH exit time tXSR 1 CLK METROLOGY Page 2 Legend reserves the right to change products of 2 or specifications without notice. L3264PM3–723ISC3C LEGEND 32x64 PC133 SDRAM Performance Technology Page 3 Legend reserves the right to change products of 3 or specifications without notice.
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