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A 1.8-V 2-Gb NAND flash memory has been successfully developed on a 90-nm CMOS STI process technology, resulting in a 141-mm2 die size and a 0.044-μm2 effective cell. For the higher level integration, critical layers are patterned with KrF photolithography. The device has three notable differences from previous generations. 1) The cells are organized in a single (16K+512) column and 128K row array by adopting a one-sided row decoder in order to minimize the die size. 2) The bitline precharge level is set to 0.9 V in order to increase on-cell current. 3) During the program operations, the string select line, which connects the NAND cell strings to the bitlines, is biased with sub-VCC in order to avoid program disturbance issues.