|XMOS LTD. Patent applications|
|Patent application number||Title||Published|
|20110225571||STRUCTURAL ANALYSER - A method and corresponding tool, the method comprising: generating a lower-level control flow structure representing a portion of an executable program, the lower-level control flow structure comprising a plurality of lower-level nodes representing operations occurring within the program and a plurality of directional edges representing program flow between nodes; generating a higher-level control flow structure by matching a plurality of the lower-level nodes and edges to higher-level structure nodes representing internal structure, each higher-level structure node representing a group of one or more lower-level nodes and one or more associated edges; and using the higher-level control flow structure to estimate a timing property relating to execution of the program on a processor. The higher-level structure nodes are selected exclusively from a predetermined set of structure node patterns, each pattern in the set having at most one entry point and at most one exit point.||09-15-2011|
|20110225570||PROGRAM FLOW ROUTE CONSTRUCTOR - A method and corresponding tool, the method comprising: receiving as an input (a) a higher-level structure representing control flow through an executable program, the higher-level structure comprising one or more levels of parent nodes, each parent node representing internal structure comprising a group of one or more child nodes and one or more associated edges between nodes; and (b) an indication of at least one start and end instruction. The method further comprises probing the levels of the higher-level structure to extract a substructure representing a route through the program from the start to the end instruction, by selectively extracting nodes of different levels of parent to represent different regions along the route in dependence on a location of the start and end instructions relative to the levels of parent nodes; and based on the extracted substructure, estimating an execution time for the route through the program.||09-15-2011|
|20110066825||MESSAGE ROUTING SCHEME - Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most to least significant. Each node comprises: mapping means configured to map each component of the local node address onto a respective routing direction, and a switch arranged to receive a message having a destination node address identifying a destination node. The switch comprises: means for comparing the local node address to the destination node address to identify a the most significant non-matching component; and means for routing the message to another node, on the condition that the local node address does not match the destination node address, in the direction mapped to the most significant non-matching component.||03-17-2011|
|20100107146||DEVELOPMENT SYSTEM - A system comprising: a server; a computer terminal coupled remotely to the server via a network and installed with a web browser; and an external test platform, connected externally to the computer terminal, the test platform comprising a programmable target device and interface circuitry operable to communicate between the computer terminal and the target device. The server hosts a development tool available for download to the web browser via the network. The development tool comprises: one or more applets to be run by the web browser, and one or more web pages for display by the web browser to provide a user-interface for the development tool including to provide access to the one or more applets. The one or more applets at least comprise code-analysis applet software programmed so as when run by the web browser to operate said interface circuitry to: load code to be tested from the computer terminal onto the target device for test operation.||04-29-2010|
|20100001405||INTEGRATED CIRCUIT STRUCTURE - An integrated circuit and corresponding method of manufacture. The integrated circuit has a die comprising: an outer strengthening ring around a periphery of the die, the outer ring having one or more gaps; and an inner strengthening ring within the outer ring and around interior circuitry of the die, the inner ring having one or more gaps offset from the gaps of the outer ring. One or more conducting members are electrically isolated from said rings and electrically connected to the interior circuitry, each member passing through a gap of the inner ring and through a gap of the outer ring.||01-07-2010|
Patent applications by XMOS LTD.