Markus Stumptner and Franz Wotawa
The state of the art in integrated circuit design is the use of special hardware description languages such as VHDL. Designs are programmed in VHDL and refined up to the point where the physical realization of the new circuit or board can be created automatically. Before that stage is reached, the designs are tested by simulating them and comparing their output to that prescribed by the specification. The task of circuit design therefore becomes primarily one of software development. A significant part of the design effort is taken up by detection of unacceptable deviations from this specification and the correction of such faults. This paper deals with the development of VHDLDIAG, a knowledge-based design aid for VHDL programs, with the goal of reducing time spent in fault detection and localization in very large designs (hundreds of thousands of lines of code). Size and variability of these programs makes it infeasible in practice to use techniques based on a detailed representation of program semantics. Instead, the functional topology of the program is derived from the source code. Model-based Diagnosis is then applied to find or at least focus in on the component(s) in the program that caused the behavioral divergence. The support given to the developer is sufficiently detailed to yield substantial reductions in the debugging costs when compared to the current manpower-intensive approach. A prototype is currently being tested as an integral part of the standard computer-aided VHDL development environment. Discrimination between diagnoses can be improved by use of multiple test cases (as well as interactive input by the developer).