Issue No.05 - May (2005 vol.54)
Jun Yang , IEEE
Lan Gao , IEEE
Youtao Zhang , IEEE
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2005.80
Due to the widespread software piracy and virus attacks, significant efforts have been made to improve security for computer systems. For stand-alone computers, a key observation is that, other than the processor, any component is vulnerable to security attacks. Recently, an execution only memory (XOM) architecture has been proposed to support copy and tamper resistant software. In this design, the program and data are stored in an encrypted format outside the CPU boundary. The decryption is carried out after they are fetched from memory and before they are used by the CPU. As a result, the lengthened critical path causes a serious performance degradation. In this paper, we present an innovative technique in which the cryptography computation is shifted off from the memory access critical path. We propose using a different encryption scheme, namely, "pseudo-one-time pad” encryption, to produce the instructions and data ciphertext. With some additional on-chip storage, cryptography computations are carried in parallel with memory accesses, minimizing the performance penalty. We performed experiments to study the trade-off between storage size and performance penalty. Our technique reduces the performance overhead from 20.79 percent to 1.28 percent on average for reasonably sized (64KB) on-chip storage.
Memory design, hardware/software protection, security and protection.
Jun Yang, Lan Gao, Youtao Zhang, "Improving Memory Encryption Performance in Secure Processors", IEEE Transactions on Computers, vol.54, no. 5, pp. 630-640, May 2005, doi:10.1109/TC.2005.80