Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY IP
System-on-chips (SoCs) are offering higher performance, feature-rich applications, and higher quality multimedia content for mobile devices. These mobile multimedia devices require high-speed data transfers, and designers need to contend with pin count and channel limitations as well as bandwidth bottlenecks.
MIPI protocols based on the MIPI M-PHY are being adopted for storage and chip-to-chip connectivity to utilize the high performance and low power characteristics of the protocol and physical layer. This webinar provides an overview of the MIPI M-PHY and explains the integration challenges faced by designers while integrating M-PHY-based protocols into SoCs.
What attendees will learn:
- MIPI M-PHY basics and advantages
- A low-risk approach to designing a standard interface for storage and chip-to-chip connectivity
- Trends in the mobile electronics market and problems that MIPI protocols solve
- How to navigate existing and future protocols required in mobile electronics
Who should attend: SoC Design Engineers, ASIC Design Engineers, Designers of complex, high-performance systems, System architects and Engineering or Technical Managers