US 8198192 B2
Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.
1. A method of fabricating sophisticated gate electrode structures, comprising:
forming a gate dielectric material above a semiconductor region of a semiconductor device, said gate dielectric material comprising a high-k dielectric material;
forming a metal-containing material above said gate dielectric material, said metal-containing material comprising a threshold adjusting species;
performing a heat treatment to diffuse a portion of said threshold adjusting species into said gate dielectric material;
removing said metal-containing material from above said gate dielectric material;
performing a treatment to stabilize said gate dielectric material;
forming a metal-containing electrode material on said gate dielectric material; and
forming a gate electrode structure of a transistor on a basis of said metal-containing electrode material and said gate dielectric material.
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11. A method of fabricating sophisticated gate electrode structures, comprising:
forming a gate dielectric material above a first active region and a second active region;
forming a first metal-containing material selectively above said first active region;
forming a second metal-containing material above said second active region;
performing a heat treatment to initiate diffusion of a first species from said first metal-containing material in said gate dielectric material above said first active region and to initiate diffusion of a second species from said second metal-containing material into said gate dielectric material above said second active region;
removing said first and second metal-containing materials; and
performing a treatment to stabilize said gate dielectric material.
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This application claims priority to German Patent Application 10 20090 21486.0, filed on May 15, 2009.
1. Field of the Invention
Generally, the present disclosure relates to the fabrication of sophisticated integrated circuits including advanced transistor elements that comprise complex gate electrode structures including a sophisticated gate dielectric, such as a high-k gate dielectric, and a metal-containing electrode material.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity, which in turn causes an increase of gate resistivity due to the reduced dimensions, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon, due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations produced by volume production techniques. One reason for the dominant role of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, during anneal cycles to activate dopants and to cure crystal damage, without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material for a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon and metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a very pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required high capacitance between the gate and the channel region. For example, a channel length of approximately 80 nm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although the usage of high speed transistor elements having an extremely short channel may be restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical circuit portions, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may not be compatible with requirements for performance driven circuits, even if only transistors in speed critical paths are formed on the basis of an extremely thin gate oxide.
Therefore, various measures have been proposed for increasing the dielectric strength and the effective dielectric constant of the silicon dioxide material, such as performing treatments on the basis of nitrogen in order in incorporate a certain amount of nitrogen. Although these treatments of the base oxide material provide significant improvements, the further scaling of the transistor dimensions may demand even further sophisticated approaches. To this end, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide based gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide based layer. It has thus been suggested to replace at least a portion of the conventional silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides an increased capacitance based on the same or greater thickness as a silicon dioxide based layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone.
After forming sophisticated gate structures including a high-k dielectric material, however, high temperature treatments and other processes are required which may significantly affect the high-k material.
For this reason, many high-k dielectric materials may be subjected to a post-deposition treatment in order to achieve superior stability of the material characteristics during the further processing. For example, an encapsulation of the high-k dielectric material may typically be necessary in order to reduce the interaction with metal-containing electrode materials and other process environments encountered during the further processing of the device. Furthermore, the crystallization temperature of the high-k dielectric material may have to be increased to provide superior stability during subsequent high temperature processes that may typically be required for completing the basic transistor configuration. Other material modifications may involve a phase separation of the high-k dielectric materials and also diffusion of implantation species, which may be incorporated into an upper portion of the gate electrode structures during the further processing, may have to be blocked. Moreover, a shift of the work function and a reduction of the permittivity of the high-k dielectric material, which may be associated with an increase of layer thickness, may result in a significant threshold voltage variation of the transistor, which is believed to be caused by a substantial interaction of the gate stack materials with oxygen. For example, hafnium oxide and zirconium oxide may exhibit a very high oxidation rate in the presence of oxygen and elevated temperatures, thereby resulting in a pronounced modification of the material characteristics which may thus lead to a significant variability of transistor characteristics. Consequently, it may be very difficult to accurately adjust the threshold voltage of transistors on the basis of a high-k dielectric material that is provided in an early manufacturing stage. In some conventional approaches, a certain degree of stabilization of material characteristics may be accomplished by a treatment of the high-k dielectric material immediately after deposition, for instance in the form of nitridation and the like, in order to enhance the further processing of the sensitive gate dielectric materials. On the other hand, the threshold voltage of the transistors may have to be specifically adjusted on the basis of a specific work function metal in combination with the high-k dielectric material. In some conventional approaches, the threshold voltage adjustment may be accomplished by incorporating a certain metal species into the high-k dielectric material in order to obtain a desired work function in combination with a metal-containing material formed on the high-k dielectric layer. One efficient technique for incorporating the desired metal species into the high-k dielectric material is the provision of a cap layer including the desired diffusion species and performing a heat treatment to initiate the diffusion of the metal species into the high-k dielectric material. The incorporation of the desired metal species for N-channel transistors and P-channel transistors may typically be performed at any appropriate manufacturing stage, for instance, in a very late stage after completing the basic transistor configuration or in an early manufacturing stage, i.e., after providing the stabilized high-k dielectric material and forming a cap layer thereon, which may contain the desired metal species for the transistor under consideration. Due to the superior stability of the high-k dielectric material, however, moderately high process temperatures and concentrations of the desired metal species are required, which may negatively influence transistor characteristics, thereby reducing the finally achieved overall performance of the transistors.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure provides techniques and semiconductor devices in which enhanced integrity and thus stability of a high-k dielectric material may be achieved on the basis of an appropriate treatment, such as nitridation, oxidation and the like, wherein, prior to the stabilization of the material characteristics, a desired threshold adjusting species may be incorporated into the high-k dielectric material. To this end, the high-k dielectric material and an appropriate cap layer or cap layers may be formed prior to performing the stabilizing treatment so that superior performance of the diffusion process may be accomplished, wherein, after incorporating the threshold adjusting species in the high-k dielectric material, the subsequent stabilization may provide superior integrity and thus stability of the resulting threshold voltage. Consequently, after incorporating the desired threshold adjusting species into the high-k dielectric material, any appropriate electrode material may be deposited on the high-k dielectric material, which may be accomplished in an early manufacturing stage or after completing the basic transistor configuration.
One illustrative method disclosed herein comprises forming a gate dielectric material above a semiconductor region of a semiconductor device, wherein the gate dielectric material comprises a high-k dielectric material. The method further comprises forming a metal-containing material above the gate dielectric material, wherein the metal-containing material comprises a threshold voltage adjusting species. Moreover, a heat treatment is performed to diffuse a portion of the threshold adjusting species into the gate dielectric material. The method additionally comprises removing the metal-containing material from above the gate dielectric material and performing a treatment to stabilize the gate dielectric material. Additionally, a metal-containing electrode material is formed on the gate dielectric material. Additionally, the method comprises forming a gate electrode structure of a transistor on the basis of the metal-containing electrode material and the gate dielectric material.
A further illustrative method disclosed herein comprises forming a gate dielectric material above a first active region and a second active region. Additionally, a first metal-containing material is selectively formed above the first active region. The method additionally comprises forming a second metal-containing material above the second active region. Furthermore, the method comprises performing a heat treatment to initiate diffusion of a first species from the first metal-containing material in the gate dielectric material above the first active region and to initiate diffusion of the second species from the second metal-containing material into the gate dielectric material above the second active region. Additionally, the method comprises removing the first and second metal-containing materials and performing a treatment to stabilize the gate dielectric material.
One illustrative semiconductor device disclosed herein comprises a first active region and a first gate electrode structure formed on the first active region. The first gate electrode structure comprises a dielectric base material and a high-k dielectric material formed on the dielectric base material, wherein the high-k dielectric material comprises a first threshold adjusting metal species in the first gate electrode structure. The semiconductor device further comprises a second active region and a second gate electrode structure formed on the second active region. The second gate electrode structure comprises the dielectric base material and the high-k dielectric material formed on the dielectric base material, wherein the high-k dielectric material comprises a second threshold adjusting metal species in the second gate electrode structure. Additionally, the semiconductor device comprises a metal-containing electrode material that is formed on the high-k dielectric material in the first and second gate electrode structures.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure provides semiconductor devices and techniques in which sensitive gate dielectric materials may be treated to receive an appropriate species for adjusting overall transistor characteristics, such as the threshold voltage and the like, prior to performing a treatment for stabilizing the material characteristics of the gate dielectric layer. As previously explained, the principles disclosed herein may be advantageously applied to sensitive high-k dielectric materials which may have a tendency for changing material characteristics upon exposure to certain environmental conditions or process conditions that may be applied during the further processing of the semiconductor device. According to the principles disclosed herein, the desired transistor characteristics, for instance with respect to threshold voltage, may be adjusted after the deposition of the sensitive dielectric material and prior to any stabilizing treatment in order to enhance the efficiency of the incorporation of the desired species, such as a metal species. Consequently, the desired species may be incorporated by diffusion on the basis of less demanding process conditions, i.e., on the basis of a reduced process temperature and concentration, such that other device characteristics may be less affected by the threshold adjustment. Based on the subsequent preservation of the material characteristics by any appropriate modification, such as nitridation and the like, the further processing may be continued by providing a single electrode metal for both types of transistors, thereby increasing the overall process efficiency.
In some illustrative embodiments, the adjustment of transistor characteristics on the basis of incorporating a species into the sensitive dielectric material prior to the stabilization thereof may also be applied to sophisticated “conventional” gate dielectric materials, such as silicon dioxide-based materials, in combination with appropriate gate electrode materials, such as polysilicon, silicon/germanium and the like. Consequently, unless specifically set forth in the embodiments described herein or in the appended claims, the dielectric gate material should not be considered as being restricted to high-k dielectric materials.
Moreover, the semiconductor device 100 may comprise a gate dielectric material 110 formed on the semiconductor layer 102. In some illustrative embodiments, the gate dielectric material 110 may comprise a high-k dielectric material 112, such as hafnium oxide, zirconium oxide, hafnium silicon oxide and the like, depending on the overall process and device requirements. When a direct contact of the high-k dielectric material 112 with the semiconductor layer 102 may be considered inappropriate, for instance in view of thermal stability and the like, a dielectric base layer 111 may be provided to act as an interface between the high-k dielectric material 112 and the semiconductor layer 102. For example, the material 111 may represent a “conventional” silicon dioxide-based material having a desired reduced thickness of, for instance, approximately 1 nm and less. On the other hand, a combined thickness and relative permittivity of the gate dielectric material 110 may be selected so as to correspond to the desired transistor characteristics, possibly in combination with a certain modification of the characteristics of the dielectric material 110 in a later manufacturing stage. As previously explained, the material characteristics of the dielectric material 110 may be moderately variable, for instance with respect to one or more of the above-described influences, so that a stabilization of the material characteristics may be provided in a later manufacturing stage in which an additional adaptation, for instance, the overall dielectric constant, may also be accomplished by incorporating an appropriate species, such as nitrogen, oxygen and the like.
Furthermore, in the manufacturing stage shown, a cap layer 120 may be formed on the dielectric material 110 and may comprise any appropriate species that may be incorporated into the dielectric material 110 in order to adjust the characteristics thereof, for instance, with respect to a threshold voltage of a transistor that has to be formed on the basis of the gate dielectric material 110. Additionally, the cap layer 120 may also provide superior integrity of the gate dielectric material 110 during the further processing. In one illustrative embodiment, the cap layer 120 may comprise a first layer 121, which may comprise a desired diffusion species, such as a metal, that may be incorporated into the dielectric material 110 in order to obtain the desired work function and thus threshold voltage adjustment for a transistor still to be formed in and above the semiconductor layer 102. For example, the layer 121 may comprise a diffusion species in the form of aluminum, tantalum and the like, which may represent appropriate candidates for adjusting the threshold voltage of a P-channel transistor and an N-channel transistor, respectively. For example, the layer 121 may be provided in the form of a lanthanum layer with a thickness of several Angstrom, when an N-channel transistor is to be formed on the basis of the gate dielectric material 110. Furthermore, a second layer 122 may be provided, for instance, in the form of titanium nitride and the like, which may efficiently provide superior integrity during the further processing. It should be appreciated that the cap layer 120 may comprise additional layers, such as an additional titanium nitride layer directly formed on the high-k dielectric material 112, if considered appropriate for the further processing.
The semiconductor device 100 as illustrated in
The semiconductor device 100 as illustrated in
With reference to
The semiconductor device 200 as illustrated in
The semiconductor device 200 as illustrated in
Similarly, the gate electrode structure 235B may comprise the high-k dielectric material 212 formed above the base layer 211, wherein a diffusion species 221A, such as a lanthanum species and the like, may be incorporated in order to obtain the desired threshold voltage. Similarly, the layer 212 may comprise the species 212D for enhancing the stability of the material 212.
It should be appreciated that, if desired, the species 226A and 221A may also be incorporated into the base layer 211, thereby also modifying the characteristics thereof. For example, a silicon dioxide material may be converted into a silicate, thereby increasing the dielectric constant of the base material 211. Consequently, the above-described process sequence provides a high degree of flexibility in adjusting the overall transistor characteristics by appropriately modifying a sensitive gate dielectric material while nevertheless providing the different characteristics for N-channel transistors and P-channel transistors during a common manufacturing sequence.
The semiconductor device 200 as illustrated in
As a result, the present disclosure provides semiconductor devices and manufacturing techniques in which the diffusion of threshold adjusting species into the dielectric material of transistor elements may be enabled at reduced temperatures and doses compared to conventional strategies. The material characteristics may be “preserved” by a subsequent treatment, for instance on the basis of nitridation or any other appropriate treatment, thereby providing the required superior stability during the further processing. During the diffusion of the cap layer species into the dielectric material, the species may also be incorporated into a base layer, if desired, thereby enhancing the dielectric characteristics thereof. Similarly, during the subsequent treatment for stabilizing the sensitive gate dielectric material, a corresponding treatment of the base layer may be accomplished, for instance, by incorporating nitrogen and the like. Hence, after stabilizing the material characteristics of the sensitive gate dielectric material, the further processing may be performed by depositing a single metal-containing electrode material, thereby further enhancing the overall process efficiency. In some cases, the interdiffusion of material into the gate dielectric material in an early manufacturing stage may also be applied to silicon dioxide-based materials, wherein a subsequent treatment, such as a nitridation, may thus conserve previously adjusted material characteristics. Thereafter, a “conventional” electrode material, such as polysilicon, amorphous silicon, silicon/germanium and the like, may be deposited.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.