The FO4 delay is the delay of one inverter when driving four others over the minimal amount of wiring.
CMOS logic delay is inversely proportional to supply voltage. For instance:
Example: core area 64 mm²; average net length 0.1 mm; 400K gates/mm², a=0.25.
Net capacitance = 0.1 mm × 1 fF/mm × 400K × 64 mm² = 2.5 nF.
|Supply Voltage||Clock Freq||Static Power||Dynamic Power||Total Power|
Workstation microprocessors dissipate tens of Watts: hence cooling fans.
The table shows example power consumption for a circuit when clocked at different frequencies and voltages. The important thing to ensure is that the supply voltage must be sufficient for the clock frequency in use: too low a voltage means that signals do not arrive at D-type inputs in time to meet set up times.
Power consumption versus frequency is worse than linear: it goes with a power law.
In the past, chips were often core-bound or pad-bound. Pad-bound meant that the chip had too many I/O signals for its core logic area: the number of I/O's puts a lower bound on the perimeter of the chip.
Today's VLSI technology allows I/O pads in the middle of the chip and designs are commonly power-bound.
|14: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory.|