Fig. 1: Montecito A member of Intel’s Itanium family, part of the company’s shift to multicore processors. The dual-core chip contains up to 1.7 billion transistors and 24MB of cache memory. [ source ]
The spatial logic of the microchip provides us with an eminent example of high-density integration, optimised for processor performance and energy efficiency. Microchips are examples of organised complexity, with microchip designers acting as a centralised agency. In this sense they can be considered master-planners of a static, non-living system.
A microchip is a semiconductor substrate onto which large numbers of interconnected transistors are placed for the purposes of performing signal processing. A transistor can simply be thought of as a switching mechanism – a means to switch electrical current from one pathway to another. Fig. 1 shows Montecito, a dual core processor released by Intel in July 2006, containing 1.7 billion transistors fitted onto a 27.72 mm × 21.5 mm substrate (smaller than the surface area of a £2 coin). The dual core design is immediately visually evident as the image is a single configuration mirrored along a horizontal axis.
In contrast to the slow evolution of the urban landscape, successive generations of Microchips have, in just a few decades — under the strain of Moore’s law — produced the basis for an extraordinary new range of expressions, been the building blocks of a social re-configuration we have come to call the network society and increasingly become embedded in our built environment through the advent of ubiquitous computing. In them we see an evolving relationship between man and space, one in which the micron and the urban scale are intertwined.
The morphology of the integrated circuit is based on multiple phases of heuristic design strategies, primarily focused on optimising wire length, energy consumption and the spatial footprint of the components.
The integrated circuit is modeled as a hypergraph G(V,E), composed of a set of vertices V and a set of hyperedges E . Large-scale circuit placement begins with an iterative clustering process undertaken to reduce the complexity of the problem by grouping transistor sub-graphs with high clustering coefficients into single logical components. This produces a higher level circuit representation with fewer vertices and edges. The clustering phase is followed by two placement phases.
First is the floorplanning phase, which involves the top-level distribution of logical components, or blocks . Subject to vertical and horizontal constraints, components are arranged according to a packing algorithm. Signal flows mean some components will need to be placed in a particular sequence. This can be considered a spatial constraint satisfaction problem.
The two cores are placed centrally, each with two levels of caches at varying distances. The L1 (Level 1) cache is so-called because the processor core has quicker access to it by virtue of its placement (the cache has a lower interconnect delay). The overall processor performance is intimately related to how quickly signals can get to and from the processor and the cache, as there is a continuous flow when processing even rudimentary instructions.