Title page for ETD etd-11072008-063637
|Type of Document
||Controlled on-time power factor correction circuit with input filter
||Master of Science
|Lee, Fred C.
|Cho, Bo H.
|Date of Defense
An active power factor correction circuit with controlled on-time is proposed. The circuit has
a simpler control scheme than the power bc10r correction circuit with hysteresis control, and yet
is able to attain high power factor. A very important aspect of this work was the formulation of the
design guidelines for the input filter for the power factor correction circuit. Conventional methods
of filter design may introduce an unwanted phase shift between the input voltage and current,
thereby degrading the power factor. The cause of this phase shift is explained and based upon it,
the design guidelines for the input filter are established. The FFT is used to more accurately define the input filter attenuation requirement. A comparision is made between power factor correction
circuit with controlled on-time and the power factor correction circuit with hysteresis control (with input filter for both of them) on the basis of their minimum weight. A regulated 100 W, 120 VAC input and 300 V output power factor correction circuit was implemented on a breadboard. Ridley's small signal switch model  for the power factor correction circuit with hysteresis control is successful1y
app1ied to this control scheme to close the loop.
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