Analysis of TSV proximity effects in planar MOSFETs and FinFETs
Ricardo Borges, Victor Moroz and Xiaopeng Xu, Synopsys, Mountain View, CA.
The impact of TSV-induced stresses on transistor performance are simulated, and a "keep-out-zone" is identified.
Over the last several years, the semiconductor industry has made significant strides in demonstrating the technical feasibility of 3D-IC integration in several different configurations, each with its own challenges and potential benefits. For example, memory cubes comprised of stacks of NAND FLASH or DRAM memory die, connected internally with through-silicon vias (TSVs), have already been manufactured by several companies. Memory cubes reduce the form factor of the memory product and improve performance because of shorter electrical interconnections. In another configuration, silicon interposer technology, also known as 2.5D-IC, mitigates a number of challenges that arise in die-stacked 3D-IC, while offering the advantage of shorter inter-die connections relative to traditional 2D packaging. The silicon interposer approach is expected to evolve into more complex and higher value implementations by moving the I/Os and the global power and ground mesh onto the interposer. However, silicon interposer technology does not offer the full benefits of form factor reduction and electrical performance advantages envisaged with die-stacked 3D-ICs, which provides the motivation for the industry to continue the research and development needed to overcome the technical and commercial barriers toward the commercialization of die-stacked 3D-ICs.
From the point of view of process development and transistor performance, the fabrication and integration of the TSVs within a 3D-IC system presents a number of challenges. These challenges, though manageable, need to be taken into account. Copper is the material of choice for the via conductor, due to its excellent electrical conductivity and pervasiveness in modern interconnect stacks. However, copper and silicon have very different coefficients of thermal expansion. Since the TSV fabrication steps involve thermal operations, the thermal mismatch of these materials induces stresses in the silicon surrounding the TSV. These stresses in turn alter the carrier mobility and on-current of the transistors fabricated in the proximity of the TSV, through the same piezoelectric effect in silicon which is responsible for boosting the transistor performance in strained-silicon technologies. This so-called TSV stress proximity effect has a range of several microns and can either produce enhancement or degradation of the current. In addition to the TSVs, the micro bumps used for inter-die connections and the solder bumps, used to attach the die stack to the bumps, also induce stresses in their proximity. Besides their impact on transistor performance, these induced stresses lead to structural reliability concerns such as cracking and delamination.
The impact of the TSV-induced stress on transistor performance is amenable to simulation with Technology CAD (TCAD) tools such as Synopsys' Sentaurus Interconnect. The data generated from Sentaurus Interconnect can then be used to identify the keep-out-zone (KOZ) surrounding the TSV. Typically the KOZ for an analog function is larger than the KOZ for a digital, with the distinction being a function of the variation tolerance for the transistor performance .
FIGURE 1 illustrates propagation of the TSV-induced stress into the surrounding wafer. Due to the large size of the TSV, 5??m in diameter and 20??m in depth, the stress propagates into silicon for distances of about 20??m. Considering linear drive current (Idlin) variability tolerance of 5% for digital circuits, the TSV-induced KOZ is 8??m.
|FIGURE 1. Stress map for the Sxx stress component around the copper TSV.|
Such a large KOZ means that a large part of the chip area is wasted, as it can not contain any transistors. For analog circuits, where the Idlin variation tolerance reduces to 0.5%, the KOZ is about 20??m, which further increases the wasted chip area.
|FIGURE 2. Canceling tensile TSV stress by a thin epitaxial compressive SiGe layer.|
One way to dramatically reduce the KOZ is to cancel tensile copper stress with a similarly sized compressive stress source. Taking into consideration that a thin epitaxial layer of SiGe can generate a sizable compressive stress and the maturity of SiGe epitaxy in the industry, a thin epitaxial SiGe layer that is grown inside the TSV hole before depositing the buffer oxide and the copper TSV, can provide the desirable large stress source with a small layout footprint. FIGURE 2 illustrates this idea.
|FIGURE 3. Comparing tensile TSV-induced stress in a conventional TSV (left) with the structure that contains compressive SiGe epi layer (right).|
Introduction of the SiGe layer dramatically reduces stress on the surface of Si wafer as can be seen on FIGURE 3.
Quantitatively, the tensile radial and the compressive tangential stress components along the Si surface for the two TSV process options are compared on Figure 4. The tangential stress is reduced to some extent, and the radial stress is reduced significantly.
|FIGURE 4. Distribution of the radial and tangential stress components along the Si surface vs distance from TSV.|
The stresses are converted into the TSV-induced mobility change, which is the dominant factor for the stress-induced Idlin variation. The conversion is performed using a sophisticated sub-band model rather than a simple linear piezo model. Figure 5 depicts hole mobility distributions for the planar p-MOSFET and p-FinFET.
|FIGURE 5. TSV-induced hole mobility change versus distance to TSV for the planar p-MOSFET (green) and for the p-FinFET (purple). TSV-only case is shown by the dashed lines, and the TSV+SiGe case is shown by solid lines.|
For the TSV-only case, the KOZ is 8??m for the p-MOSFET, reducing to 5??m for the p-FinFET. In contrast, for the TSV+SiGe case, the KOZ is zero for both the planar p-MOSFET and the p-FinFET.
|FIGURE 6. TSV-induced electron mobility change vs distance to TSV for the planar n-MOSFET (green) and for the n-FinFET (purple). TSV-only case is shown by the dashed lines, and the TSV+SiGe case is shown by solid lines.|
Similarly, FIGURE 6 shows what happens to the n-channel transistors. The planar n-MOSFET has zero KOZ, whereas the n-FinFET has 5??m KOZ.
Therefore, for the planar technology only the p-type transistor has a relatively large KOZ of 8??m. For the FinFET technology both transistor types have similar KOZs of 5??m. Similarly to the p-type transistor behavior, introduction of the SiGe epi layer eliminates the KOZ for both transistor types.
|FIGURE 7. Shear stress evolution with TSV process steps.|
|FIGURE 8. J-integral and safety factor for the crack with different insulators/barrier layers.|
The impact of the TSV-induced stress on structural reliability can also be analyzed with Sentaurus Interconnect. The data from such analysis is used to evaluate material and structure design options. The results shown in FIGURE 7 identify interfacial shear stress as the crack driving force. The crack energy release rate is evaluated using a method known as J integral. The crack energy release rate is compared in FIGURE 8 with the safety factor, which measures the difference between the material cohesive strength and the calculated J-integral. Although interface cracks between metal and oxide insulator show ~30% higher J-integral, the interfaces with oxide insulator possess larger safety factors than the interface with low-k insulator. The larger safety factor corresponds to stronger interfacial adhesion and strength. This analysis illustrates the greater adhesion and better reliability for metal/oxide interface as compared to the metal/low-k interface. For both insulation materials, TaN metal barrier shows slightly reduced J-integral as compared to a barrier with Cu-like material properties, thus improved interfacial reliability. These simulation findings are consistent with recent measurements .
|FIGURE 9. Stress evolution with TSV process steps.|
The above stress data is obtained using process simulation techniques which capture the stress evolution during TSV fabrication. FIGURE 9 illustrates the evolution of the normal stress component Sxx between two process steps. After the TSV formation step, the region with Sxx greater than 100 MPa extends to 5.4 micron away from TSV. After the micro-bump formation step, the region only extends to 3.3??m .
The simulations shown here are a good illustration of the value Sentaurus Interconnect offers in the process development and optimization of TSVs and other 3D-IC structures.
1. A. Mercha et al ,"Comprehensive Analysis of the Impact of Single and Arrays of Through Silicon Vias Induced Stress on High-k / Metal Gate CMOS Performance," Proceedings of International Electron Devices Meeting, 2010.
2. A. Karmarkar et al., "Material, Process and Geometry Effects on Through-Silicon Via Reliability and Isolation," MRS Proceedings, vol. 1249, 2010.
3. A. Karmarkar et al., "Copper Anisotropy Effects in Three-Dimensional Integrated Circuits Using Through-Silicon Vias," IEEE Trans. on Device and Materials Reliability, vol. 12, 2012.
RICARDO BORGES is senior Product Marketing Manager, TCAD group at Synopsys; XIAOPENG XU is R&D Manager, Silicon Engineering Group at Synopsys; and VICTOR MOROZ is a Synopsys Scientist. www.synopsys.com.
Solid State Technology | Volume 56 | Issue 3 | May 2013