US 4521866 A
Distributed arithmetic oversampling recursive digital filter comprising a recursive part constituted by q registers of a circulating nature, a non-recursive part of order p constituted by series registers, a memory divided into N memory blocks, a modulo N counter with α outputs, an adder--subtracter connected to the memory, an accumulator register, and a frequency clock fs. The filter is characterized in that the non-recursive part only comprises K series registers, K being an integer defined by the double inequality:
(K-1)N+2.sup.α -N≦p+P-1≦KN+2.sup.α -N
and in that it comprises multiplexers able to make these K registers recirculating N-1 times out of N and circulating 1 time out of N, these multiplexers being controlled by the outputs of the counter.
1. A distributed arithmetic oversampling recursive digital filter, comprising:
(a) a recursive part of order q comprising a parallel loading register having an output terminal and an input terminal, and q-1 series registers each of r cells, r being an integer connected in cascade;
(b) a non-recursive part of order p comprising series registers each of r cells each series register having one input terminal receiving input signals, said input signals being blockable P times out of N, wherein P and N are integers;
(c) a modulo N counter with α output terminals;
(d) a memory divided into N memory blocks, each of said memory blocks containing a set of calculated quantities characterizing the filtering to be carried out, said memory having α addressing input terminals corresponding to said blocks, said addressing input terminals being connected to said α outputs of said modulo N counter and said addressing input terminals within a block being connected to the output terminals of said series registers of said recursive and said non-recursive parts and said memory having an output terminal;
(e) an adder-subtracter having an input terminal connected to the output terminal of said memory and having an output terminal;
(f) an accumulator register having an input terminal connected to said output terminal of said adder-subtracter and having an output terminal connected to said input terminal of said parallel loading register and to said input terminal of said adder-subtracter;
(g) a clock having a first output terminal connected to said parallel loading register and said series registers, said first output terminal delivering a clock signal at a frequency rfs, and a second output terminal connected to said modulo N counter, said second output terminal delivering a clock signal at a frequency fs, said filter having an input terminal for receiving samples at a sampling frequency fE, said frequency fs of said clock being equal to NfE, said non-recursive part comprising at most K+1 series registers, K being an integer defined by the relationship (K-1) N+2.sup.α -N≦p+P-1<KN+2.sup.α -N, and wherein said filter further comprises a first plurality of first through Kth multiplexers each having first and second input terminals, a control input terminal and an output terminal, said output terminal of each said multiplexer being operatively connected to either said first or second input terminals according to a signal supplied to said control input signal, said second input terminal of each of said multiplexers being connected to the output terminal of an associated one of said series registers, said first input terminal of the jth multiplexer, j being an integer, 1<j≦K, being connected to the output terminal of that one of said series registers associated with the (j-1)-th multiplexer said first input terminal of said first multiplexer being connected to said input of said filter, and said control input terminal of said j-th multiplexer being controlled by said modulo N counter in such a way that when the content of said modulo N counter is at a maximum, said output terminal of said j-th multiplexer is operatively connected to said first input terminal of said j-th multiplexer, thereby making said series registers circulating, and when the content of said modulo N counter differs from its maximum output, said output terminal of said j-th multiplexer, is operatively connected to said second input terminal.
2. A filter according to claim 1, wherein N is not equal to 2 to the α power and said non-recursive part comprises a (K+1)th series register multiplexed with an output (αo) of said module N counter able to supply a non-significant bit for addressing said memory.
3. A filter according to claim 1, further comprising a second plurality of multiplexers and a module M counter, wherein said memory is preceeded by said second plurality of multiplexers each with M input terminals connected to said series registers, said multiplexers being controlled by said module M counter having output terminals which are connected to said addressing input terminals of said memory.
4. A filter according to claim 3, wherein M is not equal to 2 to the β power, β being an integer, and said second plurality of multiplexers are 2.sup.β -M in number, each of said multiplexers having two further input terminals, with one of said further input terminals being connected to one of said output terminals of said modulo M counter able to supply a non-significant bit for addressing said memory.
The present invention relates to a distributed arithmetic oversampling recursive digital filter. In general terms, it is used in the processing of signals and more particularly in telecommunications.
In coding-decoding-filtering systems of the PCM type (pulse code modulation) operating by interpolative coding and digital filtering, undersampling and oversampling digital filters are used. These are filters for which the sampling frequency of the input signals fE and that of the output signals fS are not identical. For undersampling we obtain fE >fS and for oversampling fE <fS.
FIG. 1 shows the organization of such systems. They comprise a coding chain and a decoding chain. The coding chain is constituted by an analog input EA, an RC type filter 1, a double integration delta-sigma coder 2 operating for example at 2048 kHz and supplying one-bit signals at 2048 kHz, a triangular undersampling digital filter 3 supplying 13-bit signals at 16 kHz, and undersampling digital filter 4 supplying 13-bit signals at 8 kHz, a circuit 5 for compressing the linear law into law A, whose digital output SN supplies 8-bit signals at 8 kHz. In a symmetrical manner, the decoding chain comprises a digital input EN, a circuit 6 for extending law A towards the linear law, an oversampling digital filter 7 operating at 32 kHz and supplying 13-bit signals at 32 kHz, a double integration delta-sigma decoder 8 operating at 2048 KHz and supplying 1-bit signals at this frequency and finally an RC type filter 9, whose output SA supplies the restored analog signal. Naturally, the digital values given are only of an exemplary nature.
French Patent Application 79 18862 filed on July 20, 1979 and entitled "Analog double integration delta-sigma coder and digital double integration delta-sigma decoder" in particular describes circuits 2 and 8.
The specification applicable to such systems appears in report G712 of the CCITT, orange book, Vol. III-2, entitled "Quality characteristics of PCM channels at voice frequencies".
Recently, projects have been launched dealing with systems of this type having to comply with much stricter specifications than that of the aforementioned report G712, particularly with regard to the filters on transmission and reception. In order to satisfy the templates appropriate for said filters, it is necessary to use the recursive digital filtering procedure in which the output signals of the filter are reinjected at the input thereof.
In the article by G. D. TATTERSALL and M. J. CAREY entitled "Digital bandlimiting filters for PCM transmission systems" published in the Journal "IEEE Transactions on Communications", Vol. COM-27, No. 1, January 1979, pp. 240-1246, the realization of such recursive filters by using a method commonly called "distributed arithmetic" is proposed.
The present invention again takes up the idea of the distributed arithmetic recursive filter, but provides an improvement in that by a careful adaptation of the circuits inherent in distributed arithmetic and circuits which permit oversampling, it is possible to bring about a by no means negligible saving as regards the means used (particularly the number of input registers) whilst retaining a very considerable flexibility of use.
Recursive digital filtering is conventionally characterized by an expression of the following form: ##EQU1## in which xn-k designates the input signals of rank n-k, yn-k output signals of rank n-k reinjected at the input of the filters, ak coefficients of the non-recursive part, whose order is p, and bk coefficients of the recursive part, whose order is q, n assuming whole values and characterizing the output signal.
Expression (1) is a particular case of a more general expression expressing a weighted sum which can be expressed by: ##EQU2##
A recursive digital filter comprises p+1 inputs receiving signals xk and q inputs receiving signals yk, i.e., in all, p+q+1 inputs. It also comprises an output supplying the sequence of signals yn.
The transfer function H(z) of such a filter expressed by means of the complex variable z is: ##EQU3##
The invention relates to a special digital processing method called "distributed arithmetic". The latter is described in U.S. Pat. No. 3,777,130 granted on Dec. 4, 1973, to A. CROISIER, D. J. ESTEBAN, M. E. LEVILION and V. RISO, entitled "Digital filter for PCM encoded signals" as well as in the article by A. PELED and B. LIU entitled "A new hardware realization of digital filters" published in the Journal "IEEE Trans. on ASSP," Vol. ASSP-22, pp.456-462, December 1974. In addition, the article by C. S. BURRUS entitled "Digital filter structures described by distributed arithmetic" published in the Journal "IEEE Trans. on Circuits and Systems", Vol. CAS-24, No. 12, December 1977, pp.674-680, provides a general approach to this question and describes a number of algorithms and structures which can be used. Reference can be made to these documents for details concerning the distributed arithmetic method, which is only described briefly hereinafter in order to facilitate the understanding of the invention.
The invention consists of forming a weighted sum of the signals expressed by the relation (2). It is assumed that uk are coded on r bits in code complement 2, but naturally other codes are also possible. The sign bit is designated uk (0) and the bits representing the absolute value of uk are designated uk (j), j being between 0 (exclusive) and r-1 (inclusive). It is then possible to write: ##EQU4## if -1<uk <1.
Then, after inverting the summations, it is possible to write v in the form: ##EQU5##
In this relation, the term uk (j) appearing in the expression in brackets is the bit of rank j of uk and this bit can only assume the two values 0 or 1. Thus, there are only two possible values, i.e., 0 or a1 for the first product u1 (j)a1. In the same way, the product u2 (j)a2 can only assume the two values 0 and a2. Thus, there are only four possible values for the sum of these two products, namely 0, a1, a2 or a1 +a2. Step by step, it is possible to see that there are finally two possible values for the sum: ##EQU6##
This sum, which will be designated wj (because it is dependent on the rank j in question), thus assumes any one of the two p values determined solely by the coefficients ak. Thus, the calculation of the weighted sum involves the calculation of the expression: ##EQU7## in which the wj can be predetermined as soon as a set of coefficients ak has been fixed.
Whichever of these 2P values is to be retained for forming wj, is defined by the group of p bits of rank j of the input signals, namely u1 (j), u2 (j) . . . up (j).
In a distributed arithmetic processing circuit the quantities wj are entered in a memory of 2p words of m bits, if m is the number of bits necessary for expressing these partial sums. The word corresponding to a particular wj is located in said memory at the address corresponding to the p bits of rank j of input signals uk.
The number m is determined on the basis of the constraints of the problem to be dealt with and can be deduced in two different ways, namely by truncating coefficients ak as in a conventional realization or by direct truncation of the quantities wj (but then processing is no longer strictly linear). The latter method is described in the article by R. LAGADEC and D. PELLONI entitled "A model for distributed arithmetic for filters with post-quantized look-up table" published in "National Telecommunications Conference," 1977, pp.29: 3-1 to 29: 3-6.
If the input signals uk are introduced into series registers with a low head weight and if at the output of the memory containing the precalculated wj is positioned an arithmetic unit comprising an adder-subtractor, an accumulator register with parallel inputs and parallel outputs which can be shifted, it is possible to obtain the weighted sum v in r elementary operations such as the reading of the memory at the address given by the p bits uk (j), addition of the content of the parallel-parallel accumulator register and the word contained in the memory at the indicated address (for j=0 it is necessary to subtract the content of the memory from the content of the register), and shifting the parallel-parallel accumulator register and the series input registers (corresponding to a division by 2 of the intermediate result).
The material organization of such a circuit is illustrated in FIG. 2. The represented circuit comprises p series registers 10/1, 10/2 . . . 10/p of r bits receiving the p input signals, a read-only memory 20 of 2p words of m bits, an adder-subtractor 30, a register 40 with parallel inputs and parallel outputs which can be shifted and a timing circuit or clock 50.
The memory has p inputs connected to the outputs of the p input registers and contains the 2p following quantities: ##EQU8## in which εk assumes the values 0 or 1, the address of each quantity being constituted by p bits applied to the p inputs.
With such means, in r clock strokes the equivalent of p multiplications and (p-1) additions is performed, the operations being performed in the following manner.
The quantities uk have a low head weight in registers 10/1 . . . 10/p. The first calculated quantity is: ##EQU9## then, after shifting the register 40, we calculate: 2-1 wr-1, wr-2, then the sum wr-2 +2-1 wr-1, then after a further shift,
2-1 (wr-2 +2-1 wr-1)=2-1 wr-2 +2-2 wr-1
and so on up to the n-th clock stroke, where it is necessary to carry out a subtraction corresponding to the sign bits uk (0). After this final stroke, the series registers 10/1 . . . 10/p must be shifted. It is also possible to truncate or round off the result v. To carry out the truncation, it is sufficient not to take account of the low weight bits as from a certain moment. For rounding off purposes, it is necessary to add, after truncating the results, a low half-weight.
These principles can be applied to the realization of a recursive digital filter. The operation to be performed is then in accordance with relation (1) and the corresponding circuit is that of FIG. 3. It comprises a non-recursive part constituted by p+1 series registers 10/0, 10/1 . . . 10/p receiving the signals xn, xn-1 . . . xn-p and a recursive part constituted by q registers 11/1, 11/2 . . . 11/q receiving the signals yn-1, yn-2 . . . yn-q register 11/1 having parallel loading and the other registers series loading. The output of registers 10/0 to 10/p-1 is connected to the input of the following register, in the same way as registers 11/1 to 11/q-1. The circuit then comprises a memory 20 with p+q+1 inputs connected to the output of the registers, said memory containing 2p+q+1 words of m bits, said words being the quantities: ##EQU10## in which εj are equal to 0 or 1, j passing from 1 to p+q+1.
Finally, the circuit comprises the aforementioned arithmetic processing members, namely an adder-subtractor 30, an accumulator register 40 with parallel inputs and parallel outputs, and a clock 50 ensuring the appropriate performance of the operations (shift of registers, loading of parallel registers, resetting of the accumulator at the end of the cycle).
There are two modifications compared with FIG. 2:
register 11/1 corresponding to yn-1 has parallel loading and the content of the parallel-parallel register 40 must be limited to r bits (by truncating or rounding off) and then, at the end of each cycle of calculations (r elementary operations), loaded into register yn-1 in a parallel manner,
the different series registers are interconnected.
The invention is based on a certain number of properties exhibited by recursive filters when using distributed arithmetic. These properties have can be summarized as follows.
In an oversampling recursive filter, the output signals yn are sampled at a frequency n times higher than the input signals xn. The calculation of the expression: ##EQU11## then has special features, because the samples xn-k will be zero (N-1) times out of N, whilst the samples yn-k will always be present. To further define this point, it should be noted that the running index n has the form n=tN+j, showing the multiplicity compared with N and in which the index j assumes all values between 0 (inclusive) and N-1 (inclusive).
When j=0, index n is a multiple of N. When k assumes all values between 0 and p, the first summation involves the coefficients a0, a1, a2 . . . ap and the samples xtN, xtN-1, xtN-2 . . . However, among these samples, only those whose rank is a whole multiple of N are not zero, namely xtN, xtN-N, xtN-2N . . . Thus, the first summation only involves certain of these products. For example, for N=4, the summation only contains the terms a0 xt4, a4 xt4-4 . . . In other words, everything takes place as if it were an ordinary filter with the set of coefficients a0, a4 . . . (whereby the index naturally may not exceed the order p of the non-recursive part).
For the following rank n we have j=1 and the samples involved in the first summation are, on this occasion, xtN+1, xtN, xtN-1, etc. On this occasion, it is the second sample xtN, the fifth, etc. which are not zero. The products to be taken into account are therefore on this occasion (and always in the case when N=4) a1 xt4, a5 xt4-N . . . Thus, the set of coefficients involved is a1, a5 . . .
For the following index n obtained for j=2 it is found in the same way that the set of coefficients involved is a2, a6 . . . Finally, for the index n obtained with j=3, the set of coefficients is a3, a7 . . .
For the following value of n we obtain j=0 again with t increased by one unit and the four aforementioned sets of coefficients (a0, a4), (a1, a5).
Table I gives the different input samples xn-k (the non-zero samples being underlined) in the case where the oversampling factor N is equal to 4 for the four values of j. This example corresponds to the case illustrated in FIG. 1, where the sampling frequencies are respectively equal to 32 kHz and 8 kHz at the output and input. In this table, the order p of the non-recursive part is equal to 6 (leading to a summation on 7 terms from k=0 to k=6). The sets of coefficients to be taken into consideration for each value of j (therefore, of n) are indicated at the bottom of each column. There are four different sets and in general terms N.
Moreover, in this example there is a maximum of 2 non-zero samples involved in a summation can k for a fixed n. Naturally, this number is dependent on the order p: the higher the order p is, number of samples which may not be zero increases. In the example of Table I, p=7 could be used without increasing the number of non-zero samples involved in the summation.
The order p is still between two successive multiples of N designated (K-1)N and KN with possible equality for the first. In the special case corresponding to p=6 and N=4, we consequently obtain K=2 (6 is between 1×4 and 2×4). It is easy to see that the number of samples to be taken into account in the summation of K of the non-recursive part is in general terms at most equal to K.
Thus, according to one of the features of the present invention, the number of series registers receiving the input signals and constituting the non-recursive part of order p is limited to K, K being defined (in the case where N=2.sup.α) by:
In the prior art, the number of registers used was taken as equal to p+1, as illustrated in FIG. 3.
According to another feature of the filter according to the invention, the N different sets of coefficients which are to be used in turn when rank n varies (in the example of Table I: (a0, a4), (a1, a5), (a2, a6), (a3)) are stored in N (in this case 4) blocks of the memory, said blocks having the same size and being addressed in turn in accordance with the value of N. This addressing is obtained by a modulo N counter which receives the control pulses at frequency fS and whose outputs are connected to the addressing inputs of the memory. When N is between 2.sup.α-1 (exclusive) and 2.sup.α (inclusive), the counter in question comprises α outputs and the memory comprises α addressing inputs of the N memory blocks. Moreover, said memory must comprise K inputs corresponding to the K series registers of the non-recursive part and also q inputs corresponding to the q registers of the ordinary recursive part. Thus, definitively the memory has α+K+q addressing inputs and a capacity of 2.sup.α+K+q words of m bits.
This second characteristic stresses the second saving of means resulting from the invention. In the prior art, the memory associated with a recursive part of order p and a non-recursive part of order q must have a capacity of 2p+q+1 words. Thus, with regard to the memory size, the gain resulting from the invention is in general:
In the most favorable case where p=KN-1 and N=2.sup.α, this gain is 2K(N-1) /N, this quantity exceeding 1 as soon as N≧2 and K>1.
In the most favorable case corresponding to p=(K-1)N and N=2.sup.α-1 -1, the gain is 2K(N-1)-N /N-1, this quantity exceeding 1 as soon as N≧2 and K≧2.
In the case where N is not a power of 2, expression (4) assumes a different form:
(K-1)N+2.sup.α -N≦P<KN+2.sup.α -N (5)
and when the signals are repeated P times out of N, at the input it assumes the following most general form:
(K-1)N+2.sup.α -N≦p+P-1<KN+2.sup.α -N (6)
Specifically, the invention can be defined in the following way. It relates to a distributed arithmetic oversampling recursive digital filter comprising a recursive part of order q constituted by a register with parallel loading and q-1 series registers, this q registers being of a circulating nature, i.e., connected in cascade; a non-recursive part of order p constituted by series registers; a memory divided into N memory blocks each containing a set of three calculated quantities characterizing the filtering to be carried out; a modulo N counter with α outputs, the memory having, on the one hand; α addressing inputs of the different blocks connected to the α outputs of the counter and, on the other hand, addressing inputs within a block connected to the outputs of the registers of the recursive and non-recursive parts; an adder-subtractor connected to the memory; an accumulator register whose input is connected to the adder-subtractor and to the output of the parallel loading register and to the adder-subtractor, the input signals of the non-recursive part being blockable P times out of N; a frequency clock fS controlling the output of the signals of the parallel register and their inputs in the recursive part and actuating the counter, the shift frequency of the registers being rfS if r is the length common to the various series registers, the frequency fS being equal to NfE in which N is an integer, fE the sampling frequency of the signals at the input of the filter and fS the input frequency of the filter, characterized in that the non-recursive part only comprises K series registers, K being an integer defined by the double inequality:
(K-1)N+2.sup.α -N≦p+P-1<KN+2.sup.α -N
and in that it comprises switching means able to make these K registers recirculating, i.e., looped onto themselves, N-1 times out of N and circulating, i.e., interconnected in cascade, time out of N, these switching means being controlled by the outputs of the counter.
Preferably, the switching means are constituted by K multiplexers with two signal inputs and one output and a control input connected to the counter.
Preferably, multiplexers can be inserted between the memory and the registers in order to reduce the size of the memory.
Preferably, when N is not a power of 2, i.e., when N differs from 2.sup.α, the invention provides a multiplexing of certain input registers with the outputs of the counter, making it possible to optimize the use of the memory.
The features and advantages of the invention will appear more clearly from the following description of illustrative and non-limitative embodiments. This description refers to the attached drawings, following those which have already been described and wherein:
FIG. 1 shows the coding chain and decoding chain of a coding-decoding-filtering system of the PCM type.
FIG. 2 shows a prior art embodiment of a distributed arithmetic processing circuit.
FIG. 3 shows a prior art embodiment of a recursive digital filter.
FIG. 4 shows an embodiment of an oversampling recursive filter according to the invention in the special case where the non-recursive part comprises two series registers (K=2) and the recursive part six series registers.
FIG. 5 shows a constructional variant of the above filter using multiplexers with two inputs located between the registers and the memory.
FIG. 6 another variant of the aforementioned filter using multiplexers with four inputs.
FIGS. 7 and 7a show a variant making it possible to optimize the filling of the memory when the oversampling factor is not a power of 2.
FIG. 8 shows another constructional variant of the above filter corresponding to the case when the oversampling factor N is not a power of 2 and when a supplementary register multiplexed with one of the outputs of the counter is used.
FIG. 4 shows an example of the filter according to the invention corresponding to the case where the order q of the recursive part is equal to 6 and where the order p of the non-recursive part is equal to 7 and in which N=4, said conditions leading to K=2 and α=2.
The filter comprises a recursive part constituted by a parallel loading register 11/1 and 5 series registers 11/2, 11/3 . . . 11/6, all of these registers being circulating, i.e., connected in cascade to one another, and a non-recursive part constituted by two series registers 10/1 and 10/2, each associated with a multiplexer having two inputs 12/1 and 12/2. The filter also comprises a memory 20 divided into four memory blocks of the same size, each containing a set of precalculated quantities characteristics of the filtering to be performed and a modulo 4 counter 25 with two outputs α0 and α1. Memory 20 has, on the one hand, two addressing inputs f0, f1 of four blocks, these inputs being connected to the two outputs of the counter and said on the other hand 8, addressing inputs e1, e2 . . . e8 of one word within a block, these inputs being connected to the outputs of 8 registers of the recursive and non-recursive parts. The filter also comprises in a known manner an adder-subtractor 30 and an accumulator register 40, whose output is connected to the parallel loading register 11/1. Finally, a clock 50 actuates the registers of the non-recursive and recursive parts at frequency rfS (in each case, r is the number of bits of the processed signal as well as counter 25 and the parallel loading of register 11/1 at frequency fS.
The switching means which are able to make the two registers 10/1 and 10/2 recirculating, i.e., looped on themselves three times out of four, and circulating, i.e., interconnected in cascade once out of four, are constituted by the two multiplexers 12/1 and 12/2 and by the NAND gate 13 with two inputs connected to the outputs α0 and α1 of counter 25. Each multiplexer has two signal inputs m1 and m2, an output m3 and a control input m4. The second input m2 of each multiplexer is connected to the output of the series register with which it is associated, the first input m1 being connected to the output of the preceding register, except in the case of the first 12/1, whose input is connected to a general input of the signals to be processed. The control input of the multiplexers is connected to the output of the NAND gate. It is therefore at state 0 only when the two outputs α0 and α1 are at 1 or in other words when the counter content is at its maximum (N-1 on counting from 0 to N-1, N on counting from 1 to N). The output m3 of each multiplexer is then connected to the first input m1, making the two registers 10/1 and 10/2 circulating. In the three other cases, the output of the NAND gate is at 1 and output m3 is connected to the second input m2, which makes the two registers recirculating.
In the illustrated embodiment, the capacity of the memory is 22+2+6 =210, i.e., 1024 words instead of 26+6+1 =213, i.e., 8192 words, as in the prior art, giving a gain of 8 on the memory size.
The arrangements described hereinbefore can easily be modified if the input signals are repeated (or blocked) at the filter input in accordance with a known procedure. If the signals at the input of a filter are repeated P times out of 10, the signal undergoes complementary filtering of the following transfer function: ##EQU12## which must be corrected in passband, but whose out-of-band attenuation (in particular, the zeros at f=kfS /P) can facilitate the synthesis of a filter satisfying a given template. The hitherto considered case corresponds to P=1 and consequently there is then no parasitic transfer function (G1 (f)=1).
On repeating the input samples P times out of N to find the power of the input signal at the output, it is necessary to multiply the input samples of N/P (or multiply the coefficients of the non-recursive part by N=P). When P=N (case known under the name "zero-order blocker"), this multiplicative factor is equal to 1 and the transfer function is: ##EQU13##
If the input signals are blocked, the number of xn-k to be taken into consideration in the summation on k increases and consequently so does the number of coefficients ak involved in each set. Table II gives the case envisaged in Table I when the signals are blocked 2 times out of 4. It can be seen that when j=0 (first column) the sample of rank k=3 is no longer zero, because it corresponds to xtN-4 repeated. Thus, the coefficients involved in the summation for j=0 are no longer a0 and a4 and are instead a0 and (a3 +a4). This also applies for j=1, where it is necessary to retain the set of coefficients (a0,a1), (a4 +a5), etc . . . ,
In general terms, it can be demonstrated that the N sets of coefficients to be taken into consideration on repeating the input signals P times out of N are as follows: ##EQU14##
On making P=1 the results of Table I are obtained and on making P=2 the results of Table II are obtained.
Thus, this modification affects the precalculated quantities to be introduced into memory 20. Moreover, the number K of registers to be used at the input is defined by the double inequality:
The aforementioned arrangements make it possible to reduce the memory size. This size can be further reduced on placing the multiplexers between the memory and the registers at the cost of a multiplication of the calculation frequency by M, if M is the multiplexing factor. Naturally, precautions must be taken so that when an input xn-k is addressed to the memory, that part of the memory containing the set of coefficients to be used is correctly addressed, which assumes that the α inputs of the memory corresponding to the addressing of the blocks receive the bits supplied by the modulo N counter.
The two possible solutions are either to only effect multiplexing on the (K+q) inputs of the memory connected to the registers or to repeat, if necessary, the α bits obtained at the output of the counter in such a way that for each xn-k selected by a multiplexer, the α bits of the counter are also selected.
FIG. 5 illustrates the case where 5 multiplexers 26/1 to 26/5 with M=2 inputs and one output are positioned between memory 20, on the one hand, and the registers and counter 25, on the other, in an embodiment corresponding to the case illustrated in FIG. 4. These multiplexers are controlled by a modulo 2 counter 27 working at the frequency 2rfS and which supplies a bit S equal to 0 or 1. Memory 20 then has 6 inputs, respectively, E1 to E6. When S is at 0, these inputs are respectively connected to α0, α1, 10/1, 10/2, 11/6 and 27. When S is at 1, they are connected to 11/5, 11/4, 11/3, 11/2, 11/1 and 27. Thus, the memory size is only 26 =64 words of m bits, i.e., a reduction by a factor of 16 compared with the case of FIG. 4.
FIG. 6 shows another example of the use of multiplexers, on this occasion with M=4 inputs. Three multiplexers 28/1, 28/2 and 28/3 are controlled by a modulo 4 counter 29 with two outputs β0 and β1. The memory comprises 2 inputs g0 and g1 connected to the outputs of the modulo 4 counter 29 and three inputs F1, F2, F3. The correspondence between the bits supplied by counter 29 and the elements to which the three inputs F1 to F3 are connected is as follows:
______________________________________ Input F1 Input F2 Input F3β0 β1 connected to connected to connected to______________________________________0 0 10/1 αo α10 1 10/2 αo α11 0 11/6 11/4 11/21 1 11/5 11/3 11/1______________________________________
Thus, the size of the memory is only 25 =32 words of M bits.
In the above description, the oversampling factor N is assumed to be a power of 2 (N=2.sup.α). In the case where this condition is not satisfied, the invention provides for a special arrangement making it possible to optimize the filling of the memory.
This variant of the invention is based on the following comments. The content of the counter varies between 0 and N-1 (a similar reasoning would apply if the content varied between 1 and N). The binary configuration supplied by the α outputs of the counter and corresponding to N, N+1, 2.sup.α -1 are consequently never reached. This means that certain configurations between 0 and N-1 will be entirely characterized by a number of bits strictly below α. In other words, among the α bits supplied by the counter some may not be significant, i.e., may have an influence on the memory addressing control.
For example, for N=3 counter 25 counts from 0 to 2. The binary configuration supplied by its outputs are therefore as follows:
______________________________________ α1 α0______________________________________ 0 0 0 1 1 0______________________________________
Binary configuration 11 is never produced because the counter content does not reach 3. Thus, if α1 is at 1, the least significant bit α0 lacks significance because in itself α1 =1 is sufficient for addressing one of the blocks of the memory, so that bit α0 is not involved in this addressing. Thus, one input of the memory can be freed when α1 =1 and this input can be allocated to data, so that a double sized memory block can be formed. This switching operation can be brought about by a multiplexer.
In general terms, it is possible to demonstrate that a memory with 2.sup.α+n words can be subdivided into memory blocks of 2n words and memory blocks of 2n+1 words, resulting from the equation:
2.sup.α+n =[N-(2.sup.α -N)]2n +(2.sup.α -N)2n+ 1
which can be directly demonstrated. In this equation, the term in square brackets proves the inequalities:
and the term in parentheses proves the inequality, 2.sup.α -N≧0 because 2.sup.α-1 <N≦2.sup.α. This means that the memory of 2.sup.α+n words can be subdivided into N-(2.sup.α -N) blocks of size 2n and into (2.sup.α -N) blocks of size 2n+1. Thus, in general terms, it is possible to free (2.sup.α -N) supplementary inputs.
Moreover, when N differs from 2.sup.α, the sequence of samples involved in the summation of the non-recursive part has special features. The following Table III gives, as an example, the sequence of non-zero samples xk in the case where N=3 and where the order of the non-recursive part is equal to 6. The zero samples are not mentioned for simplification purposes.
The number of non-zero xk involved in the summation on k is equal to 2, except on one occasion when it is equal to 3. It is easy to see that in general terms the number of non-zero xk is equal to k or K+1 in which K is defined by the aforementioned inequality:
(K-1)N+2.sup.α -N≦p<KN+2.sup.α -N (6)
which only differs from the inequality (9) by the introduction of the terms 2.sup.α -N, representing the variation between N and the power of 2 which is immediately obtained (if N=2.sup.α, this variation is zero and the first condition is satisfied). It can also be seen that the cases where the non-zero xk represent K+1 is precisely 2.sup.α -N. For example, for N=3, we obtain α=2, 2.sup.α -N=1, K=2 and there is a case where the number of inputs to be taken into consideration is equal to K+1=3.
Table IV gives in the same way the sequence of sample xk involved for N=5 and p=7. We then obtain α=3, 2.sup.α -N=3, K=1 and there are 2.sup.α -N=3 cases where the number of inputs to be taken into consideration is equal to K+1=2.
On comparing these considerations concerning the number of inputs to be taken into account with those concerning the nature of the binary configurations supplied by the counter, it is immediately apparent that the number of cases where it is necessary to use a supplementary register (K+1 registers instead of K) is precisely equal to the number of binary configurations supplied by the counter containing one non-significant bit. In Tables III and IV, the binary configuration supplied by the counter have been shown in the lower part in such a way that the configurations with non-significant bits (framed) face the cases where the number of non-zero xk is equal to K+1.
According to the invention, the memory is not then addressed at the same time with the bit which is liable to be non-significant and with the content of the supplementary register and is instead addressed with either the first (when it is significant) or the second (when the bit in question is not significant), making it possible to optimize the use of this memory.
This variant is illustrated in FIG. 7 in the case where N=3, α=2, and K=2, corresponding to Table III. From the point of view of the sampling frequencies, this is a question, for example, of the values 24 kHz and 8 kHz.
FIG. 7a shows the solution consisting of using three series registers 10/1, 10/2, 10/3 associated with their respective multiplexers 12/1, 12/2, 12/3 as described hereinbefore (the auxiliary means are not shown so as to simplify the drawings). These three registers are connected to three addressing inputs e7, e8 and e9 of memory 20. In addition, the two outputs α0 and α1 of counter 25 are connected to the two memory inputs f0 and f1. As stated hereinbefore, when α1 is at 1, α0 is not significant, so that then the memory 20 is poorly used. To obviate this, the variant as shown in FIG. 7b is used, which differs from that of FIG. 7a by the addition of a multiplexer 31 having two inputs 31/1 and 32/2, an output 31/3, and a control input 31/4. Input 31/1 is connected to the supplementary series register 10/3, input 31/2 to output α0 of counter 25, output 21/3 to an input (f0 /e9) of the memory, and control input 31/4 to the counter output α1. When α1 is at 1, it is input 31/1 which is connected to the output 31/3, and when α1 =0 input 31/2 is connected to the same output. Thus, input (f0 /e9) of the memory is connected either to the supplementary register 10/3 when bit α0 is not significant or to output α0 when the bit which it supplies is significant.
This arrangement can be used in the same way when the multiplexing factor M of the multiplexers (like 26/1 to 26/5 in FIG. 5 or 28/1 to 28/3 in FIG. 6) is not equal to a power of 2. In this case, those bits supplied by counter 29 which may not be significant are multiplexed with inputs connected to registers. For example, for multiplexers with 3 inputs (M=3) at the output of the modulo 3 counter a bit β0 is obtained, which is not significant when β1 =1 and output β0 can be multiplexed with one of the registers.
FIG. 8 illustrates the case where all these arrangements are combined in the case where M=N=3. Counters 25 and 29 are then modulo 3, and bits α0 and β0 are not significant when α1 and β1 are at 1. The multiplexers with three inputs are in reality obtained by two multiplexing stages with two inputs, respectively, 34/1, 34/2, 34/3 and 36/1, 36/2, 36/3. The multiplexer 33 with two inputs and one output makes it possible to multiplex the output of register 10/1 with the output β0 of counter 29, which is not significant when β1 =1. Thus, in the illustrated case we have p=6 and q=6, i.e. K=2. Thus, there are K+1=3 series registers 10/1, 10/2, 10/3 containing the inputs xk and six registers 11/1 to 11/6 containing the outputs yn. Register 10/3 is multiplexed by the least significant bit β0 of counter 25. The convention adopted for the multiplexers is that already used, namely that the upper input is connected to the output when the control signal is at 1. The use of multiplexers 34/1, 34/2, 34/3, 33, 36/1, 36/2, 36/3 makes it possible to reduce the memory size from 210 =1024 words of m bits to 25 =32 words of m bits. Without multiplexer 31 and without the multiplexers of the above list, the size of the memory would have been 211 =2048 words of m bits. The use of multiplexers multiplies by 3 the calculating frequency.
These arrangements can also be combined with the case where the inputs are blocked P times out of N. It is then necessary to modify the relation defining K to:
(K-1)N+2.sup.α -N≦p+P-1<KN+2.sup.α -N (6)
TABLE I______________________________________k j = 0 j = 1 j = 2 j = 3______________________________________ ##STR1## xtN+1 =0 xtN+2 =0 xtN+3 =0 1 xtN-1 =0 ##STR2## xtN+1 =0 xtN+2 =0 2 xtN-2 =0 xtN-1 =0 ##STR3## xtN+1 =0 3 xtN-3 =0 xtN-2 =0 xtN-1 0 ##STR4## 4 ##STR5## xtN-3 =0 xtN-2 =0 xtN-1 =0 5 xtN-5 =0 ##STR6## xtN-3 ≠0 xtN-2 =0 6? xtN-6 =0? xtN-5 =0? ##STR7##
TABLE II__________________________________________________________________________k j = 0 j = 1 j = 2 j = 3__________________________________________________________________________ ##STR8## xtN+2 = 0 xtN+3 = 0 1 xtN-1 = 0 ##STR9## ##STR10## xtN+2 = 0 2 xtN-2 = 0 xtN-1 = 0 ##STR11## ##STR12## 3 ##STR13## xtN-2 = 0 xtN-1 = 0 ##STR14## 4 ##STR15## ##STR16## xtN-2 = 0 xtN-1 = 0 5 xtN-5 = 0 ##STR17## ##STR18## xtN-2 = 0 6 xtN-6 = 0 xtN-5 = 0 ##STR19## ##STR20## coefficients a0,a3 + a4 (a0 + a1),(a4 + a5) (a1 + a2),(a5 + a6) (a2 + a3),a6__________________________________________________________________________
TABLE III______________________________________k j = 0 j = 1 j = 2______________________________________ ##STR21## 1 ##STR22## 2 ##STR23## 3 ##STR24## 4 ##STR25## 5 ##STR26## 6 ##STR27## Number of non- 3 2 2zero xk Binary ##STR28## 0 0 0 1configuration______________________________________
______________________________________k j = 0 j = 1 j = 2 j = 3 j = 4______________________________________ ##STR29## 1 ##STR30## 2 ##STR31## 3 ##STR32## 4 ##STR33## 5 ##STR34## 6 ##STR35## 7 ##STR36## Number of non- 2 2 2 1 1zero xk Binary config- uration of counter ##STR37## ##STR38## ##STR39## 0 0 0 0 0 1______________________________________