Aspar, Zulfakar and Khalil-Hani, Mohamed (2009) Modeling of a ladder logic processor for high performance programmable logic controller. In: Proceedings - 2009 3rd Asia International Conference on Modelling and Simulation, AMS 2009. Institute of Electrical and Electronics Engineers, New York, 572 -577. ISBN 978-076953648-4
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Official URL: http://dx.doi.org/10.1109/AMS.2009.83
Today, programmable logic controllers (PLCs) is the dominant technology deployed in control automation systems in modern factories. The main modeling method of the PLC is based on ladder logic diagrams (LLDs). However, as a system gets more complex, LLD implementations poses a stumbling block in the design of more complex and real-time PLCs. Consequently, in this paper, a novel architecture for a high performance LLD implementation, which we call the Ladder Logic Processor, is proposed. In the proposed architecture, each computation of the underlying ladder logic is performed at a fixed number of clock cycles per ladder rung, regardless of the number of steps involved. Notwithstanding, the technique maintains the existing LLD paradigm where every rung is processed sequentially. The LLDs are targeted for implementation in Field Programmable Gate Arrays (FPGAs). Experimental work performed to evaluate the performance of the proposed architecture shows promising results.
|Item Type:||Book Section|
|Additional Information:||ISBN: 978-076953648-4; 2009 3rd Asia International Conference on Modelling and Simulation, AMS 2009; Bandung, Bali; 25 May 2009 through 26 May 2009|
|Uncontrolled Keywords:||ladder logic diagram (LLD), processor, programmable logic controller (PLC)|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|Deposited By:||Liza Porijo|
|Deposited On:||07 Jul 2011 09:45|
|Last Modified:||07 Jul 2011 09:45|
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