Issue No.01 - January (1994 vol.43)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.250617
<p>An optimization technique for the design of two types of multiple-valued PLAs is described. In a type-I PLA, the multiple-valued function is realized directly, whereas in a type-II PLA, output encoding is used to encode the binary output of the PLA. In both types, multiple function literal circuits are used for the purpose of minimization. It is shown that the proposed technique leads to a considerably reduced size of PLA when compared to the earlier techniques.</p>
logic arrays; minimisation; encoding; adders; many-valued logics; network synthesis; optimization technique; multiple valued PLA design; output encoding; binary output; multiple function literal circuits; minimization; PLA size; programmable logic arrays; adder; multiple valued logic.
K.V. Asari, C. Eswaran, "An Optimization Technique for the Design of Multiple Valued PLA's", IEEE Transactions on Computers, vol.43, no. 1, pp. 118-122, January 1994, doi:10.1109/12.250617