Cadence Designs Systems Inc. unveiled software Wednesday (Oct. 8) it said will improve semiconductor manufacturing at the 22-nm design node.
Working with Tessera Technologies Inc., Cadence (San Jose, Calif.) said it has integrated a new capability called custom lithographic source illumination into its source mask optimization software. The technology also was integrated into Cadence's resolution enhancement technology (RET) design flow.
Chip manufacturing at 22 nm is not expected to begin before 2011. At 22-nm and lower manufacturing nodes, existing RETs will not provide required IC pattern fidelity. Cadence claims its source mask optimization technology delivers more accurate lithography to provide chip pattern fidelity and increased manufacturing yields.
The company further claims the new capability enhances lithographic souce illumination based on the ability to print 2-D layout structures "through a process window," rather than only through the critical dimensions of a design.
"We're going beyond" design-for-manufacturing," Dipu Pramanik, vice president of silicon signoff and optimization at Cadence, said in a statement announcing the design capability.