By Tiernan Ray
The key is volume of chip die Intel could squeeze out of each wafer it processes:
In 2008, when INTC introduced ATOM at a $40-45 price point versus its then ASP of $100, most investors assumed that a lower price point would equate to lower profitability; however, INTC achieved a 64.7% GM in 4Q09, its highest GM ever at the time (and currently the third highest), when ATOM peaked at 16% of unit mix. Why? ATOM has a smaller die, implying more die per wafer and total revenue per wafer very similar to the core family – also note that ATOM was at least partially incremental implying better fixed cost absorption. Semiconductor economics depend upon several factors including: (1) cost per wafer defined by fixed capital costs (33%), labor and overhead (33%) and material costs (33%), (2) die size which drives gross die per wafer, (3) yields which drive good die per wafer, and (4) ASP per die which in combination with (3) drives revenue/wafer. It is our contention that IFS should be able to provide smaller die, better yields and support premium price points which in combination would support better economics than feared. It is important to note that INTC’s higher cost per wafer is not a structural impediment/issue, rather it is a conscious choice by the Company to optimize transistor performance and more importantly to maximize yield – we suspect INTC’s “at volume” yield is 90%+, significantly higher than a foundry “at volume” yield of 40- 60%. Structurally higher yield at INTC is a key consideration when examining the economics of a foundry model […] Our estimates for INTC’s current leading edge revenue per wafer are based on our assumptions around die sizes, yields and ASPs – note that our die size and ASP estimates include chipsets – and our estimates for INTC’s current cost per wafer is based on our assumptions around GMs. We then look at different revenue/wafer scenarios for IFS by flexing: (1) die size, (2) yields, and (3) ASPs – we keep wafer costs relatively constant and consistent with Core costs. Operating profitability is derived by applying a TSMC/UMC-like operating expense-to-sales ratio.
A key assumption, notes Pitzer, is the wafer cost Intel would incur:
If AAPL revenue is used as “fab filler” (not likely in our opinion) or the capacity were funded by AAPL, then cost/wafer could be 30-40% lower. It’s also worth noting that our analysis does not adjust for (1) potentially lower cost on foundry wafers – INTC could cut down on costs per wafer by reducing yield requirements, (2) better fixed cost absorption – recall 33% of costs are related to labor and non-depreciation overhead or (3) potentially higher wafer costs at more complex technologies.
Pitzer’s note is much more positive than, for example, one put out on Wednesday by Goldman Sachs‘s James Covello, which warned that foundry revenue could be much less profitable for Intel.
Intel shears today are up 6 cents at $20.55.