US 20110050472 A1
A delta-sigma analog-to-digital converter (ADC) having a serialized quantizer output has a data rate greater than a quantization rate of the delta-sigma modulator, but less than a bit rate determined by the product of the number of bits required to represent the input to a feedback digital-to-analog converter and the quantization rate. Additional information can be encoded in the serial bit stream by selection among redundant codes based on the value of the additional information. The serial bit stream may encode differences between successive quantizer output samples and the additional information may include the absolute value of the quantizer output, synchronization information and/or framing information for distinguishing data corresponding to multiple ADC input channels.
1. An analog-to-digital converter, comprising:
a noise-shaping filter having an input for receiving an analog signal to be converted to a digital value;
a quantizer having an input coupled to an output of the noise-shaping filter for generating quantized output values at a quantization rate of the quantizer, wherein the quantized output values are from a set of more than two output values;
a digital-to-analog converter having an input for receiving the quantized output values and having an output coupled to an input of the noise-shaping filter for providing a feedback signal, wherein the noise-shaping filter, the quantizer and the digital-to-analog converter form a delta-sigma modulator loop; and
a serial data circuit having an input coupled to an output of the quantizer for generating a serial bit stream representing the quantized output values, wherein a ratio of the bit rate of the serial bit stream to the quantization rate of the quantizer is greater than unity but less than a minimum number of bits required to represent the input of the digital-to-analog converter.
2. The analog-to-digital converter of
3. The analog-to-digital converter of
4. The analog-to-digital converter of
5. The analog-to-digital converter of
6. The analog-to-digital converter of
7. The analog-to-digital converter of
8. The analog-to-digital converter of
9. The analog-to-digital converter of
10. The analog-to-digital converter of
a transformer having a first winding coupled to an output of the serial data circuit; and
a decoder circuit having an input coupled to a second winding of the transformer, wherein the decoder circuit decodes the serial bit stream to obtain the quantized output values.
11. The analog-to-digital converter of
12. The analog-to-digital converter of
13. The analog-to-digital converter of
14. An analog-to-digital converter, comprising:
a quantizer for generating a digital output from an analog input signal; and
an output encoder for generating a data output of the analog-to-digital converter from the digital output of the quantizer, wherein the data output represents changes in the digital output as a sequence of codes in the data output, and wherein the sequence of codes extends over a set of codes including at least one redundant code, whereby one value of the changes in the digital output is represented by at least two codes, and wherein a pattern of the at least two codes in the data output represents an indication of an absolute level of the digital output.
15. A decoder circuit for receiving and decoding a serial bit stream representing output values of an analog-to-digital conversion, the decoder circuit comprising:
a receiver for receiving the serial bit stream, wherein the serial bit stream encodes the output values of the analog-to-digital conversion along with additional information by using redundant codes to express at least one output level of the analog-to-digital conversion; and
a decoder for decoding the serial bit stream to obtain the output values, wherein the decoder checks a sequence of codes within the serial bit stream for error by examining a sequence of the redundant codes.
16. The decoder circuit of
17. The decoder circuit of
18. A method of operating an analog-to-digital converter, comprising:
filtering an input and feedback signals with an analog loop filter;
quantizing a result of the filtering to provide quantized output values;
providing feedback proportional to a result of the quantizing as an input to the filtering;
converting a result of the quantizing to a serial bit stream, wherein a ratio of the bit rate of the serial bit stream to a quantization rate of the quantizing is greater than unity but less than a minimum number of bits required to represent a set of possible values for the feedback provided by the providing.
18. The method of
20. The method of
21. The method of
22. The method of
23. The method of
second filtering second input and second feedback signals with another analog loop filter;
second quantizing a result of the second filtering to provide second quantized output values; and
providing another feedback signal proportional to a result of the second quantizing to as an input to the second filtering, and wherein the converting further encodes a result of the second quantizing along with the result of the first quantizing, and wherein the converting further encodes the additional information including a framing indication for indicating whether a given value in the serial bit stream is one of the result of the first quantizing or the result of the second quantizing.
24. The method of
25. The method of
26. The method of
27. The method of
coupling the serial bit stream through a transformer through a first winding of the transformer; and
decoding the serial bit stream from a signal received from a second winding of the transformer to obtain the quantized output values.
28. The method of
29. The method of
1. Field of the Invention
The present invention relates generally to analog-to-digital converters, and more specifically, to an analog-to-digital converter having a serialized quantizer output.
2. Background of the Invention
Delta-sigma analog-to-digital converters (ADCs) are in widespread use in consumer and industrial devices. Delta-sigma ADCs provide a very linear response and control of quantization noise. The relative simplicity of the architecture and the ability to finely control the quantization noise makes delta-sigma converter implementations very desirable. The delta-sigma modulator based analog-to-digital converter includes a loop filter that receives an input signal and a quantizer that converts the output of the loop filter to a digital representation. Feedback from the quantizer output is applied to the loop filter in feedback modulator topologies or is summed with the output of the loop filter in feed-forward modulator topologies to provide a closed-loop that causes the time-average value of the output of the quantizer to accurately represent the value of the modulator input signal. The loop filter provides shaping of the quantization noise at the output of the quantizer in response to the feedback signal applied from the quantizer to the loop filter. The feedback provided from the quantizer is typically generated by a coarse feedback DAC that receives the digital output of the quantizer and generates an analog value that is provided to the loop filter or the output summer.
The output of the delta-sigma ADC is generally the output of a decimation filter that is provided at a rate substantially lower than the quantization rate of the quantizer. The output decimated samples are usually provided in either a parallel or serial form. However, the input to the decimation filter, which is the output of the quantizer, is typically provided in a parallel form if the output of the quantizer has more than two levels. Since a typical quantizer may have, for example, seventeen levels, a serial bit stream at five times the quantization rate would be required to transfer the quantizer output using a typical serial interface. In some applications, for example in isolated circuits such as transformer-coupled or optically-isolated circuits, it is desirable to couple the quantizer output using a serial interface in order to transfer the data from the quantizer output to the serial interface over a single channel. However, the increased data rate required in an ADC having a number of quantizer levels greater than two comes with increased power requirements, increased component bandwidth requirements and higher generated levels of electromagnetic interference (EMI) due to the higher bit rates required.
Therefore, it would be desirable to provide a delta sigma ADC that has a serialized quantizer output without requiring a high serial data rate.
The above stated objective of providing a delta sigma ADC with a serialized quantizer output is achieved in an analog-to-digital converter circuit and its method of operation.
The analog-to-digital converter includes a loop filter that provides an output to a quantizer input. The output of the quantizer provides the output of a delta-sigma modulator and is converted using a digital-to-analog converter to provide a feedback signal to the loop filter. The output of the quantizer is coupled to a serial data circuit that serializes the output of the quantizer to produce a serial bit stream at a data rate that is higher than the quantization rate, but lower than the quantization rate multiplied by the number of bits required to represent the input to the digital-to-analog converter.
Additional information may be encoded in the selection among redundant codes provided in the serial bit stream and the output of the quantizer may be encoded as differences so that as few as two bits are required to represent the quantizer output, while providing two redundant codes that can be used to encode other information such as synchronization information, framing information (especially among multiple ADC channels) and an absolute value of the output of the ADC.
In a particular embodiment, the output of the quantizer may be provided to a digital integrator. A difference circuit generates a difference between a present value and a previous value if the output of the digital integrator provides a feedback signal to the loop filter, which may include a summing circuit for combining the feedback with a plurality of feed-forward signals provided from the loop filter. The output of the difference circuit is encoded in the serial bit stream, and the output of the digital integrator is then encoded in the selection of the redundant codes at a lower rate in order to provide the absolute output value of the ADC at the remote end of a serial interface that receives the serial bit stream.
The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.
The present invention encompasses a delta-sigma analog-to-digital converter (ADC) method and apparatus having a serialized quantizer output. The serial output provides for cost effective and simple isolation through a transformer, optical coupler, or capacitive coupling mechanism. The serial data output of the ADC of the present invention has a bit rate that is greater than the quantization rate, but less than a rate determined by the number of bits required to represent the output of the quantizer multiplied by the quantization rate. In other words, the ratio of the bit rate of the ADC output to the quantization rate is greater than unity, but less than the number of bits required to represent the output of the quantizer. Additional information such as synchronization for the samples and synchronization of a rotating pattern of multiple channels of data can be encoded in the bit stream by selecting among multiple redundant codes for one or more values of the quantizer output, which may be delta (difference) encoded. If the quantizer output is delta encoded, the additional information may include an absolute value of the quantizer output, so that the startup value can be determined from the absolute value and subsequent changes received at the remote side of the interface and any error due to a missed or erroneous transmission can be corrected.
Referring now to
The transfer rate of additional information info is dependent on the pattern of values at the output of quantizer 13, since additional information info can only be transmitted when the value of the output of quantizer 13 is 0 in the illustrated encoding scheme, since 0 is the only value for which selection between multiple redundant codes can be made in order to encode the extra information. However, the transfer rate is sufficient for certain types of information, such as synchronization information and error correcting information that does not require a high transmission rate. Further, depending on the characteristics of input signal in and the response of loop filter 12, the quantizer output value(s) chosen for assignment to redundant codes can be a more frequent value than other values. For example, in the embodiment illustrated in Table I, the zero code may be generated by more than 50% of samples, statistically, yielding an average bit rate of additional information info of at least ⅙ of the bit rate of the serial bit stream transmitted through transformer T1.
Referring now to
Limiter 21 receives the output of quantizer 13 and limits changes in the output codes generated by quantizer 13, so that the difference between successive quantizer values can only be an increment (+1), a decrement (−1), or no change (0). A difference circuit, formed by unit delay 22 and subtractor 23 provides a serial bitstream diff, that encodes differences between the quantizer output values, and serial data circuit 14A encodes the output of subtractor 23 in a two-bit serial bitstream as depicted in Table II below.
Referring now to
In order to account for the action of digital integrator 40, a portion of the feedback signal applied to the loop filter is differentiated by a differencing circuit. In the depicted embodiment, the differencing circuit is provided by a differentiator 39 that receives an input from a DAC 36 and applied to a summer 33C that provides the input to the final integrator stage 31C. DAC 36 receives the output of storage device 44. Another feedback path that is necessary for the converter to provide the correct DC and low-frequency output from the converter corresponding to the voltage of signal IN, is provided directly from DAC 36.
Referring now to
Another encoding level as between the bits of additional information info, will generally be employed in order to synchronize the transmission of the additional information. For example, a marker can be generated by a succession of the same state of additional information info, such as two successive ones followed by a zero: 110. Occurrence of the marker can provide synchronization information, and the codes between the markers can provide other information such as the absolute value abs of the quantizer output and channel framing information. For example if a sequence such as 1100011001100101101100 . . . is generated in additional information info and is interpreted as M00M0M0010M0M00, where M is a marker, if the number of bits between each marker M is limited to five (or the number of codes starting with a zero is limited to 6 between successive 11 occurrences), then 18 codes are available, which can for example, encode 17 absolute quantizer levels and one extra code for indicating that other information follows in a next code, such as a channel number.
Table III illustrates an encoding scheme in which the coding scheme stated above is followed. The leading zero and the trailing 11 are included in the codes, so that each code includes a start bit 0 and a stop marker 11. The unique (data-bearing) portion of each code is shown in bold. The codes shown in Table III are codes transmitted via the selection among redundant codes for the quantizer output difference information, such as codes 01 and 10 of Table II. Therefore, the Codes shown in column 1 of Table III are not bit sequences in serial bitstream serdat, but rather occurrences of the different redundant codes that indicate 0 and 1. Further, as described above, the rate of transmission of the bits forming the codes illustrated in Table III varies with the occurrence of the codes in the quantizer difference information for which redundant code selection is possible. Therefore, the data rate of the information transmitted via the codes of Table III varies not only with the length of the code, but with the pattern of the difference information being generated by the quantizer at any given time. However, a constant average bit rate for the bits of the codes shown in Table III can be assumed, as the statistical likelihood of the difference values assigned to redundant codes should be relatively constant under normal operating conditions of the ADC.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.