Advances in co-design and simulation have created more opportunities for first-pass success because now developers can simulate the entire system on a host PC prior to tape-out. Synopsys offers a variety of simulation products encompassing the entire scope from automatically generated cycle accurate simulators to fast, functional instruction set simulators. To enable SW development in a full system-on-chip (SoC) context, Synopsys provides a methodology package that allows virtualization of the software visible SoC components, such as peripheral registers, memories and interrupts.
Although simulation is a proven tool for decreasing time-to-market, it is important to match one's needs with the strengths of the various simulation technologies available. Synopsys offers a broad suite of simulation products that enable hardware / software co-design prior to silicon being available. Each product differs in its intended use model, speed, accuracy, and debug views.
DesignWare® MetaWare® ISS is provided by default within the DesignWare Metaware SW development toolkit. It enables easy development, test and debug of small SW components. The DesignWare MetaWare ISS provides additional capabilities that are not available on hardware, such as:
Within the DesignWare Metaware ISS a cycle estimation component (CES) can be activated. It allows estimation of machine cycles when executing programs. The CES also includes a cache thrash analysis routine to point out cache thrashing. Simulation performance of the Metaware ISS goes up to ~2 MIPS.
DesignWare ARC® xISS Turbo Fast ISS for full application development enables fast development, software test and debug. DesignWare ARC xISS and DesignWare ARC xISS Turbo are high-performance instruction-set level simulations that increase software development productivity at every stage of ARC-Based product development. DesignWare ARC xISS Turbo uses advanced Just-in-Time Compiler technology to produce 200+ MIPS (millions of instructions per second) performance, while DesignWare ARC xISS provides affordable yet advanced ISS capability at ~20 MIPS performance.
With the addition of DesignWare ARC xCAM, the DesignWare ARChitect™ IP Configurator can automatically generate cycle accurate models of any customized DesignWare ARC IP, allowing code to be tuned on the exact hardware configuration being considered. Executing at between 40kHz to 60kHz, DesignWare ARC xCAM models are available within minutes of a configuration being finalized, enabling a genuinely iterative design approach. DesignWare ARC xCAM models provide detailed cycle and "programmer's view" information for profiling and they easily import into SystemC co-development tools.
- Set hardware watchpoints on memory and registers
- Specify memory size and location
- Stop execution on loads of a value
- Trace instructions
- View the most recently executed instructions
Reduce Time-to-Market and Minimize Risk
Differentiate to Keep Competitive Edge
- Parallelize hardware and software development
- Quickly iterate through multiple system configurations to determine the best options for your requirements
- Increase the number of develop/debug/optimize cycles to ensure your product meets your requirements
- Add more features or respond to late feature requests with the schedule time gained
- Prototype earlier in the development cycle to influence prospects and customers
- Make your solution easier for your customers to integrate