One of the main challenges at smaller technology nodes is dealing with increasing variability that could lead to delayed design schedule and lost performance. For advanced nodes, variability is associated with design modes, power states, process conditions and manufacturing steps. Designers are forced to balance multiple operational modes and design corners with aggressive performance and power targets. In order to achieve optimal quality of results (QoR), it is essential to concurrently analyze and optimize across the different cost functions such as timing, signal integrity (SI), and power.
Since the introduction of 40nm, the number of operational modes and process corners has increased rapidly. This is mainly due to the growing complexity of designs and increasing process variations at smaller technology nodes. A mode/corner scenario is any combination of cell and interconnects variations, design constraints, library and operational modes that need to be considered during physical design. There is an increasing need to reduce guard banding in the face of increasing process variability to ensure that SoCs can meet their power as well as their timing and SI targets. The variability problem has gotten even worse at 20nm and 16nm due to the effect of double patterning and the introduction of FinFETs.
Dispense with tradition
The traditional solutions were architected to address a different set of problems and are not equipped to address the variability challenge. From a multiple-corner and mode context, the critical handicap of the last-generation tools is the inability to handle more than two mode/corner scenarios at a given time. Specifically, the ‘timing graph’, which is the most fundamental data structure in any implementation system, was generated from one mode and one setup/hold corner analysis. All place and route engines, including timing analysis, are hence limited by the information stored in this data structure. As it is very difficult to replace or retrofit this basic architectural limitation, it is nearly impossible for the traditional solutions to efficiently address the new multi-corner multi-mode design (MCMM) closure problems.
What is needed is the ability to capture the circuit behavior for any number of modes and corners dynamically and without impacting memory requirements and runtimes. In addition, all the place and route engines should concurrently analyze and optimize the various design metrics including timing, power, and SI across all modes and corners. The solution should scale efficiently for increasing design sizes and the high number of mode/corner combinations
The answer is to move away from the traditional sequential approach to concurrently analysis and optimization. An effective place and route implementation system should deliver a comprehensive set of capabilities to help designers close timing, power, and SI across any number of modes and corners. A new timing-analysis architecture that can concurrently address multiple modes and corners is critical and essential. A variability-aware routing approach that optimizes for double patterning and other DFM metrics during place and route is also essential to address the manufacturing challenges.