Image text transcribed for accessibility: Using a 4-bit synchronous counter with parallel load (see below for inputs and outputs) and a minimum number of additional gates as needed, construct a counter that counts from 0101 through 1010. Repeat for a count from 0101 through 1000. For a 4-bit ring counter, starting from an initial state of 1001. list the sequence of states of the four flip-flops after each shift. Beginning in state 1001, how many states are there in the count sequence of an n- bit ring counter? For a 4-bit Johnson counter, starting from an initial state of 1001. list the sequence of states of the four flip-flops after each shift. Draw the circuit corresponding to the Verilog module below. For the circuit below, calculate the minimum period of the clock signal, T and determine whether any hold time violations occur in the circuit. Assume for a D flip-flop that t = 0.6 ns. i = 0.4 ns. 0.8 ns t 1.0 ns. Assume that the delay through any logic gate can be calculated as 1 + 0.1k ns., where k is the number of inputs to the gate.