Image text transcribed for accessibility: Simulate the following gates in VHDL. It is advised that you keep all your .vhd files in one project for future references. It is also advised to use the same project for all your computer assignments as many of the previous codes will be used in the future assignments. OR gate Inverter with gate delay of Ins. NAND gate with gate delay of 2ns. Implement a D flip-flop shown in Figure 1., using the components designed in 2. and 3.