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The analysis regarding the impact of the single-step power control (SSPC) scheme on the system performance such as bit error rate, packet error rate and queueing variation is hard to access. In this work, we propose an approach to analyze that impact when being in finite state Markov channel (FSMC). To achieve the understanding of the relationship between SSPC, FSMC, and the queueing variation, power control error (PCE), error rate, and PDF of queueing length are first calculated. PCE variation is modelled, which then benefits the evaluation of packet error rate (PER) and bit error rate (BER). Furthermore, based on these results, a queueing model is proposed to describe the variation of queueing length, which is an embedded Markov chain. The proposed queueing model can help determine the optimal queueing buffer size and the optimal target SNR for a specific overflow probability under. Simulation results have shown the validation of the proposed PCE variation model and queueing variation model.