Embedded Systems: Two Routes Lead to Software Defined Radio
Two Routes Lead to Software Defined Radio
by Jon Titus, Senior Technical Editor
A bit of C code that runs on a microprocessor does not create a software-defined radio (SDR). Most SDRs use a traditional signal-sampling technique, followed by much software massaging of data. But semiconductor companies can now put more of the analog signal-handling elements on a chip. This column provides an update on both techniques.
In a typical SDR, an analog tuner translates an RF signal down to an intermediate frequency (IF), usually below about 200 MHz. Then an ADC digitizes the IF signal and a digital down converter further translates the digital signal down to baseband. Depending on the type of signal and modulation scheme, suitable signal processing operations extract the original transmitted information.
"For example, in a UHF SDR, an analog tuner might translate a 10-MHz-wide signal centered at 3 GHz down to a 70-MHz IF signal where it’s easily sampled with a high-resolution ADC," explained Rodger Hosking, VP at Pentek, a manufacturer of board-level DSP and SDR products.
"Now, the latest FPGAs from Xilinx, for example, supply up to 640 DSP engines that are replacing the dedicated ASICs and DSPs previously required for digital down conversion and demodulation," said Hosking. FPGAs also provide flexibility. "Both board vendors and customers can reconfigure FPGAs so one SDR board can handle many different types of communications such as wideband code-division multiple access (CDMA) or Universal Mobile Telecommunications System (UMTS) services, for example."
After down converting a signal to an IF frequency--typically 21.4, 70, 140 or 160 MHz--developers can take advantage of undersampling to digitize these signals. "Traditionally, you sample a signal at more than twice its frequency," said Hosking. "But the Nyquist Theorem really says you must sample at twice the bandwidth. So, a 70 MHz signal with a 10 MHz bandwidth can be sampled at 100 MHz. Of course, you must select the proper sampling rate for the band of frequencies that you want."
Recent SDR modules offer 200 MHz ADCs to handle wider signal bandwidths and deliver 16 bits of resolution. "You often need to find a weak signal in the presence of a strong signal," said Hosking. "Since you must limit the analog signal gain so the large signal doesn’t overload the ADC, the more ADC bits you have, the more easily you can resolve the smaller signal."
Ultimately, engineers must implement SDR algorithms. "We always start by modeling and testing signal-processing algorithms in MATLAB. New high-level block diagram compilers can produce FPGA bit streams that work reasonably well for prototypes or proof of concept," noted Hosking. "However, for final production FPGA code, our FPGA experts create VHDL modules for each block, and carefully optimize them for the best performance, dynamic range, speed and use of resources."Continued on next page...