US 3965442 A
An oscillator which includes a complementary symmetry metal oxide semiconductor (CMOS) inverter, a crystal connected between the input and output terminals of the inverter, and input and output capacitors connected to these input and output terminals, respectively. Low power dissipation is achieved by making the input capacitance of much higher value than the output capacitance. Frequency stability is obtained by incorporating a voltage controlled capacitor in the circuit which, in response to a change in operating voltage, changes value in a sense to compensate for the tendency of the oscillator frequency to change.
1. An oscillator comprising, in combination:
two operating voltage terminals,
two field effect transistors of complementary conductivity types, each having a conduction path and a control electrode, said conduction paths connected in series between said operating voltage terminals, said two control electrodes connected to an input terminal, and the connection between said two conduction paths serving as an output terminal;
a regenerative feedback loop comprising a crystal connected between said output and input terminals;
a relatively small value of capacitance connected between said output terminal and a point of reference potential; and
a value of capacitance at least 10 times larger than said small value of capacitance connected between said input terminal and said point of reference potential.
2. An oscillator as set forth in claim 1, further including a voltage controlled capacitor in said regenerative feedback loop of a value such that when the operating voltage changes and tends to change the oscillator frequency in one sense, the capacitance changes in a sense and amount to change the oscillator frequency substantially the same amount in the opposite sense.
3. An oscillator as set forth in claim 2, wherein said voltage controlled capacitor comprises the distributed capacitance between the control electrode and the conduction path of each transistor.
A crystal controlled oscillator employing complementary symmetry metal oxide semiconductor (CMOS) devices often is employed as the time base for an electronic time-piece. It is desirable in this application to use AT cut crystals designed to operate at a frequency above 1MHz (a commonly used value is roughly 4 MHz). The reason is that such crystals are much less expensive than lower frequency crystals and also more stable (have higher Q's) than the lower frequency crystals. Where the timepiece is small (a wristwatch, for example) and the power source (a battery) is of a limited capacity, the power dissipation of the oscillator must be very low, sufficiently so to obtain a reasonable life expectancy -- a year or so, from the battery. It is also, of course, important that the oscillator frequency be stable over a reasonable range of battery voltage. It is known that such stability may be achieved by employing a relatively large output capacitance connected between the output terminal of the oscillator and ground.
The present invention resides, in part, in the discovery that the ratio between the input and output capacitance of the oscillator affects the power dissipation of the oscillator. In particular, it has been discovered that increasing the ratio between the input capacitance and the output capacitance of the oscillator very substantially decreases the power consumption. Unfortunately, it has also been discovered that the decreased power consumption is achieved at the expense of frequency stability as a function of operating voltage. This problem has been solved, in accordance with another aspect of the present invention, by incorporating in the circuit a voltage controlled capacitor which changes value in a sense to compensate for the tendency for the oscillator frequency to change with voltage.
The invention is illustrated in the drawing of which:
FIG. 1 is a schematic diagram of a known CMOS oscillator;
FIGS. 2 and 3 are graphs which illustrate certain operating parameters in the circuit of FIG. 1;
FIG. 4 is a schematic drawing of an improved oscillator in accordance with an embodiment of the invention; and
FIGS. 5 - 7 are graphs to help explain the operation of the circuit of FIG. 4.
The known oscillator of FIG. 1 includes a field effect transistor inverter formed of complementary MOS transistors P1 and N1. The conduction paths of these transistors are connected in series between two operating voltage terminals, one at VDD and the other at a second level, ground in this example. The crystal 10 is connected between the input terminal 12 and the output terminal 14 of the inverter. Resistor 16 connects across the crystal. Input capacitor Ci is connected between the input terminal 12 and a point of reference potential, shown as ground, and output capacitor Co is connected between the output terminal 14 and ground.
It is known in the art that frequency stability may be achieved in the circuit of FIG. 1 by making the output capacitance Co much larger than the input capacitance Ci. If the supply voltage VDD changes by some small amount ΔV, for example, the amplifier phase shift φa also changes and the phase shift through the feedback network φn) then also will change to satisfy the condition.
φa + φn = 360° (1)
It is known that when φn changes, there is also a change in the oscillator frequency. However, if dφn /df of the feedback network is high, this frequency change will be relatively small.
The parameter dφn /df is related to the input capacitance Ci and the output capacitance Co in the manner shown in FIG. 2. It is clear from this FIGURE that at a given input capacitance, as the output capacitance increases, dφn /df also increases. Put another way, as the ratio between Co and Ci increases, the parameter dφn /df increases. It is therefore clear that oscillator frequency stability as a function of operating voltage, can be improved by making Co large and Ci small.
The present inventor has discovered, however, that the above is contrary to the condition required for low power dissipation, that is, for low operating current. It can be shown that the average feedback network current IA can be defined as: ##EQU1## where: fo = crystal frequency ##EQU2## R and L are resistance and inductance parameters associated with the crystal
Ci = input capacitance; and
Co = output capacitance
Equation 2 is plotted in FIG. 3 for an AT cut, 4 MHz crystal. As is clear from this FIGURE, as the input capacitance increases, the average current IA in the feedback network decreases. This is quite surprising as one would expect an increase in capacitance to result in an increase in current. It may also be observed from FIG. 3 that very substantial differences in current flow result at different values of input capacitance. For example, at an output capacitance Co of 10 picofarads (pf) or so, roughly one tenth as much current IA flows when Ci = 32 pf as when Ci = 1 pf. However, referring back to FIG. 2, the frequency stability (proportional to dφn /df) is much lower at Ci = 32 pf than at Ci = 1 pf.
In a circuit according to the present invention, as shown in FIG. 4, the input capacitance Ci is made much much larger than the output capacitance Co (larger at least by a factor of 10 or so). Unfortunately, as is shown in FIG. 2 this results in relatively poor frequency stability (a relatively low dφn /df). In some applications this can be tolerated. However, where high timing accuracy is required, the poor frequency stability with operating voltage is a serious disadvantage.
The present inventor has discovered that this disadvantage may be obviated by including in the circuit a voltage controlled capacitor CR between the input and output terminals 12 and 14 of the oscillator. In the circuit of FIG. 4, if the voltage VDD should, for example, increase, the phase shift through the amplifier will increase and will approach more closely 180°. As the phase shift φa through the amplifier increases toward 180° (and the phase shift φn through the feedback network corresponding decreases towards -180°) the result is a frequency increase from the oscillator. The voltage controllable capacitor CR, however, increases its capacitance in response to the increase in operating voltage VDD. It is particularly convenient to place CR between the input and output terminals since small changes in this capacitance cause a greater frequency shift than equal changes in Co and Ci. By choosing CR to be of an appropriate value, the capacitance change in response to VDD can be made to be such that it causes the oscillator frequency to change in a sense opposite to and an amount equal to the change in oscillator frequency caused by the change in φn. In other words, CR changes in a sense and amount to maintain the oscillator frequency reasonably constant even though VDD changes.
The above is illustrated in FIGS. 5 and 6. FIG. 5 indicates that if the phase angle φN decreases then frequency increases. FIG. 6 is a plot of the change in frequency as a value of the load capacitances of CL. The schematic diagram of this figure is the equivalent circuit of the crystal and CL, interpreted in the light of FIG. 4, includes the capacitance of the voltage controllable capacitor CR. It is clear that if VDD changes (increases, for example,) which tends to cause an increase of the oscillator frequency as illustrated in FIG. 5, that the load capacitance CL (which includes CR) increases and tends to decrease the oscillator frequency. Thus by choosing an appropriate value of the voltage controllable capacitance, the oscillator frequency can be kept constant over a reasonable range of VDD. Ordinarily, the change in VDD is such that the change in CL required to compensate is generally not more than several picofarads.
The capacitor CR can be a lumped, voltage controllable capacitor such as a back biased diode, as one example. There are also other possibilities. However, it is preferred to use a distributed capacitance element and this is the reason this capacitor is shown in phantom in FIG. 4. It is particularly convenient to employ the capacitance between the gate electrodes of the P and N devices and the respective conduction channels of these devices. This can be done without changing the length-to-width ratio of each channel. The area of the gate electrode determines the amount of distributed capacitance which is introduced. If, for example, the gate electrode is made wider so that the channel width is increased, the length-to-width ratio of the channel may be retained at its original design value by spacing the source and gate electrodes further apart.
It is important in oscillator applications that the design width-to-length ratio of the respective transistors be retained at their original design value because this parameter determines the oscillator starting voltage. The particular width-to-length ratio which is chosen in any application will depend upon the battery operating voltage and other design criteria.
FIG. 7 illustrates the gate-to-drain capacitance CGD of a MOS transistor as a function of the gate to source voltage VGS. The maximum capacitance reached, COX, is directly proportional to the width and length of the channel and inversely proportional to the thickness of the channel.
A circuit such as shown in FIG. 4 may have the following circuit parameters:
Ci = 7 picofarads
Co = 0.3 picofarads (this is an estimate, as the capacitance employed is a distributed capacitance -- that present between point 14 and ground)
16 = 22 megohms
10 = nominally 2.097150 MHz
P1 channel width (WP1) = 4.8 mils
P1 channel length (Lp1) =0.4 mils
WP1 /LP1 = 12
n1 channel width (WN1) = 2.4 mils
N1 channel length (LN1) = 0.4 mils
WN1 /LN1 =
the W/L ratio of the P type transistor is double that of the N type transistor to obtain equal source-to-drain current flows, as is understood in the art. The threshold voltage VT of each device is about 0.5 volt.
The circuit above was operated at different values of VDD and the following results obtained
VDD FREQUENCY______________________________________2.5 volts 2.0975233.0 volts 2.0975184.0 volts 2.097521______________________________________
The variation in frequency is roughly ± 1.5 parts per million over the VDD range shown which is very fine indeed.
Care must be taken in the design above not to employ too much capacitance CR or overcompensation results. For example, it is found that when the channel dimensions are increased as follows to cause a corresponding increase in CR,
wp1 = 12 mils
LP1 = 1 mil
WP1 /LP1 = 12
wn1 = 6
ln1 = 1
wn1 /ln1 = 6
the results below are obtained:
VDD FREQUENCY______________________________________2.5 volts 2.097560 MHz3.0 volts 2.097536 MHz4.0 volts 2.097506 MHz______________________________________
Here the frequency variation is roughly ± 14 parts per million.
Note that in the circuits described above a 2 MHz crystal rather than the 4 MHz crystal mentioned in the introductory portion of the specification; however, the operating principle remains the same. Note also that in each example the oscillator frequency differs from the nominal crystal frequency. This is normal and is a function of the distributed capacitance present in the particular circuit employed.