Jitter & the Digital Interface Page 3
Moreover, calculations show that jitter caused by interface band-limiting is correlated with the signal. In fact, frequency analysis, both theoretical and measured on equipment, shows the jitter spectrum to exhibit lines corresponding to the signal frequency and to interference or beating between the signal and the sampling frequency. These beat frequencies themselves modulate the signal frequency inside the converter to produce artifacts. For example, a 4kHz signal causes a jitter spectral line at 100Hz by beating with the 44.1kHz sampling frequency. The 100Hz component in turn causes jitter at 3.9kHz and 4.1kHz to appear on the reconstructed signal's spectrum (footnote 7).
This somewhat simplistic demonstration of the generation of jitter by bandwidth limitations is intended more to give a physical understanding of the problem than to yield an exact numerical value. For a more refined computation, one must know which digital interface signal edges actually contribute to the jitter, and which do not. The Crystal CS8412 and the UltraAnalog AES 20 receivers, for instance, use only half of the edges to regenerate the master clock. The Yamaha YM3623B receiver uses only the edges located in that portion of the signal called the preamble. The definition of digital interface jitter must then be modified to exclude the edges ignored by the receiver.
Another great contributor to interface jitter is the mismatch between transmission cable and receiver impedance. A 10' cable represents a round-trip delay of about 30ns (30,000ps), and any impedance mismatch adds an attenuated echo signal with the same 30ns delay. It doesn't take three pages of math to realize that this causes quite a mess. In that respect, one may regret the loose impedance (110 ohms ±20%) specification recommended by the AES/EBU standard. Equipment manufacturers should attempt to be as close to 110 ohms impedance as possible for their transports, processors, cables, etc. A tolerance of 5% is a good starting point; 3% would be better. The consumer S/PDIF interface, with a 75-ohm ±5% impedance spec, is probably acceptable.
Once the transmitter/transport and the receiver have the proper impedance, the cable needs to be impedance-matched. While several companies have recently introduced mechanically superb and financially extravagant cables, impedance matching in itself does not need to be expensive. The television industry has been producing impedance-matched cables and connectors for use up to 900MHz; even good-quality cables are reasonably priced. While shielding of AES transmission pairs is a good idea, the isolation requirements are well below that of analog cables. Hence, two digital transmission cables with the same characteristic impedance will have the same effect on the jitter, whether they cost $3 or $300.
It's clear that jitter performance of an AES/EBU or S/PDIF transmission link is highly dependent on hardware implementation. This includes the transmitter (a CD transport), the interface cable, and the input receiver in the digital processor. Of the three, the receiver is, at least conceptually, clearly the most difficult one to design and manufacture. Although a low-jitter transmitter and interface isn't, in theory, that difficult to design, bad cables and transmitters/transports abound in the real world.
Measuring transport & interface jitter
The designer of low-jitter circuits faces a great obstacle: the lack of commercially available instruments for measuring jitter. Without a way of measuring jitter, how can we know how our transmitters, interfaces, and input receivers are performing? The solution is to design and build your own jitter analyzer. This is, however, no small task; many pitfalls await the courageous adventurer.
Clock jitter can be measured in three ways, each with its advantages and disadvantages. First, we can measure jitter using a reference clock running at a different frequency from the clock we want to measure. This is the method used in reciprocal counters. The reference clock is compared to the measured clock. To be of any use, the counter must resolve time within a reference clock period. The instrument's quality is based on the accuracy of this time resolution. Moreover, crosstalk between the reference and measured clocks must be avoided. This method will work with non-periodic signals such as those carried by the AES/EBU or S/PDIF interface signal.
Another method uses a reference clock running at the same frequency as the measured clock. This technique can measure the jitter degradation caused by a circuit, or measure the intrinsic jitter and jitter attenuation characteristics of a phase-locked loop (PLL) such as is found in input receiver circuits. The recovered clock is compared to the reference clock with a relatively simple circuit. The reference clock must be of extraordinary accuracy. UltraAnalog uses this technique to measure the performance of its low-jitter AES 20 input receiver.
Finally, clock jitter can be measured with a low-jitter PLL. The incoming clock is sent to a PLL with very low intrinsic jitter and a very low jitter attenuation cutoff frequency. The low-jitter clock is compared with the incoming clock; a simple circuit separates the jitter component in the incoming clock and outputs the jitter in analog form.
The PLL's jitter attenuation cutoff frequency must be very low. Below the attenuation cutoff frequency, the PLL follows the incoming clock and its jitter, passing the incoming jitter to the recovered clock. The recovered clock will thus have the same jitter as the incoming clock; no measurement can be made by comparing the two clocks. By replacing the simple phase comparator described in the second method with a more sophisticated cascaded track-and-hold circuit, this technique can measure non-periodic signals such as the digital interface signal.
This is the method used in the custom jitter analysis instrument built by UltraAnalog, shown in block form in fig.7. An AES/EBU or S/PDIF signal is input to the analyzer, and the analyzer's output is the jitter component of the measured clock, with a gain of 100mV per nanosecond of jitter. The instrument's measurement bandwidth is 500Hz-100kHz, and the intrinsic (residual) jitter is less than 30ps. This 30ps figure defines the minimum jitter level that can be measured by the instrument. Figs.8 and 9 show the instrument's bandwidth and intrinsic jitter, respectively. The plots of fig.9, made with different input signals to the analyzer, represent the combined performance of the test transport and analyzer. Although the spectral analysis in fig.9 is extended to 200kHz, the jitter numbers in the caption represent the RMS jitter values calculated over a DC-40kHz bandwidth.
Fig.7 UltraAnalog jitter analyzer architecture.
Fig.8 UltraAnalog jitter analyzer frequency response.
Fig.9 UltraAnalog jitter analyzer, spectrum of intrinsic jitter (19.3ps, solid line); while decoding 1kHz at 0dBFS (27.8ps, long-dashed line); decoding 1kHz at -60dBFS (32.1ps, short-dashed line); and decoding 60Hz+7kHz in a 4:1 mix at 0dBFS (29.1ps, dotted line) (vertical scale is ps per 1/3-octave band).
With this jitter-analysis instrument, we can measure and quantify the performance of any digital source and interface combination, such as CD transports, DAT machines, or "jitter-reduction" devices. In addition, the analyzer can measure the performance of a digital processor's input receiver circuitry.
Footnote 7: The way in which a 4kHz signal can produce a 100Hz line by beating with 44.1kHz can be explained by the fact that the data-to-jitter crosstalk is highly nonlinear, and that all harmonics of the 4kHz frequency, including 44.0kHz, are present and beat with 44.1kHz.—Rémy Fourré