Research Scientist at
the Microsystems Technology Laboratories.
617 253 4183
Various Projects and Interests
Computer aided design tools and techniques for microsystems design.
Semiconductor device modeling. Inverse modeling problems and techniques.
Sage mathematical software.
Computer microvision for microelectromechanical systems.
Gestalt-class, an object oriented database programming interface.
Lee, Z. K., M. B. McIlrath, and D. A. Antoniadis, "Two-Dimensional Doping Profile Characterization of
MOSFETs by Inverse Modeling Using I-V Characteristics in the Subthreshold Region," IEEE Transactions on
Electron Devices, Vol. 46, No. 8, 1640-1649.
A. Gower, D. Boning, and M. McIlrath, "Flexible, Distributed Architecture for Semiconductor Process Control and Experimentation", Proceedings of the Society of Photo-optical Instrumentation Engineers 2912.
"Semiconductor Process Representation". Encyclopedia of
Electrical and Electronics Engineering, vol. 19.
D. S. Boning, M. B. McIlrath, P. Penfield, Jr., and E. M. Sachs, "A General Semiconductor Process Modeling Framework", IEEE Transactions on Semiconductor Manufacturing, pp. 266-280, Nov. 1992
M.B. McIlrath, D.E. Troxel, M.L. Heytens, P. Penfield, Jr., D.S. Boning, and R. Jayavant, "CAFE - The MIT Computer-Aided Fabrication Environment,"
IEEE Transactions on Components, Hybrids, and Manufacturing Tech.
, 15(2): 353-60.
Thesis Supervision (Advisor/Co-advisor)
Gower, A. Integrated model-based run-to-run uniformity control for epitaxial silicon deposition. Ph.D thesis, Dept. of Elec. Eng and Comp. Sci., MIT, 2001
Verminski, M.A Distributed Software Architecture for Semiconductor Process Design.S.M. thesis.Department of Electrical Engineering and Computer Science, MIT, February 1998
Exploring Semiconductor Device Parameter
Space using Rapid Analytical Modeling.
thesis. Department of Electrical Engineering and
Computer Science, MIT, January 1998
Rahman, N. E. Extraction of MOSFET Doping Profiles from Device Electrical Measurements. M. Eng. Thesis. Dept. of Electr. Eng. and Comput. Sci., MIT, 1996.
Unver, E.R. Implementation of a Design Rule Checker for Silicon Wafer Fabrication. M.E.thesis. Dept.of Electr. Eng. and Comput. Sci.,MIT,1994
Course VI undergraduate advisor.
Some information for advisees here.