US 7952185 B2
A device comprising a chip, which is held in casting compound and on which a hollow structure is arranged is disclosed.
1. A device, comprising:
a chip, which is held in a casting compound and on which a hollow structure is arranged, the casting compound and the hollow structure each forming part of a surface of the device which extends substantially in parallel to a principal plane of the chip;
a dielectric layer,
a first electrically conductive layer overlying at least a part of a surface formed by the casting compound and a part of a surface being formed by the hollow structure, wherein the first electrically conductive layer is arranged between the chip and the dielectric layer, and
wherein the hollow structure is arranged between the chip and a portion of the first electrically conductive layer in relation to a direction normal to the principal plane.
2. The device of
3. The device of
4. The device of
5. The device of
6. The device of
7. The device according to
8. The device of
9. The device of
10. The device of
wherein the upper side is not covered by casting compound and forms part of the surface of the device; and
wherein the first electrically conductive layer extends over at least a part of the upper side of the hollow structure.
11. The device of
12. The device of
13. A device, comprising:
a chip, which is held in a casting compound and on which a hollow structure is arranged, the hollow structure having a lid and a sidewall, the sidewall enclosing a portion of the chip, extending between a surface of the chip and the lid, and the lid at least partially covering the portion of the chip; and
a first electrically conductive layer, which has been applied at least in certain regions to the casting compound;
wherein the lid of the hollow structure comprises a through-hole for connecting the hollow structure to its surroundings, the through-hole being hollow, and
wherein the first electrically conductive layer and the through-hole are arranged at a same side of the chip.
The present application claims priority to German Patent Application No 10 2006 058 010.9, filed Dec. 8, 2006, the entirety of which is hereby incorporated by reference.
The invention relates to semiconductor devices with hollow structures.
Many chips, in particular those with electromechanical systems, require a hollow to ensure their function. Various techniques are known for creating such a hollow. It is possible to create the walls of the hollow by structuring a layer, subsequently dividing up the wafer into individual chips and then closing the hollow by applying a cover to the walls of the hollow. Another possibility is to produce the hollow by using a further wafer which has depressions in its surface, forming hollows over the active surface of the first wafer when the two wafers are joined together.
Against this background, according to a first aspect, a method of producing devices in which hollow structures are produced on a wafer is provided. The wafer is divided into at least two chips. The two chips are covered with casting compound. By dividing the casting compound, at least two chips are separated.
According to a second aspect, an arrangement which has a number of chips which are together held in casting compound and on which hollow structures are arranged is provided.
According to a third aspect, a device which has a chip which is held in casting compound and on which a hollow structure is arranged is provided.
The invention is explained in more detail below by way of example with reference to the drawings, in which:
Devices with a chip embedded in a casting compound are described below. The chips may be of extremely different types and contain for example electrical or electromechanical functional elements in the region of their active area. The chips may be configured as so-called MEMS (Micro-Electro Mechanical Systems), it being possible for micro mechanical structures such as for example bridges, membranes or tongue structures to be provided. The chips may be configured as sensors or actuators, for example BAW (Bulk Acoustic Wave) filters, pressure sensors, acceleration sensors, rotation sensors, microphones and so on and so forth. Chips in which such functional elements are embedded generally comprise electronic circuits which serve for driving the functional elements or further process signals generated by the functional elements. Like the chip, the functional elements accommodated in the hollow may consist of semiconductor material, but may also be produced from other materials, such as for example insulators, plastics or metals.
As explained in more detail below on the basis of examples, multichip devices with a number of functional elements, for example the combination of two BAW filters with the same resonant frequency or tuned to slightly different resonant frequencies may be provided. Other chips and/or passive electronic components may also be integrated in a device along with the chip with a hollow structure provided on top. For example, a chip with a hollow structure for realizing the MEMS functionality (for example a BAW filter) and a chip without a hollow structure for signal generation and/or signal evaluation (for example an LNA (low noise amplifier)) may be provided in a multichip device. Apart from realizing the hollow structure from a polymer in the way described in more detail below, the hollow structure may also consist of other materials, for example a semiconductor material or an insulator, for example glass.
The hollows 4 are produced in the wafer assembly. This may be performed for example by a polymer material being used for the layer 6 and structured by a photopatterning technique. The creation of the hollows 4 in a polymer layer 6 is explained later by way of example on the basis of
Furthermore, it is also possible to use photolithographic means to produce free regions 8, in which wafer metallizations 7 are created, in electrically conductive connection (not represented) with one or more electromechanical functional elements 3, and consequently forming terminal regions for the operation of the electromechanical functional elements 3.
It is pointed out that the structuring of the outer walls of the hollow enclosure 5 does not necessarily have to be performed by the singulation into chips 11, but in the same way as the creation of the free regions 8 can be carried out photolithographically in the wafer assembly. This allows any desired peripheral form of the hollow enclosures 5 to be achieved, and in particular the hollow enclosures 5 may be dimensioned in such a way that they are arranged only over a partial region of the chip area. For example, a structuring of the layer 6 may be performed along the dividing lines provided for the chip singulation. This has the effect that the layer 6 is not subjected to mechanical stress during the chip singulation. In this case, a free space that runs around in the manner of a frame may be present between the outer edge of the chip 11 and the contour line of the hollow enclosure 5.
The production of the hollow enclosures 5 and wafer metallizations 7 by suitable structuring of a layer 6 represents a low-cost method, since essentially only layer depositing and photolithographic techniques have to be used, and the creation of the hollows 4 is performed in the wafer assembly. The hollow enclosures 5 may, however, also be created in some other way, for example by a second wafer (for example made of glass or semiconductor material) being provided with suitable depressions and joined together with the semiconductor wafer 1 in such a way that the depressions form the hollows 4. In this case, wafer metallizations 7 may be realized for example by etching free appropriate regions in the second wafer, used as a covering.
It is pointed out that the top region of the hollow enclosure 5 is not mechanically stressed by the casting step, since the upper side 10 of the hollow enclosure 5 is not encapsulated with casting compound. This makes it possible to prevent the hollow enclosure 5 being compressed by the casting step, which can very easily occur in the case of encapsulating the entire hollow enclosure 5, for example in the case of a hollow enclosure 5 consisting of polymer material. The free (i.e. unsupported) side wall regions of the hollow enclosure 5 are shorter than the free (i.e. unsupported) top region of the hollow enclosure 5 and may additionally be made stronger, so that no damage is caused by the casting operation in the side wall region surrounded by casting compound.
Before the cast wafer 16 is singulated into chip packages, further process steps may be carried out in the “cast wafer assembly”. Such processes can be carried out at particularly low cost, since the chip packages can be simultaneously processed while they are still together in the cast wafer 16. The cast wafer 16 forms as it were an artificial wafer, to which the production steps known from WLP (wafer level packaging) technology can be applied. In WLP technology, all the processes carried out before a wafer is divided into chips are carried out at wafer level. By analogy with WLP technology, it may be provided in the present case that, after the production of the cast wafer 16, all the processes carried out before the cast wafer 16 is singulated into chip packages are carried out at “cast wafer level”, i.e. for all the chip packages together on the intact cast wafer.
The thin-film technique that is used allows the polymer layers 20, 21 and metallization layers to be very thin and the structuring to be very fine. Typically, the polymer layers are 5 to 20 micrometers thick and the metallization layers 2 to 15 micrometers thick. The polymer layers 20, 21 consist for example of polyimide and are deposited by a depositing process, for example spin coating, on that surface of the cast wafer 16 that is formed in certain regions by the upper sides 10 of the hollow enclosures 5. The contacting of the chips 11 by means of a thin-film technique is illustrated in
If, other than as represented in
Regions of the chip package outside the chip contour are also available for the wiring, i.e. the external terminal areas 22 may lie with some or all their surface area outside the contour line (“footprint”) of the chip 11.
Subsequently, solder depots or solder balls 24 may be attached to the external terminal areas 22. This operation, referred to as ball attach, is likewise preferably performed on the intact cast wafer 16 and may be performed for example by means of templates which apply solder material to the external contact areas 22 at the correct locations.
After the performance of any further process steps there may be, the cast wafer 16 is divided up into individual chip packages 25, see
A further variant is to provide a passage 30, which passes through the polymer layers 20, 21 and the top region of the hollow enclosure 5 and consequently connects the hollow 4 to the surroundings. The passage 30 may be created for example by photopatterning. This variant of a chip package 25.2, represented in
SiP (system in package) modules, which may contain a number of chips 11 or a single chip 11 and further passive or discrete devices in a chip package 25.5, can also be realized as a further configuration.
As described in conjunction with
The exposures have the effect of inducing in the polymer layer 6 a crosslinkage of the exposed regions with different depths that can be specifically set. The different depths may be accomplished for example by using different wavelengths of the light used for the exposure. The crosslinked regions 43 are represented in
The top hole 44 may possibly be closed with a further polymer layer 45. The structure 5 represented in
It is true for all the exemplary embodiments that a high degree of flexibility is made possible with respect to arrangements and geometries of hollow enclosures 5 and external terminal areas 22. The production of the hollow enclosures 5 at wafer level makes production possible in a low-cost way. A further cost reduction is achieved by the use of low-cost “photoresist hollow enclosures” of a polymer, allowing a packaging with reliable process attributes to be achieved in spite of their low mechanical load-bearing capacity as a result of the top region 10 being left free during the casting. The multilayer thin-film technique allows a “fan-out design” to be achieved on the contact level, by which package terminals can be realized outside the chip area, thereby making it possible to achieve both an increase in the contacting reliability, by increasing the pitch spacing between external terminal areas, and an increase in the number of external terminal areas. This also opens up new possibilities in particular for the production of SiP modules of extremely varied types and designs.
It is therefore intended that the foregoing detailed description be regarded as illustrative rather than limiting, and that it be understood that it is the following claims, including all equivalents, that are intended to define the spirit and scope of this invention.