US 7240249 B2
A deskewing circuit configured to receive a main clock signal wherein data bits are misaligned with respect to the main clock signal. A multiphase clock generator coupled to the main clock to generate N/2 clock phases on the rising edge of the main clock and N/2 clock phases on the falling edge. A plurality of n samplers to generate a first set of N/2 sampled signals on the positive phases and a second set of N/2 sampled signals on the negative phases. A corresponding plurality of n phase selectors to determine which phase is the best for each set of sampled signals and generate the two selected signals corresponding to that phase. A control logic block configured to receive a corresponding plurality of n first control signals. A data bus gathering all said selected signals for further processing, wherein said selected signals are aligned with said reference clock but misaligned with respect to each other.
1. A deskewing circuit configured to receive a main clock signal having a period T and a plurality of n data bits in parallel wherein said data bits are misaligned with respect to said main clock signal; said deskewing circuit comprising:
a multiphase clock generator coupled to said main clock to generate N/2 clock phases on the rising edge of the main clock and N/2 clock phases on the falling edge thereof, one of said clock phases being selected as the reference clock;
a plurality of n samplers, each sampler being coupled to one data bit and to said N clock phases to generate a first set of N/2 sampled signals wherein x varies between 0 and N/2-1 on the positive phases and a second set of N/2 sampled signals on the negative phases;
a corresponding plurality of n phase selectors, each phase selector being coupled to said two sets of sampled signals to determine which phase is the best for each set of sampled signals and generate the two selected signals corresponding to that phase on the one hand, and a first control signal on the other hand that indicates when this determination is completed;
a control logic block configured to receive a corresponding plurality of n first control signals and a determined pair of sampled signals and in turn, to generate a second control signal that inhibits said phase selectors as soon as said control signals indicate that the best phase has been determined for all said phase selectors; and
a data bus gathering all said selected signals for further processing, wherein said selected signals are aligned with said reference clock but misaligned with respect to each other.
2. The deskewing block of
The present invention relates to high speed networking and more particularly to an improved circuit for bit skew suppression in high speed multichannel data transmission.
Cross reference is hereby made to EP patent application No. 04101582.7, entitled Improved circuit for bit alignment in high speed multichannel data transmission which was filed on even date herewith.
At high frequency transmission rates, when bits are transferred in parallel on the same bus, for example at the interface between a telecom chip and a network processor, a misalignment of the bits often occurs. This misalignment, commonly referred to as the skew, is often due to transmission path differences, but can also result from other factors such as impedance mismatches or delays in the clock signals. When bits are transferred in parallel at high speed, they go through different paths, and therefore have different arrival times.
For example, the Frame Based ATM level 4 or the SPI4 phase 2 protocols recommended respectively by the ATM and OIF forums, state that deskewing is only mandatory if the transmission lines (or links) are running at more than 350 MHz, but not for the lower frequencies (the standard transmission range starts at 310 MHz). When the bits are received in accordance with these protocols, a training sequence is sent inband periodically. The 20-word training pattern consists of 10 repeated training control words followed by 10 repeated training data words, wherein the training data word 1111000000000000 is orthogonal to the training control word 0000111111111111. It is applied to a 17 bit-width data bus, 1 control bit being associated to each set of 16 bits.
In this context, the role of the deskewing/alignment block 14 is to suppress the skew and properly realign the data and control bits on the main clock. To that end, it analyses the border between the training control words and the training data words to determine the delay which must be added to each transmission line of the data bus to realign the bits. This delay defined during the training period is then applied to inband data bits.
As illustrated in
In turn, the deskewing block 17 generates an internal reference clock signal (ref_clk), 2*16 data bits (bit_tdat) and 2*1 control bits (bit_tctl), that are sent to the alignment block 18. Said data and control bits are aligned with said reference clock but misaligned with respect to each other. Finally, the alignment block 18 processes these bits and generates 2*16 data bits (tdat_desk) and 2*1 control bits (tctl_desk) that are still aligned with said main clock and are now also aligned with each other.
After reset, the source continuously sends training patterns until enough valid parity values are received. Each control word and especially each training control word includes a parity field which is a diagonal interleaved parity computed on all the data which have been received after the previous control word. The parity values will not be correct until the deskewing is properly done.
It is therefore desirable to have a deskewing/alignment block combination which renders the functional logic block totally skew insensitive on the totality of said standard transmission range. It is also desirable to avoid the need of switching between two telecom systems or operating modes depending on whether the transmission frequency is lower or higher than 350 MHz. It is further desirable to have a deskewing/alignment block combination that performs an automatic discrimination between the data sequences and the training sequences that are periodically sent inband. Finally, it is still further desirable that there is no interaction between the deskewing/alignment block combination and the functional logic block.
According to the present invention there is described an improved deskewing circuit configured to receive a main clock signal having a period T and a plurality of n data bits transmitted in parallel at very high speed wherein said data bits are misaligned with each other and with respect to said main clock signal (skew). Said improved deskewing circuit comprises:
The novel features believed to be characteristic of this invention are set forth in the appended claims. The invention itself, however, as well as other objects and advantages thereof, may be best understood by reference to the following detailed description of an illustrated preferred embodiment to be read in conjunction with the accompanying drawings.
The block diagram architecture of the deskewing block 17 in accordance with the present invention is shown in
In addition, the sampler is used to perform the clock domain change from the sampling clock to the phase selected as the reference clock, e.g. P0, referred to as ref_clk hereinbelow. As shown in
The generation and the role of these signals will be explained later on in due course. The phase selector 24-i generates the bit_deskewed(i) and the two selected data bit signals bit1tdatp(i) and bit_tdatn(i) signals. The bit_deskewed(i) signal is set high to indicate that phase selector 24-i has determined which phases were the best for sampling the data bits. The same reasoning applies to the control bits, phase selector 24-16 generates the bit_deskewed(16) and the selected control bit_tctlp and bit_tcltn signals. The sampled signals tdatp0(i), tdatn0(i), tctlp0 and tctln0 and tctln7 on the one hand and the bit_deskewed(i) signals, wherein i still varies from 0 to 16 on the other hand, are applied to a control logic block 25.
This block, which also receives the end_of_training signal, generates the training_mode signal mentioned above and the bit_deskewed signal. The latter signal indicates that the operation of determining the best phase in all phase selectors 24-0 to 24-16 has been completed. The sampled signals and the selected signals are made available on a double width data bus 26 that thus transports 32 data bits, referred to as the bit_tdat(0) to bit_tdat(31), (bit_tdat 0 to 31 in short) and 2 control bits referred to as bit_tctl(0) and bit_tctl(1), (bit_tctl 0 to 1 in short), that will be applied to the alignment block 18 shown in
In summary, the main role of the deskewing block 17 is to find the best phase to sample each of the incoming bits and to output 2 sets of data/control bits in the common clock domain (ref_clk). To that end, the samplers 23- are used to sample the bits with different clock phases and the selectors 24- choose the best phase for each bit. On the other hand, the control logic block 25 detects the training sequences and properly drives the phase selectors. In essence, the deskewing block 17 schematically shown in
1. Description of the Multiphase Clock Generator 19
Multiphase clock generator 19 can be implemented either with a controlled delay line loop circuit (DLL) or a phase locked loop circuit (PLL). The latter circuit is more flexible in that it can operate with frequencies as low as 100 MHz. If implemented with a DLL, sixteen different clock phases with a fixed delay between each other are necessary. If implemented with a PLL, sixteen different clock phases equally spaced in the clock period are necessary. In the present implementations, the deskewing mechanism can be used with a double edge clock running between 100 and 500 Mbits/s, which is equivalent to a 200 Mbits/s to 1000 Mbits/s range.
As shown in
Referring now to
2. Description of the Control Logic Block 25
The main task of the control logic block 25 is to detect the training sequences and properly drive the phase selectors. It consists in a finite state machine (FSM) and some counters and flags, but it will betterr be described by its functionalities. These counters and flags include:
Wait_for_training: the FSM stays in this state as long as the incoming data does not contain a suspected training word (0FFF0FFF) with the control bit tctl high. The training control word and training data word counters are reset. The training_ongoing and training_mode flags are reset, too, respectively at 0 and 00.
The logic diagram of the one-bit sampler 23-i is schematically shown in
As shown in
This last set of latches generates eight signals, tdatp0(i) to tdatp7(i), that are the incoming data bits sampled with the positive clock phases. A symmetric construction applies to the lower slice 37-2 with respect to the negative clock phases to generate sampled signals tdatn0(i) to tdatn7(i). However, in the lower slice, the first and second column of latches are clocked by the phase N0 while the phase P0 is clocking the third column of latches. By this mechanism, both the metastability problems and the clock domain change are taken care of.
The same reasoning applies to sampler 23-16 which samples the control bit tctl to generate control bits tctlp0(i) to tctclp7(i) using the positive clock phases P0 to P7 in the upper slice and to generate control bits tctln0(i) to tctcln7(i) using the negative clock phases N0 to N7 in the lower slice. Once the sampling is done, the data are moved to the reference clock domain, ref_clk is the clock used by the next circuits. The sampled data and control bits are used by the control logic block 25 described above to check if they are training words. In summary, bit sampler 23-i generates two set of data/control bits sampled with the positive and negative clock phases respectively. Once the 16*17 bits are output, the phase selection operation can start in the corresponding phase selector 24-i.
4. Description of the One-bit Phase Selector 24
The logic diagram of the one-bit phase selector 24-i is schematically shown in
As shown in
To that end, the output of counter enabler 43-x is connected to the enable input of each of said counters while each clock input thereof receives the reference clock ref_clk. The output of each counter, e.g. 44-x 0, is connected to the first input of a corresponding comparator, e.g. 45-x 0 which receives the counter threshold information from a dedicated control block referenced 46. All the outputs of comparators 45-x 0 to 45-x 7 in slice 41-1 are applied to a phase encoder 47. Likewise, the latter also receives the eight signals resulting from the processing of sampled data bits tdatnx(i) in the lower slice 41-2. Phase encoder 47 generates the encoded_phase signal that is applied to the control block 46. The training_mode, the counter threshold, and the bias (for positive and negative phases) signals are also applied to the control block 46 as inputs.
The role of this control block 46 is to decode the signal representing the training_mode flag. Indeed, depending on the value of the training_mode flag, the control block 46 will enable/disable the counter enablers 43- via the enable/disable signal. Control block 46 generates the selected_phase signal that specifies the two selected phases (positive and negative) that are applied to the control input of the multiplexor 48, which receives data bits tdatpx(i) and tdatnx(i), wherein x varies from 0 to 7, as inputs. In turn, multiplexor 48 generates data bits bit_tdatp(i) and bit_tdatn(i). Likewise, selector 24-16 (not shown) receives sampled control bits tctlp and tctln before processing them the same way.
Once the signals generated by phase selectors 24-0 to 24-16, i.e. bit_tdatp(0) to bit_tdatp(15), bit_tdatn(0) to bit_tdatn(15), bit_tctlp and bit_tctln, are gathered, they form the bus 26 shown in
During the training sequence (training_mode flag=01), the phase selector 24-i looks for a transition 1->0 if the two last bits were 1, or 0->1 when the two last bits were 0. To do so, the transition encoders 42-x are used on each set of 8 bits sampled values in accordance with the conversion scheme depicted in Table 1 or Table 2 below, and the counter enabler 43-x associated therewith enables the correct counter. A counter is dedicated to each of the eight positive and negative clock phases. As shown in
At that time, the control block 46 stores the encoded_phase signal which represents the phase where the transition has occurred the most often. Then, by adding positive and negative bias signals, it selects two phases (one positive and one negative) to select the corresponding data bits tdatpx(i) with the phase_select (for positive phases) signal and tdatnx(i) with the phase_select (for negative phases) signal at a stable position. As shown in
In these tables, the left values are the possible sampled values that are input during training sequences and the right values are the phases where the transition occurred. The only difference between Tables 1 and 2 is the fact that the first encode scheme is level triggered, while the second encode scheme is edge triggered. The deskewing mechanism can be used to correct relative skew differences of +/− two cycles.
Description of the Alignment Block 18 Overall Architecture
Alignment block 18 will be now described by reference to
These latched signals, labeled buffer_1(i+16) and buffer_1(i), are applied to said multiplexor 50-i as two other inputs and to the data input of another pair of flip-flops referenced 52-i-1 and 52-i-2 (form sub-block 52-i) that respectively generate signals buffer_2(i+16) and buffer_2(i). In turn, these signals are applied to multiplexor 50-i as two further inputs. Finally, signal buffer_2(i+16) available at the output of flip-flop 52-i-1 is supplied to the data input of flip-flop 53-i which in turn generates a signal labeled buffer_3(i+16), applied to the multiplexor 50-i as a seventh input. Note that, the reference clock signal ref_clk is applied to the clock input C of all the flip-flops mentioned above (and by the way of all the flip-flops implemented in
As a result, seven signals are applied to multiplexor 50 i, which thus requires three control signals. Still referring to
As shown in
On the other hand, all the aligned data and control bits generated by aligners 49-0 to 49-16, before latching, are applied to a control block 58. Data bits bit_tdat(i+16), bit_tdat(i) via bus 26 and the bit_deskewed signal are also applied to said control block 58. In turn, control block 58 generates three signals. A first signal, latched in flip-flop 59 is labeled end_of_training, the others are the enable_test and data_align signals mentioned above.
As long as the bit_deskewed signal is low, these three signals will remain low. When the bit_deskewed signal goes high, the enable_test signal detects transitions on the data and control bits sent on data bus 26. It is set to 1 when all these bits are equal to 0 and conversely set to 0 when they are equal to 1. When the enable_test signal goes low, bits output by multiplexor 50- are checked and the data_align signal goes high if the bits are correctly aligned. The end_of_training signal will go high when said bits are no longer a training pattern.
Operation of the alignment block 18 can be understood in conjunction with the following description. At each rising edge of the reference clock ref_clk, there are two sets of data which are coming from the deskewing block 17, 16 data bits plus one control bit corresponding to the positive edge of the main clock tdclk, and 16 data bits plus one control bit corresponding to its negative edge. The role of deskewing block 17 is to align control/data bits on the reference clock ref_clk (but they remain misaligned with each other), while the role of the alignment block 18 is to realign said deskewed but misaligned control/data bits with the main clock tdclk. The FBATM level 4 and the SPI4 phase 2 standards specify that the training pattern can be used to compensate 1 bit time relative skew between two transmission lines. But the alignment mechanism implemented here has been designed to compensate a relative skew of +/−2 bit times.
For a given bit, the training sequence is composed of 2 phases. During 10 cycles, the bits receive a first value, and then the opposite value during the next 10 cycles. For example: 11111111110000000000, then 00000000001111111111. Since the alignment block 18 receives two bits at the same time, only three configurations can be received during a given cycle, i.e. 00, 01, or 11.
XOR gates are used to find out where the transition has occurred, in or out of this couple of bits. This is done for every of the (16+1) couples of bits. If a transition is found inside one couple of bits, the recal(i) signal is set to 1 for this transmission line, otherwise its value is 0. Two other signals labeled realign0(i) and realign1(i) point out that a transition has been detected between two successive couples of bits. This test takes two cycles maximum to operate.
The configuration shown in the first of the two examples depicted in
The second example depicted in
These examples illustrate the role of the realign0(i), realign1(i) and recal(i) control signals, i.e. to properly drive the multiplexor 50-i to select the appropriate data bits to be output among bit tdat(i)/bit_tdat(i+16), buffer_1(i)/buffer_1(i+16), buffer_2(i)/buffer_2(i+16), and buffer_3(i+16). Indeed, when realign0(i)=realign1(i)=0, the bits output by multiplexor 50-i are driven from data bits bit_tdat(i) and bit_tdat(i+16). Therefore, there is no delay at all. When realign0(i)=0 and realign1(i)=1, the bits output by multiplexor 50-i are driven from buffer_1(i) and buffer_1(i+16). Therefore, there is now 1 cycle delay. Finally, when realign0(i)=realign1(i)=1, the bits output by multiplexor 50-i are driven from buffer_2(i) and buffer_2(i+16), then causing a 2 cycle delay.
Furthermore, the realign0(i) and realign1(i) signals select if the data bits that are output pertain to the same column, or to two different columns. When recal(i)=0, the data bits output from the multiplexor 50-i are driven from one column. Either data bits bit_tdat(i)/bit_tdat(i+16), buffer_1(i)/buffer_1(i+16), or buffer_2(i)/buffer_2(i+16) are output depending on the realign0(i) and realign1(i) control signals. When recal(i)=1, the data bits are driven from two columns. The first one, i.e. bit tdat(i+16) is determined by realign0(i) and realign1(i), while the second one, i.e. bit_tdat(i) is the next one. For instance, when realign0(i)=realign1(i)=1, data bits are driven by buffer_2(i+16) and by buffer_3(i), so that there is a half cycle delay.
In summary, the behavior of the alignment block 18, on the first cycle, realign1(i) is modified and if a second realignment cycle is required, realign1(i) is copied to give realign0(i) and then modified with the new values. Not to disturb the data flow, the recal and realign signals are put in temporary buffers during computation and are taken into account only when the enable_test signal goes low.
In the present implementation, the deskewing/alignment mechanism can be used with a double edge clock running between 311 and 400 Mbits/s, which is equivalent to a 622 Mbits/s to 800 Mbits/s range. It will be apparent to those skilled in the art that various modifications may be made in the process and products illustratively described therein, without departing from the spirit or scope of the invention as expressed in the following claims.