Graphene Wireless Network-on-Chip
Albert Cabellos, Universitat Politècnica de Catalunya, Spain
Modern Systems-on-Chip (SoCs) today contains hundreds of Intellectual Properties (IPs)/cores, including, programmable processors, co-processors, accelerators, application-specific IPs, peripherals, memories, reconfigurable logic, and even analog blocks. We are now entered in the so called many-core era. The International Technology Roadmap for Semiconductors foresees that the number of Processing Elements (PEs) that will be integrated into a SoC will be in the order of thousand within the 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The Network-on-Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, and integration of large number of PEs on a chip.
The goal of the workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of many-core systems-on-chip. This workshop will focus on issues related to design, analysis and testing of on-chip networks. We also look for new type of NoC-based computing paradigms inspired by biological systems to solve hard computational problems such as learning, recognition, and complex decision making.