Part 1 of this blog covered International Technology Roadmap for Semiconductors (ITRS) updates to System Drivers, Design, Modeling and Process Simulation, Process-Integration Device and Structures (PIDS), and Front-End Processing, as presented in a session on the last day of SEMICON/West 2013.
SEMATECH’s Mark Neisser provided a sobering overview of the challenges associated with extending Lithography technology to pattern device structures below a half-pitch of 20nm. The ITRS Lithography International Technology Working Group (ITWG) works with pitch and half-pitch ranges as lithographically determined and so do not have an exact correspondence to “nodes.” ArF light sources at 193nm wavelength have been extended as far as possible using immersion, and all so-called “next-generation lithography” (NGL) technologies have problems, such that it’s unsure if any will be ready at the decision points needed insertion into future chip-making lines. Today, we can look at anticipated half-pitch ranges needed for proposed device structures and determine which proven technologies could be used:
- 30-20nm half-pitch is the limit of ArF Double-Patterning,
- 19-15nm half-pitch is estimated as the limit of EUV Single-Patterning,
- 14-11nm half-pitch is estimated as the limit of ArF Quadruple-Patterning, and
- 10-8nm half-pitch corresponds to the estimated limit of EUV Double-Patterning at the current NA.
“The industry needs an alternative to Quadruple-Patterning,” opined Neisser, “and the price-per-bit won’t necessarily go down.”
Front End Processes (FEP) needed for future chip-making were reviewed by Joel Barnett of Tokyo Electron. The FEP team is in flux, and Barnett solicited new team members. “Really what’s driving FEP these days is new materials for both logic and memory,” explained Barnett. New materials raise unpredictable integration challenges, for deposition, etch, cleaning, and metrology. We need to know the correlation between electrical properties and materials structures, and how can interfaces be engineered. Continued scaling of High-Performance finFET logic devices is challenging in all aspects: EOT, junctions, mobility enhancement, new channel materials, parasitic series resistance, and contact silicidation. Fin pitch has now been set by consensus with the PIDS and Lithography ITWGs to be 0.75 of M1 pitch.
Emerging Research Devices (ERD) that could replace standard CMOS FETs were discussed by An Chen of GLOBALFOUNDRIES with an emphasis upon novel memory technologies. One surprise was the removal of “nano-mechanical memory” from tracking in the main ERD table due to lack of progress. Resistive-RAM (RRAM) is now anticipated to move into commercial manufacturing in 2018, and the ERD ITWG plans to start tracking 4 different RRAM technologies in a new table: conductive-bridge RAM (CBRAM), metal-oxide bipolar filament, metal-oxide unipoloar filament, and metal-oxide bipolar interface effect. Unlike conventional Flash many emerging memory devices need a “select device,” and while transistors provide the best performance 2-terminal devices are more easily scaled. On the logic side, ERD anticipates new devices with “learning capabilities” to be developed in the long-term such as neuromorphic chips.
Emerging Research Materials (ERM) that could be needed to integrate new functionalities into integrated circuits were shown by C. Michael Garner, now with Stanford and Garner Nanotechnology Solutions. Alternate-channel materials such as Ge and III-V compounds seem destined to be used in future CMOS, and the best results to date combine Ge pMOS with III-V nMOS. However, integration cost and complexity would be reduced if only one new material could be coaxed into use as the alternate-channel, and so there is continuing work on Ge nMOS and III-V pMOS transistors. Contacts are important for all new materials, so the engineering of atomic-interfaces will be critical for future devices.
“A few people have demonstrated that providing a very thin barrier counter-intuitively lowers contact resistance,” shared Garner.