are a technique used in Design For Test
. The objective is to make testing easier by providing a simple way to set and observe every flip-flop
in an IC
. A special signal called scan enable
is added to a design. When this signal is asserted, every flip-flop in the design is connected into a long shift register
, one input pin provides the data to this chain, and one output pin is connected to the output of the chain. Then using the chip's clock signal
, an arbitrary pattern can be entered into the chain of flips flops, and/or the state of every flip flop can be read out.
In a full scan design, Automatic test pattern generation is particularly simple. No sequential pattern generation is required - combinatorial tests, which are much easier to generate, will suffice. If you have a combinatorial test, it can be easily applied.
- Assert scan mode, and set up the desired inputs.
- De-assert scan mode, and apply one clock. Now the results of the test are captured in the target flip-flops.
- Re-assert scan mode, and see if the combinatorial test passed.
There are many variants:
- Partial scan: Only some of the flip-flops are connected into chains.
- Multiple scan chains: Two or more scan chains are built in parallel, to reduce the time to load and observe.
- Test compression: the input to the scan chain is provided by on-board logic