|Publication number||US7586363 B2|
|Application number||US 11/955,237|
|Publication date||Sep 8, 2009|
|Filing date||Dec 12, 2007|
|Priority date||Dec 12, 2007|
|Also published as||US20090153231, WO2009076137A1|
|Publication number||11955237, 955237, US 7586363 B2, US 7586363B2, US-B2-7586363, US7586363 B2, US7586363B2|
|Inventors||Feng Pan, Jonathan H. Huynh|
|Original Assignee||Sandisk Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (78), Non-Patent Citations (4), Classifications (7), Legal Events (4) |
|External Links: USPTO, USPTO Assignment, Espacenet|
Diode connected regulation of charge pumps
US 7586363 B2
A circuit including a charge pump and regulation circuitry is described. The output of the charge pump is connected to provide a first output signal that is connectable to drive a load. A diode is connected to provide a second output signal of lower voltage from the first output signal. The regulation circuitry is connected to the second output level and is connectable to the charge pump to regulate its output. The circuit also includes a current source connectable from the second line to ground, where control circuitry connects the current source to the second line when the first line is connected to the load.
1. A circuit, comprising:
a charge pump;
a first output signal connected to receive an output of the charge pump and connectable to a load through a first switch;
a first diode connected to provide a second output signal of lower voltage from the first output signal;
regulation circuitry connected to receive the second output signal and connectable to the charge pump to regulate the output thereof;
a second switch coupled to receive the second output signal; and
a current source connected between the second switch and ground; and
whereby the second switch connects the current source to receive the second output signal in response to the connection of the first switch to the load.
2. The circuit of claim 1
, further comprising:
a second diode connected to allow current to flow from the second output signal to the first output signal.
3. The circuit of claim 1, wherein the first diode is a diode connected transistor.
4. The circuit of claim 1
, further comprising:
a capacitor connected between the second output signal and ground.
5. The circuit of claim 1
, further comprising:
a capacitor connected between the first output signal and ground.
6. The circuit of claim 1, wherein the load is a capacitive load.
7. The circuit of claim 1, wherein the second switch disconnects the current source from the second output signal based in response to the second output signal reaching a predetermined level.
8. The circuit of claim 1, wherein the circuit is a non-volatile memory circuit and said charge pump, first diode, regulation circuitry, a switch and current source are formed as peripheral circuitry thereupon.
9. A method of operating a circuit including a charge pump and a regulator connectable to the charge pump to regulate an output thereof, the method comprising:
providing the output of said charge pump as a first output signal therefrom to a load through a first switch;
connecting said output of the charge pump to a first diode and deriving as output therefrom a second output signal of lower voltage than the first output signal;
supplying the second output signal as input to the regulator to regulate the output of the charge pump in response thereto;
connecting the first output signal to the load using said first switch; and
in response to connecting the first output signal to the load, enabling a current source between the second output signal and ground using a second switch.
10. The method of claim 9, wherein the circuit further includes a second diode connected to allow current to flow from the second output signal to the first output signal.
11. The method of claim 9, wherein the first diode is a diode connected transistor.
12. The method of claim 9, wherein the circuit further includes a capacitor connected between the second output signal and ground.
13. The method of claim 9, wherein the circuit further includes a capacitor connected between the first output signal and ground.
14. The method of claim 9, wherein the load is a capacitive load.
15. The method of claim 9, wherein second switch disconnects the current source in response to the second output signal reaching a predetermined level.
16. A method of operating a charge pump, comprising:
deriving from an output of the charge pump a second output of lower voltage using a diode;
regulating the output of the charge pump based on the second output using a regulator;
connecting the output of the charge pump to a load using a first switch; and
in response to connecting the output of the charge pump the load, connecting a current source connected between the second output and ground using a second switch.
17. The method of claim 16, wherein the current source is enabled based on a signal controlling the connection of the output of the charge pump to the load.
18. The method of claim 16, wherein the current source is disabled in response to the second output reaching a predetermined level.
FIELD OF THE INVENTION
This invention pertains generally to the field of charge pumps and more particularly regulation charge pumps using a diode connected regulation scheme.
Charge pumps use a switching process to provide a DC output voltage larger than its DC input voltage. In general, a charge pump will have a capacitor coupled to switches between an input and an output. During one clock half cycle, the charging half cycle, the capacitor couples in parallel to the input or power supply voltage so as to charge up to the input voltage. During a second clock cycle, the transfer half cycle, the charged capacitor couples in series with the input voltage so as to provide an output voltage twice the level of the input voltage. This process is illustrated in FIGS. 1 a and 1 b.In FIG. 1 a, the capacitor 5 is arranged in parallel with the input voltage VIN to illustrate the charging half cycle. In FIG. 1 b, the charged capacitor 5 is arranged in series with the input voltage to illustrate the transfer half cycle. As seen in FIG. 1 b, the positive terminal of the charged capacitor 5 will thus be 2*VIN with respect to ground.
Charge pumps are used in many contexts. For example, they are used as peripheral circuits on flash memory and other non-volatile memories to generate many of the needed operating voltages, such as programming or erase voltages, from a lower power supply voltage. A number of charge pump designs are known in the art and these use a regulation scheme to provide the desired output level. As the accuracy of the output can be important for the application in which it is being used, and as the accuracy of the output level depends on the regulation of the charge pump, there are consequently often needs to improve the ability of the regulation to track the output level.
SUMMARY OF THE INVENTION
In an exemplary embodiment, a circuit including a charge pump and regulation circuitry is described. The output of the charge pump is connected to provide a first output signal that is connectable to drive a load. A diode is connected to provide a second output signal of a lower voltage from the first output signal. The regulation circuitry is connected to the second output level and is connectable to the charge pump to regulate its output based on the second voltage. The circuit also includes a current source connectable from the second line to ground, where control circuitry connects the current source to the second line when the first line is connected to the load.
Various aspects, advantages, features and embodiments of the present invention are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail.
BRIEF DESCRIPTION OF THE DRAWINGS
The various aspects and features of the present invention may be better understood by examining the following figures, in which:
FIG. 1 a is a simplified circuit diagram of the charging half cycle in a generic charge pump.
FIG. 1 b is a simplified circuit diagram of the transfer half cycle in a generic charge pump.
FIG. 2 is a top-level block diagram for a regulated charge pump.
FIG. 3 shows a charge pump arrangement to generate two different voltage levels through a diode-connected transistor.
FIG. 4 shows a non-ideal recovery case when a load is driven.
FIG. 5 shows an ideal recovery case when a load is driven.
FIG. 6 shows an exemplary embodiment of a charge pump arrangement to generate two different voltage levels through a diode-connected transistor that incorporates improvements described.
In charge pump arrangements where two different voltage levels are generated through a diode-connected transistor and the regulation is from the bottom branch, the level of the upper branch can result in a lower regulated level and slow recovery when the load is connected to top branch.
FIG. 2 is a top-level block diagram of a typical charge pump arrangement. As shown in FIG. 201, the charge pump 201 has as inputs a clock signal and a voltage Vreg and provides an output Vout. The voltage Vreg is provided by the regulator 203, which has as inputs a reference voltage Vref and Vout. The regulator block 203 regulates the value of Vreg such that k*Vout=Vref, where, by adjusting the value of k, the desired value of Vout can be obtained. The value k can be implemented as, for example, a resistor ratio and is typically adjusted through a digital to analog converter, as will be familiar in the art. (Although not shown, the regulator (203) will also be connected to receive the voltage Vext from the external power supply to the chip. Regulator 203 can take other supply voltages, not just Vext.
Vref is a fixed reference value, such as provided by band-gap generator (not shown) with a voltage of, say, 1.2 volts. Clock_High is a clock (not shown) input to the Pump 201.
More information on prior art charge pumps that can be used for charge pump 201, as well as for those in FIGS. 3 and 6, such Dickenson type pumps and charge pumps generally, can be found, for example, in “Charge Pump Circuit Design” by Pan and Samaddar, McGraw-Hill, 2006, or “Charge Pumps: An Overview”, Pylarinos and Rogers, Department of Electrical and Computer Engineering University of Toronto, available on the webpage “www.eecg.toronto.edu/˜kphang/ece1371/chargepumps.pdf”. Other example that can be used can be found in U.S. Pat. Nos. 5,436,587; 6,370,075; 6,922,096; and 7,135,910; and applications Ser. No. 10/842,910 filed on May 10, 2004; Ser. No. 11/295,906 filed on Dec. 6, 2005; Ser. No. 11/303,387 filed on Dec. 16, 2005; Ser. No. 11/497,465 filed on Jul. 31, 2006; Ser. No. 11/523,875 filed on Sep. 19, 2006; an application entitled “Low Voltage Charge Pump with Regulation”, by Feng Pan, Jonathan H. Huynh and Qui Vi Nguyen, filed concurrently with the present application; and Ser. No. 11/845,903 and Ser. No. 11/845,939, both filed Aug. 28, 2007.
FIG. 3 shows a charge pump connected to generate two different voltage levels through a diode-connected transistor. The output of charge pump 301 is connected to a first line 331 to supply a first output voltage VTOP, corresponding to Vout in FIG. 2. A switch SW 325 schematically indicates the ability to connect VTOP to drive a load, here indicated as a capacitive load Cload 323. This load could correspond, for example, to some high voltage switches to pass VBOT voltage.
The arrangement of FIG. 3 also provides a second output level VBOT along line 333. The second output level VBOT is offset relative VTOP by an offset voltage (the threshold voltage of diode) to place it at a lower level. In the exemplary embodiment, this is effected by placing a diode D1 311 having a voltage drop of VT so that VTOP=VBOT+VT. The diode can be implemented in the various ways familiar to those in the art, such as BJT or CMOS versions. In the example, D1 311 is a diode connected NMOS whose threshold voltage is VT. The exemplary embodiment also includes the additional diode D2 313, allowing current to flow back to 331 should its level drop low enough, and a capacitor C1 321 connected between 333 and ground to store charge for the second output on 333.
The ability to provide two output voltages as in FIG. 3 can be quite useful in a number of applications where charge pumps are used. The derivation of one of these outputs from the other allows the relative difference between these two be maintained at a more or less fixed amount, at least when these voltages are in equilibrium. For example, in the operation of off non-volatile memories, there are often cases where two voltages levels offset by a given amount are needed, such as in the operation of a NAND-type chain structure of memory cells where a Vpass, or pass voltage, is applied to non-selected word lines and needs to raised relative the selected word lines. (Memory devices with such NAND chain structures are described in U.S. Pat. Nos. 5,570,315, 5,903,495, 6,046,935.) As the amount of need offset between VTOP and VBOT will be dependent upon the devices to which they are supplied, using a similarly formed device, such as a diode connected transistor, can closely match the appropriate amount of voltage offset to pass the voltage. Of course, two separate charge pump circuits could be used to provide the two levels VTOP and VBOT, but this would increase the amount of circuitry and complexity and the two levels may not track each other by the desired voltage difference. Using one pump 301 with a single regulation 303 and a device formed from the appropriate technology, here the diode connected transistor 311, to provide the voltage offset between the levels consequently has a number of advantages. Although only two levels are shown in FIG. 3 (and, below, in FIG. 6), additional levels could similarly be provided.
In FIG. 3, the regulation circuitry 303 is connected to receive the second, lower output voltage VBOT, which is the typical arrangement. Although the regulation could be based on both of VTOP and VBOT, this would introduce additional circuitry and complexity. Alternately, the regulation could be based on VTOP alone; however, as VBOT is often more critical in term of accuracy in design, it is usually preferred to directly regulate off of the lower VBOT value, with the VTOP value being indirectly regulated. Consequently, when a load (not shown) is driven by the second output on 333, the regulation 303 will respond to any drop in the value of VBOT. When load Cload 323 is is driven by VTOP by closing of SW 325, the regulator 303 will respond only to the extent to which any change in VTOP is reflected in VBOT. This response to a drop in VTOP is, under the arrangement of FIG. 3, typically less than ideal.
In the arrangement of FIG. 3, as the regulation is based on VBOT, a dip in VTOP will often not be reflected in VBOT. More specifically, for the arrangement of FIG. 3, the waveform of VTOP in response to a load can be divided into 2 cases: In a first case, if the VTOP drop is still above VBOT-Vt, Vtop will stuck at a lower level after switching, and only start to recover after VBOT is out of regulation. In the second case, if VTOP drop below VBOT-Vt, then VBOT will be out of regulation by default and exhibit a dip, resulting in the VBOT and VTOP (as VBOT is only brought up by raising VTOP) being brought back to the desired level.
FIG. 4 shows the non-ideal recovery for this first case once Cload is connected to VTOP at a time indicated by t. As shown, the level on VTOP 405 takes a dip as the load is connected; however, under the arrangement of FIG. 3, this dip is not reflected in VBOT 407, which maintains its level after the dip at t. As the regulation is based on VBOT, the pump will only turn on and off based on VBOT; and as VTOP has not dropped far enough (to below VBOT-VT) to take also VBOT out of regulation, VTOP could stay at this level indefinitely. Only once VBOT 407 falls out of the desired range, such as when a load is also attached there, and will both level begin to be pumped. This is shown at a time indicated by t′. Only once VBOT dips will the pump begins to pull both VBOT and VTOP back up.
FIG. 5 illustrates an ideal recovery case once Cload 323 is connected. As shown, VTOP 505 and VBOT 507 are initially at their more or less desired level, separated by VT. At a time again indicated by t, Cload is connected to VTOP, causing VTOP to dip. In order for the regulation circuitry to be aware of this dip and cause the pump to quickly restore the VTOP level, the input to the regulator, namely VBOT, should also dip as VTOP dips. Under the arrangement of FIG. 3, however, the recovery is the non-ideal behavior shown in FIG. 4.
FIG. 6 shows several aspects of an exemplary embodiment allowing the indirect regulation of VBOT to more closely resemble the ideal recovery of FIG. 5 by inducing a dip in VBOT 507 at time t when Cload is connected to VTOP.
FIG. 6 again includes charge pump 601 providing a first output level VTOP along line 631 to a load Cload 623 through switch SW 625 and also providing a second output level VBOT by way of diode D1 611 along line 633, from which the regulator circuitry 603 takes its input. The optional, but commonly preferred, elements C1 621 and D2 613 are again included. It is again noted that although D2 613 allows current to flow from 633 to 631, in the case of a dip in VTOP, the drop may not be large enough to case any flow through D2 613; and even if these is some flow, this may not cause enough of a drop in VBOT to turn on the pump in terms of the recovery time specification for VTOP.
To help resolve the problems described with respect to FIG. 4, FIG. 6 adds a current source Idummy 651 that is enabled and connected to VBOT though a switch SW2 653 (control circuitry not shown) when a load is connected to VTOP. This causes VBOT to fall below the regulation threshold, thus enabling the pump 601 to turn on and charge up VTOP. The current source 651 can realized in any of the standard form for such pull-down elements will have feedback so that it can be turned off after VBOT is brought back up to its value. The control circuitry can enable and/or connect the current source 651 based upon the same control signal used to enable the switch SW 625 or otherwise in response to determining that the load has connected. This arrangement can be particularly useful when VBOT has capacitive regulation. The exemplary embodiment also adds a pool capacitor Cpool 655 connected between 631 and ground. This can help to reduce noise on VBOT to prevent accidentally turn off PUMP 601 before VTOP reaches regulation.
Although the invention has been described with reference to particular embodiments, the description is only an example of the invention's application and should not be taken as a limitation. Consequently, various adaptations and combinations of features of the embodiments disclosed are within the scope of the invention as encompassed by the following claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3697860||Mar 15, 1971||Oct 10, 1972||Westinghouse Electric Corp||Dc static switch circuit with a main switch device and a power sharing circuit portion|
|US4511811||Feb 8, 1982||Apr 16, 1985||Seeq Technology, Inc.||Charge pump for providing programming voltage to the word lines in a semiconductor memory array|
|US4583157||Feb 8, 1985||Apr 15, 1986||At&T Bell Laboratories||Integrated circuit having a variably boosted node|
|US4636748||Jun 26, 1985||Jan 13, 1987||Data General Corporation||Charge pump for use in a phase-locked loop|
|US4736121||Aug 18, 1986||Apr 5, 1988||Sos Microelettronica S.p.A.||Charge pump circuit for driving N-channel MOS transistors|
|US4888738||Jun 29, 1988||Dec 19, 1989||Seeq Technology||Current-regulated, voltage-regulated erase circuit for EEPROM memory|
|US5392205||Nov 7, 1991||Feb 21, 1995||Motorola, Inc.||Regulated charge pump and method therefor|
|US5436587||Nov 24, 1993||Jul 25, 1995||Sundisk Corporation||Charge pump circuit with exponetral multiplication|
|US5508971||Oct 17, 1994||Apr 16, 1996||Sandisk Corporation||Programmable power generation circuit for flash EEPROM memory systems|
|US5563779||Dec 5, 1994||Oct 8, 1996||Motorola, Inc.||Method and apparatus for a regulated supply on an integrated circuit|
|US5563825||Jun 7, 1995||Oct 8, 1996||Sandisk Corporation||Programmable power generation circuit for flash eeprom memory systems|
|US5568424||Jun 7, 1995||Oct 22, 1996||Sandisk Corporation||Programmable power generation circuit for flash EEPROM memory systems|
|US5592420||Jun 7, 1995||Jan 7, 1997||Sandisk Corporation||Programmable power generation circuit for flash EEPROM memory systems|
|US5596532||Oct 18, 1995||Jan 21, 1997||Sandisk Corporation||Flash EEPROM self-adaptive voltage generation circuit operative within a continuous voltage source range|
|US5621685||Jun 7, 1995||Apr 15, 1997||Sandisk Corporation||Programmable power generation circuit for flash EEPROM memory systems|
|US5625544||Apr 25, 1996||Apr 29, 1997||Programmable Microelectronics Corp.||Charge pump|
|US5693570||Nov 18, 1996||Dec 2, 1997||Sandisk Corporation||Process for manufacturing a programmable power generation circuit for flash EEPROM memory systems|
|US5969565||May 19, 1997||Oct 19, 1999||Nec Corporation||Voltage booster circuit|
|US5973546||Jun 8, 1998||Oct 26, 1999||Advanced Micro Devices, Inc.||Charge pump circuit architecture|
|US6018264||Jul 31, 1998||Jan 25, 2000||Lg Semicon Co., Ltd.||Pumping circuit with amplitude limited to prevent an over pumping for semiconductor device|
|US6023187||Dec 23, 1997||Feb 8, 2000||Mitsubishi Semiconductor America, Inc.||Voltage pump for integrated circuit and operating method thereof|
|US6026002||Sep 28, 1998||Feb 15, 2000||Siemens Aktiengesellschaft||Circuit configuration for supplying an electronic load circuit|
|US6134145||Aug 3, 1998||Oct 17, 2000||Sandisk Corporation||High data rate write process for non-volatile flash memories|
|US6154088||Aug 5, 1998||Nov 28, 2000||Micron Technology, Inc.||Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit|
|US6198645||May 28, 1999||Mar 6, 2001||National Semiconductor Corporation||Buck and boost switched capacitor gain stage with optional shared rest state|
|US6249898||Jun 30, 1998||Jun 19, 2001||Synopsys, Inc.||Method and system for reliability analysis of CMOS VLSI circuits based on stage partitioning and node activities|
|US6314025||Sep 27, 2000||Nov 6, 2001||Sandisk Corporation||High data rate write process for non-volatile flash memories|
|US6329869||May 17, 2000||Dec 11, 2001||Nec Corporation||Semiconductor device with less influence of noise|
|US6344959||Apr 30, 1999||Feb 5, 2002||Unitrode Corporation||Method for sensing the output voltage of a charge pump circuit without applying a load to the output stage|
|US6344984||Sep 1, 2000||Feb 5, 2002||Nec Corporation||Voltage multiplier having an intermediate tap|
|US6370075||Jun 29, 1999||Apr 9, 2002||Sandisk Corporation||Charge pump circuit adjustable in response to an external voltage source|
|US6404274||Apr 9, 1999||Jun 11, 2002||Kabushiki Kaisha Toshiba||Internal voltage generating circuit capable of generating variable multi-level voltages|
|US6424570||Jun 26, 2001||Jul 23, 2002||Advanced Micro Devices, Inc.||Modulated charge pump with uses an analog to digital converter to compensate for supply voltage variations|
|US6445243||May 10, 2001||Sep 3, 2002||Sanyo Electric Co., Ltd.||Charge-pump circuit and control method thereof|
|US6456170||Mar 30, 2000||Sep 24, 2002||Fujitsu Limited||Comparator and voltage controlled oscillator circuit|
|US6486728||Mar 16, 2001||Nov 26, 2002||Matrix Semiconductor, Inc.||Multi-stage charge pump|
|US6518830||Aug 21, 2001||Feb 11, 2003||Stmicroelectronics S.R.L.||High efficiency electronic circuit for generating and regulating a supply voltage|
|US6525949||Dec 22, 2000||Feb 25, 2003||Matrix Semiconductor, Inc.||Charge pump circuit|
|US6531792||Aug 3, 2001||Mar 11, 2003||Fujitsu Limited||DC-DC converter and storage apparatus|
|US6556465||Mar 27, 2002||Apr 29, 2003||Sandisk Corporation||Adjustable circuits for analog or multi-level memory|
|US6577535||Feb 16, 2001||Jun 10, 2003||Sandisk Corporation||Method and system for distributed power generation in multi-chip memory systems|
|US6606267||Oct 18, 2001||Aug 12, 2003||Sandisk Corporation||High data rate write process for non-volatile flash memories|
|US6724241 *||Jan 27, 2003||Apr 20, 2004||Atmel Corporation||Variable charge pump circuit with dynamic load|
|US6734718||Dec 23, 2002||May 11, 2004||Sandisk Corporation||High voltage ripple reduction|
|US6760262||Mar 4, 2003||Jul 6, 2004||Sandisk Corporation||Charge pump circuit adjustable in response to an external voltage source|
|US6798274||Mar 27, 2003||Sep 28, 2004||Sanyo Electric Co., Ltd.||Booster and imaging device using booster|
|US6834001||Sep 16, 2002||Dec 21, 2004||Sanyo Electric Co., Ltd.||Multi-stage switched capacitor DC-DC converter|
|US6859091||Sep 18, 2003||Feb 22, 2005||Maxim Integrated Products, Inc.||Continuous linear regulated zero dropout charge pump with high efficiency load predictive clocking scheme|
|US6891764 *||Apr 11, 2003||May 10, 2005||Intel Corporation||Apparatus and method to read a nonvolatile memory|
|US6922096||Aug 7, 2003||Jul 26, 2005||Sandisk Corporation||Area efficient charge pump|
|US6944058||Jun 13, 2003||Sep 13, 2005||Sandisk Corporation||High data rate write process for non-volatile flash memories|
|US6975135||Dec 10, 2002||Dec 13, 2005||Altera Corporation||Universally programmable output buffer|
|US6990031||Aug 29, 2002||Jan 24, 2006||Elpida Memory, Inc.||Semiconductor memory device control method and semiconductor memory device|
|US7023260||Jun 30, 2003||Apr 4, 2006||Matrix Semiconductor, Inc.||Charge pump circuit incorporating corresponding parallel charge pump stages and method therefor|
|US7030683||May 10, 2004||Apr 18, 2006||Sandisk Corporation||Four phase charge pump operable without phase overlap with improved efficiency|
|US7113023||Jun 21, 2005||Sep 26, 2006||Sandisk Corporation||Area efficient charge pump|
|US7116155||Mar 26, 2004||Oct 3, 2006||Sandisk Corporation||High voltage ripple reduction and substrate protection|
|US7120051||Dec 14, 2004||Oct 10, 2006||Sandisk Corporation||Pipelined programming of non-volatile memories using early data|
|US7135910||Feb 28, 2005||Nov 14, 2006||Sandisk Corporation||Charge pump with fibonacci number multiplication|
|US7227780||Nov 30, 2005||Jun 5, 2007||Spansion Llc||Semiconductor device and control method thereof|
|US7239192 *||Aug 4, 2004||Jul 3, 2007||Stmicroelectronics Sa||Self-reparable device to generate a high voltage, and method for repairing a device to generate a high voltage|
|US7276960||Jul 27, 2005||Oct 2, 2007||Dialog Semiconductor Gmbh||Voltage regulated charge pump with regulated charge current into the flying capacitor|
|US7397677||Feb 8, 2006||Jul 8, 2008||National Semiconductor Corporation||Apparatus and method for charge pump control with adjustable series resistance|
|US20050248386||May 10, 2004||Nov 10, 2005||Sandisk Corporation||Four phase charge pump operable without phase overlap with improved efficiency|
|US20060114053||Nov 8, 2005||Jun 1, 2006||Renesas Technology Corp.||Charge-pump-type power supply circuit|
|US20070001745||Aug 30, 2005||Jan 4, 2007||Chih-Jen Yen||Charge pump for generating arbitrary voltage levels|
|US20070126494||Dec 6, 2005||Jun 7, 2007||Sandisk Corporation||Charge pump having shunt diode for improved operating efficiency|
|US20070139099||Dec 16, 2005||Jun 21, 2007||Sandisk Corporation||Charge pump regulation control for improved power efficiency|
|US20070139100||Dec 16, 2005||Jun 21, 2007||Sandisk Corporation||Voltage regulation with active supplemental current for output stabilization|
|US20070229149||Mar 30, 2006||Oct 4, 2007||Sandisk Corporation||Voltage regulator having high voltage protection|
|US20080024096||Jul 31, 2006||Jan 31, 2008||Sandisk Corporation||Hybrid charge pump regulation|
|US20080157852||Dec 29, 2006||Jul 3, 2008||Sandisk Corporation||Unified voltage generation apparatus with improved power efficiency|
|US20080157859||Dec 29, 2006||Jul 3, 2008||Sandisk Corporation||Unified voltage generation method with improved power efficiency|
|US20080239802||Mar 30, 2007||Oct 2, 2008||Tyler Thorp||Device with Load-Based Voltage Generation|
|US20080239856||Mar 30, 2007||Oct 2, 2008||Tyler Thorp||Method for Load-Based Voltage Generation|
|EP0382929A2||Dec 15, 1989||Aug 22, 1990||Kabushiki Kaisha Toshiba||Voltage regulator circuit|
|EP0780515A1||Dec 20, 1996||Jun 25, 1997||BWG Butzbacher Weichenbau GmbH||Device for holding down a rail|
|WO2001006336A1||Jul 11, 2000||Jan 25, 2001||Maxim Integrated Products||Pulse frequency operation of regulated charge pumps|
|1||Ang et al., "An On-Chip Voltage Regulator Using Switched Decoupling Capacitors," 2000 IEEE International Solid-State Circuits Conference, 2 pages.|
|2||Feng Pan et al., "Charge Pump Circuit Design", McGraw-Hill, 2006, 26 pages.|
|3||Louie Pylarinos et al., "Charge Pumps: An Overview", Department of Electrical and Computer Engineering University of Toronto, 7 pages.|
|4||Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or Declaration, Application No. PCT/US2008/085429, mailed Feb. 24, 2009, 15 pages.|
|Feb 6, 2013||FPAY||Fee payment|
Year of fee payment: 4
|May 13, 2011||AS||Assignment|
Effective date: 20110404
Owner name: SANDISK TECHNOLOGIES INC., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK CORPORATION;REEL/FRAME:026276/0908
|Nov 3, 2009||CC||Certificate of correction|
|Jan 8, 2008||AS||Assignment|
Owner name: SANDISK CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PAN, FENG;HUYNH, JONATHAN H.;REEL/FRAME:020335/0659
Effective date: 20071211