High Performance Physical Design of a 28nm Quad-Core ARM Cortex-A15 with 4MB L2 Cache
This presentation was delivered by Jason Karka and Michael Robinson of Texas Instruments at Austin SNUG 2012. It highlights key strategies used in a Synopsys IC Compiler place-and-route flow for a 28nm quad-core ARM® Cortex-A15 processor. Various physical design techniques were used to obtain very High clock frequencies. Many of these tactics will be of use not only to designers implementing quad-core A15 processors, but also to those designing other 28nm high performance chips. Topics discussed include net patterning and layer assignment to deal with a tapered metal stack, hierarchical partitioning, placement density and clustering, clock gate cloning, useful skew, logic-level balanced CTS, and techniques for post-route setup and hold closure.