Obtain a timing diagram for a positive-edge-triggered JK master-slave flip-flop during four clock pulses. Show the timing diagrams for C, J, K, Q and Q’. Assume that before the first pulse: output Q is equal to 1, J=0 and K=1. Then, after the second clock pulse, J=1 and K=0. After the third clock pulse J=1 and K=1.