According to briefing materials supplied by Crossbar, the memory is based on a silver top electrode over amorphous silicon over a polysilicon bottom electrode. The principle of operation is that a writing voltage causes silver ions to migrate through the silicon to form a filament that eventually can connect the top and bottom electrodes. A reverse voltage causes the ions to move and break the connection. Lower voltages can be used to "read" the connection as a 1 or 0.
There are some similarities to the programmable metallization cell technology licensed to Adesto Technologies Corp. and others and being brought to market under the term conductive bridging RAM or CBRAM. (See: Altis upgrades embedded non-volatile memory.)
Crossbar's demonstration array is substantial at a size of 1K by 1K, and was fabricated in a commercial wafer fab using a 110-nm minimum geometry, Minassian said. He declined to name the fabricator. However, the company also has experience of making devices at geometries below 30nm and the filaments are thought to be less than 10nm in diameter, Minassian added.
Voltages are modest, all below about 3.5 volts, and scale with geometry, Minassian said. The performance claims for the memory include 20 times faster write, 20 times lower power consumption, and 10 times the endurance of contemporary NAND flash memory. The read latency is about 20ns. The retention and endurance are tunable to a degree but Crossbar is quoting 10 years and 1 million cycles of endurance at sub-10nm geometry.
An inherent blocking diode within the cross-point structure also helps avoid "sneak-path" problems while reading bits and keep the device structure simple and potentially close to the 4F2 theoretical minimum cell size.
Memory layers can be stacked and processes are compatible with CMOS. Source: Crossbar Inc.
Other benefits include its simple construction, which means the memory is inherently capable of layered stacking -- and more easily than 3-D flash, which requires a tapered vertical channel.
Crossbar reckons that monolithic integration of up to eight memory layers on top of CMOS memory access circuitry should be "easy" and will allow multi-terabyte memory ICs. The company has already designed a memory controller circuit for a triple layer non-volatile memory as part of its development activity.
"We've developed the CMOS controller logic and put memory layers on top," said Minassian. The technology is also capable of multi-level cell configuration whereby multiple resistance points can be set and detected allowing multiple bits to be stored in a single cell.