Non-Volatile Storage for Mobile Phones, M Systems
By Veronica Mayfield
As we move into mobile computing platforms enabled by tomorrow's 3G and 4G phones, with features such as media messaging, video streaming and running third party applications, the memory requirements will escalate to hundreds of megabytes. This shift in emphasis is significantly stretching the demands being placed on non-volatile storage systems typically used in 2G phones such as battery backed SRAM or NOR flash (see Figs 1 & 2).
Fig. 1 Memory Sub-System in a 2G Phone
Going forward, the requirements for non-volatile storage in mobile phones can briefly be summarized as follows:
High capacity shift to 16-64Mbyte (128-512Mbits) and rising
Good read and write performance
Reduced power consumption
File based storage
Reduced physical size
Reduced system, bill of materials (BOM) and development costs
Fig. 2 Memory Sub-System in a 3G Phone
These requirements are effectively being driven on three fronts-users, manufacturers and operators. Users not only want smaller phones with longer battery life but also the performance to execute complex applications for both business and entertainment. Manufacturers, on the one hand, are looking to drive down their bill of materials. Yet, on the other hand, they are turning to increasingly complex operating systems with filing systems among other advanced features, which need to be booted and executed securely. It is expected that code and data are stored without error. From the operator perspective the issue of dropping average revenue per user (APRU) is well known and is leading them to offer more data centric services and features which are naturally storage hungry (more data and more applications = more revenue).
Mobile system designs are faced with a number of choices when looking for non-volatile storage solutions. The first is whether or not to separate code and data storage and, if so, whether to use different technologies for each or the same technology but separate devices. Separation is a more secure option and is a simple extension to conventional embedded memory solutions. For smaller systems, this works well and it offers advantages in development and production tooling. The downside is that it increases the device count which impacts costs, size and power consumption. The greater the required storage capacity, the greater the impact.
Several primary technology choices are available battery backed RAM, magnetic media, NOR flash, NAND flash and disk-on-chip.
Battery backed RAM provides high-speed random read-write access; it tends to be expensive, large and requires continuous power. Although the technology has been used successfully in many PDAs, the devices tend to be large and heavy from a user perspective and needs charging every day to ensure data isn't lost. Magnetic media is another possible option, especially where larger amounts of storage are required. Small hard disks are available but they are currently somewhat large even for PDAs and have really only successfully found their way into portable embedded systems such as data loggers. Consequently both technologies tend to be discounted for the mobile phone market.
NOR flash is a popular choice. It is a reliable technology with a long track history in embedded systems predominantly for code storage and designers are very familiar with it. The electrical interface is well understood, being based on address and data buses (see Fig. 3). No bit errors are introduced during the writing or reading operations so what you read is what you wrote! It offers good read performance with random access being possible enabling it to be used naturally for execute in place (XIP). Extending its use to storing user data would seen an apparently simple step but this is not actually the case as the processes involved are actually quite complex.
First, it is not possible to simply write the data to the NOR flash. The target location in the NOR flash device has to be erased before the data can be written. However, as NOR flash devices are organized internally as 'erase blocks,' erasing is not done on a byte-by-byte basis. Whole blocks have to be erased. This is fine for code storage as the whole device is typically erased and then reprogrammed. But it is a significant issue for data storage. To overwrite some data in a block, the whole block must be copied to an erased block replacing the old data with the new as the copy is made.
This is a time consuming process. Typically, erase times range from 100s of milliseconds to seconds for a block; reading a byte takes around 100ns, while writing a byte takes 10 to 20 microseconds per byte. One way to speed it up is to use an algorithm that can allow the identification of a newer version of an item of data. In such schemes, many items of data in a block can be superseded until a point is reached where this has happened to most of the data. At this point the good data is moved to another erased black and the old one is erased.
Frequently, an erase block is further divided into the programming blocks. When erased, all the bits are in a '1' state. Writing data only moves some bits to a '0' state. The remaining '1' bits can be written to at a later date but only to a '0' state. This is called partial programming. In this way, a block can be partially written a number of times. The actual number of times depends on the individual device.
NOR flash devices also have a limited life expectancy, which is a function of the number of times the device has been erased. Although, this is typically 100s of 1000s of cycles, the time taken to erase a block increases with every time it has been erased. When a device had reached its life expectancy, the time to erase a block will usually exceed the specification for erase time and they could also become unreliable. Therefore, to ensure devices are used to their maximum, the management algorithms should include wear leveling to ensure each erase block is aged at the same rate as other blocks.
NAND flash is a newer technology than NOR flash and, as such, unfamiliar to many system designers. The electrical interface is more like an I/O device than a memory device (see Fig 4). The storage cells are typically 40% smaller than those of NOR devices, enabling higher density storage in the same size device. Unlike NOR, NAND devices are not byte addressable and, due to their internal construction, less reliable. Internally, the cells are arranged in serially linked chains, typically in 512 bytes. These chains are further arranged into erase blocks.
Managing data storage on these devices is more complex than for NOR devices although some of the management is very similar. Cells must be erased before writing can take place. Erasing sets the cell to a '1' state and writing can only set the cell to the'0' state. Partial programming is also possible and devices have a limited lifetime requiring wear leveling.
To achieve 100% data reliability, algorithms must be put into place to detect (EDC) and correct (ECC) errors in data when read from the device. This will necessarily add an overhead to the read operations. However, there are some applications where 100% data reliability is not required. For example, bit errors can be tolerated when storing pictures or audio in fixed formats as there is no need to store any format or meta data. For this reason, NAND is used extensively in media cards. However, media card performance is usually limited by the interface to a card.
Typically with NAND devices, a read operation of 512 Mbytes takes 25 microseconds, a write of 512 bytes, 250 microseconds and a block erase operations, about 3 milliseconds.
NAND devices generally require significantly less power than NOR devices. During erase and write, the most power consuming operations, a NAND device requires a few microamps whereas a NOR device requires a few milliamps. The lower current utilization, together with the shorter operation times, gives NAND a significant power saving advantage over NOR. While a NAND device can be connected to the I/O bus, doing this would limit its performance. To remove this limit, a NAND controller could be used. However, this would be another device in the BOM or gate count in the ASIC, thus increasing costs.
The Growing Importance of Write Performance
In 2G handsets, write performance is not an important factor: Data storage requests are infrequent and small usually leaving plenty of time available to complete the operations. Consequently, both NOR and NAND flash generally satisfied their data storage requirements. In 3G and 4G handsets, write performance will effectively define the feel of the product, making the choice of non-volatile storage technology a critical factor in some handsets.
With applications that utilize database type operations such as contact management, calendar and messaging, when editing an entry or organizing the data, slow write operations will frustrate users leaving them waiting while the operation completes. Camera applications found on many handsets are writing 10s to 100s of blocks of data for each picture taken. To capture streaming images or sound, the sustained write performance of non-volatile storage can dictate the overall performance for these operations. The combination of the frame rate, color depth and frame size set and data rate. If this exceeds the sustained write performance of the storage device, then the streaming operation will be limited in one of a couple of ways. Either the frame attributes must be reduced or the data has to be streamed to system memory for a short period of time and then saved to non-volatile storage, thus limiting the streaming operation in duration and introducing a delay at the end of the streaming operation while the data is written.
Operating systems, filing systems and open standards encourage the exponential expansion of available applications with voracious appetites for resources. The operating context of any one application is no longer deterministic and depends upon the interactions between the operating system and other running applications. Due to their singularity within a system, key resources, such as screen storage, have to manage very carefully and must be optimized for performance. Slow handling of such resources no longer just affects the application utilizing that resource, but potentially many other applications.
As the device becomes full, writing new data becomes more difficult. In order to do this, the management system must make space. Because there may be a large amount of superceded data, the management system will have to garbage collect before the write can take place. Instead of this taking place in the background, it must happen before the write can complete, leading to a very long apparent write times when in actual fact, it is the combination of many erases and writes. Slow writes can make a handset unusable through sheer frustration.
A possible solution lies in the development of multi level cell (MLC) flash technology. NOR and NAND devices, for example, store one bit in each storage cell while MLC technologies store more than one bit in each cell. Currently, this is two bits per cell which doubles the storage for a given physical device size, thereby halving the cost per bit. But this is not without cost. Because of the manner in which the bits are stored, the error rate is significantly higher than equivalent single level cell technology. The data rate is also reduced due to the amount of control required to manage each cell and the partial write feature is removed. In view of this, it would be easy to question the validity of MLC in the mobile market. However, with the relentless drive to increase capacity and reduce costs, the cost per bit advantage of MLC makes a compelling case for its adoption. The other factors are simply new engineering challenges in a search of solutions.
The latest non-volatile storage solution for mobile devices is DiskOnChip technology. As the name suggests, many of the attributes associated with a disk are applied to flash storage (see Fig. 5). It uses the latest non-volatile storage media at its core, combined with a thin controller ensuring hardware interface compatibility and unmatched reliability. Currently, it is based on NAND as it is the most appropriate technology available for high capacity non-volatile storage at this time. The controller provides a standard NOR-like or multiplexed interface, compatible for most standard legacy designs. Based on TrueFFS technology for flash management, the controller also solves NAND error issues. M-Systems believes that DiskOnChip is the only device to date to support multi level cell NAND, making it a lower cost option than using standard NAND devices.
One of the main obstacles of using NAND as the only non-volatile storage solution is that is does not support XIP. Usually this requires an additional non-volatile device as a boot ROM (similar to a BIOS and hard disk approach of desktop machines). DiskOnChip provides a built-in XIP boot block, enabling it to be used as the sole non-volatile memory device in mobile devices and achieve further cost and BOM savings by eliminating the boot ROM all together.
Software integration is usually one of the main challenges for integrating flash as a disk-like device. The TrueFFS flash management and file system software is available to solve this on most mobile operating systems, such as Symbian OS, Microsoft OSs, Linux, Palm and many others, and offers a development kit for proprietary OSs or platforms.
With mobile handsets in mind, a deep power down mode reduces power consumption when not in use, and extends battery life.
With the increased demand for fast, reliable and high capacity on-board memory in today's 2.5G-3G handsets, and with size and cost limitations becoming even more critical, NAND flash and chip-based disks in particular are emerging as important technologies in on-board non-volatile storage solutions. The introduction of MLC NAND is a clear indication of the cost and size advantages of NAND over NOR are here to stay for quite some time. However, NOR flash will remain a key player in the voice-centric handset segment and many also have a place in other mobile applications.
Veronica Mayfield is a business development director with the mobile group of M-Systems Europe.