ARM Technical Support Knowledge Articles
Cortex-A9 Knowledge Articles
Knowledge Articles in this section
Cache and Write Buffer (1)
Reset and Initialization (1)
Accessing Cortex-A9MP's global timer causes abort
Can AXI-based ARM cores generate bursts across 1KB boundaries?
Cortex-A9 MPCore and Cortex-A5 MPCore SMP initialization example
Cortex-A9 MPCore cached Dhrystone examples
Cortex-A9 MPCore cached Dhrystone examples for Versatile Express
Cortex-A9 TrustZone example
How should cache maintenance operations be handled in systems with multi-level cache, with reference to DMA?
Performance Monitor Unit example code for ARM11 and Cortex-A/R
What is the pupose of ACP signals ARUSERS[4:0], AWUSERS[4:0] on Cortex-A9 MPCore ?
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