The "Chip 9" or "Log Gain (LG)" problem of the AtoM chip was
first observed in
Santa Barbara and then also in
Pisa/Milano. Briefly, the symptoms of the problem are:
Non-statistical correlated fluctuations in the threshold
turn-on curves under internal charge injection.
Reduced gain (hence the LG label).
Whether this is a real effect, or an artifact
of the poor measurements of the 50% threshold turn on
curves is not well understood
The problem occurs only on some, but not all, p-side chips.
It never occurs on the n-side.
Initially the problem was thought to be correlated with the location
on the HDI at chip ID=2 (ID=9 in the teststand software, hence the
chip 9 label). With better statistics we now know that
there is no such correlation.
The problem is not associated with the HDI, since it
has been replicated at LBL for a chip mounted on a test card.
The problem depends on the number of channels that are
fired simultaneusly, the value of the injected charge, and the
temperature of the HDI.
It has been hypothesized that the problem may be due to a problem
in the internal charge injection circuitry. This can be verified
by examining the behaviour under external charge injection. We
understand that members of the Pavia group will be performing
measurements by injecting charge through externally-bonded
capacitors. Here we report on measurements performed at
UCSB on a bonded detector using a focussed infrared LED source.
The measurements were performed on DFA D01B-6, bonded to HDI H1-18.
We performed a series of threshold scans both with internal charge
injection and using an LED pulser. The amount of charge deposited
via the LED was controlled by varying the length of the pulse
used to fire the LED. This length varied typically between 15 and
55 nsec; the risetime of the LED is of order 5 nsec.
The size of the LED spot on the detector was approximately 600 micron
(FWHM). All measurements
reported here used a 40 MHZ clock and a shaping time of 100 nsec.
In Figures 1 and 2 we show threshold turn-on curves
from internal charge injection
for a channel on
the n-side and a channel on the p-side.
Figure 1: Threshold turn-on curves under internal charge injection
for a channel on the n-side
(chip 3 chan 41) and a channel on the p-side (chip 9 chan 24).
These correspond to a charge injection of 2 CAL DAC counts and
firing 16 channels simultaneously.
Figure 2: Same as Figure 1, but firing 8 channels simultaneously.
The fact that chip 9 on the p-side is affected by the Chip 9/LG
problem in the run taken in Figure 2 is not immediately obvious.
In general, it is a little harder to spot the problem simply by inspecting
the threshold curves after bonding than it is before bonding (due
to the slow turn on in the curves after bonding).
However, the chisquared distributions for the error function fits are
a good way to spot the Chip 9/LG problem, see Figures 3 and 4.
Figure 3: Distribution of chisquared for the threshold turn
on curves of chip 3 (n-side) and chip 9 (p-side). These are for
charge injection of 2 CAL DAC counts and firing 16 channels simultaneously.
No (or little) evidence of Chip 9/LG problem.
Figure 4: Same as Figure 3, but for firing 8 channels
simultaneously. The Chip 9/LG problem
We now show in Figure 5 the chisquared distribution for threshold turn-on
curves obtained when externally injecting charge in the front end by
shining the infrared LED on the detector. Note that the statistics are
small because only a few channels per side were illuminated by the
LED. However, a wide range of charges was explored, see the caption
to Figure 5.
Figure 5: Distribution of chisquared for the threshold turn-on
curves of chip 3 (n-side) and chip 9 (p-side). These are for
charge injection using the infrared LED. The points here have been
accumulated in a number of different runs, where the LED intensity
was varied by varying the length of the LED pulse. The charge collected
ranged approximately between 1 and 3 fC.
There is no difference in the chi-squared distributions for chip 9 and
chip 3 in Figure 5. Therefore, at least for the one chip that
we studied, we conclude that there is no evidence of Chip 9/LG
problems when examining threshold turn-on curves under external
The other very serious manifestation
of the chip 9/LG problem is a (possibly) reduced gain. We can measure
the relative gain of all chips because we are able to control
the amount of deposited charge by varying the
length of the LED pulse. We appear to be operating in a
very linear region, see Figure 6. We are now analyzing
these data to determine whether the gain of chip 9 is
anomalously low. This work is not finished, but preliminary
results are very encouraging. Stay tuned.
Figure 6: Distribution of 50% threshold turn on point vs the
length of the LED pulse for two channels on the p-side. Note that
thresholds decrease bottom to top, i.e. THR DAC = 0 is the highest
threshold, THR DAC = 63 is the lowest threshold.
Channel 25 is at or near the maximum of the light intensity, channel
29 is further away, hence the difference in slopes.
(12 August 1998) Information on chip 9 / LG gains is now