Issue No.08 - August (1981 vol.30)
I. Shirakawa , Departrment of Electronic Engineering, Osaka University
The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multiphase clocking system, and occupies ordinarily a considerable part of chip area. In this paper a layout system for this portion of an LSI chip is described, which is constructed on the basis of heuristics for a set of interrelated optimization problems. Implementation results of the layout system are also shown to reveal that the random logic portion can be realized in such an areas as comparable to one done by manual layout.
random logic, Complex gate, computer-aided design (CAD), large-scale integration (LSI), layout, minimization of Boolean exeression, MOS ratioless circuit one-dimensional gate array problem
I. Shirakawa, N. Okuda, T. Harada, S. Tani, H. Ozaki, "A Layout System for the Random Logic Portion of an MOS LSI Chip", IEEE Transactions on Computers, vol.30, no. 8, pp. 572-581, August 1981, doi:10.1109/TC.1981.1675842