A capacitively-divided, injection-locked, ring oscillator is proposed that decreases dynamic power consumption by reducing voltage swing. A feedforward capacitor is placed in series with the load capacitance, effectively AC coupling each inverter stage to the next stage. Simulations are performed using digital programmability of the capacitor weights of both the feedforward and load capacitors, showing a reduction in the power consumption by as much as 36% with a 72% reduction in voltage swing. At the limits of reduced voltage swing, the power consumption is limited by static leakage current. Built in a 1.2V, 90nm CMOS process, the proposed capacitively-coupled, ring oscillator with digital trimming is injection-locked to an off-chip reference clock, with the measurement results verifying the correctness of the simulated performance.