|Optimizations for Pipelined Processors email@example.com (1993-01-21)|
|Re: Optimizations for Pipelined Processors firstname.lastname@example.org (1993-01-22)|
|Re: Optimizations for Pipelined Processors email@example.com (1993-01-22)|
|Re: Optimizations for Pipelined Processors firstname.lastname@example.org (1993-01-22)|
|From:||email@example.com (Mike Smith)|
|Date:||Fri, 22 Jan 1993 15:35:26 GMT|
firstname.lastname@example.org (Alon Ziv) asks about implementing
compiler back-ends for pipelined processors and (basically) about
|> So, the question is: _is_ there any research going on for these ideas? I
|> would assume that it has started, and---if so---would very much like to
|> have some references about progress so far, as it seems to be
|> (potentially, at least) VERY interesting.
Yes, lots. In the mid-1980s (during the research on RISC processors),
there was considerable work done on pipeline scheduling to basically
handle load delay slots, branch delay slots, and FP latencies. Today, the
work on pipeline scheduling has moved to the world of superscalar and
superpipelined processors (which require scheduling to get good
performance). There has been a lot of work, especially from Universities
like U. of Illinois (Wen-mei Hwu's project called IMPACT) and Stanford
(the TORCH project) and from research centers like IBM Israel (Bernstein
et al.) and IBM Watson (Ebcioglu et al) to name a few. A lot of this work
is similar to the VLIW work originally done by Fisher (Trace Scheduling)
and Nicolau (Percolation Scheduling).
You can find a lot of interesting papers by looking through the recent
proceedings from ASPLOS, ISCA, MICRO, and PLDI.
I just finished a Ph.D. dissertation that describes an architecture and
back-end scheduler for superscalar/superpipelined processors. This thesis
has a large background section and bibliography which you might find
interesting. My thesis is available via anonymous ftp from
velox.stanford.edu (126.96.36.199). Once you are in,
Hope you find it useful,
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