Electrical and Computer Engineering BOSTON UNIVERSITY
This homework assignment covers material primarily from Chapter 2 and Chapter 5 in the Kang and Leblebici textbook plus the class lecture notes. The assignment is due on Friday, Feb. 15, 2001 by 5:00 PM to Sulakshana Pasnoor (PHO313).
1. A transmission gate (shown below) is used to charge and discharge a load capacitor connected to Vout. The N and P switches have +5 and 0 volts on their gates, respectively. The N device has an electrical W/L = 2/1 and the P device has W/L = 4/1. Oxide capacitance is assumed to be 3.5 fF/um2 for both devices. The mobilities are given as 500 cm2/Vsec for the N-FET and 200 cm2/Vsec for the P-FET. Threshold voltages are determined as follows:
VTN = 0.424 + 0.625 [0.85 + Vsx]1/2 and VTP = -0.576 – 0.474 [0.80 + Vsw]1/2
where Vsx is source-to-substrate voltage and Vsw is source-to-well voltage.
Assume the input has risen to +5 volts and the X-gate is charging the capacitor. Find the (dc) resistance of the transmission gate for Vout = 0, 1, 2, 3, 4, and 5 volts. Sketch a plot of Rgate vs Vout. (20 pts)
2. Determine the appropriate regions of operation and derive the equations for the dc transfer characteristic of the saturated PMOS load inverter shown below. Write down expressions for the VOH and VOL of the circuit. Determine the (W/L)load required to obtain a VOL of 0.3 volt or less given the device parameters of question 1 above, VDD = 5 volts, and (W/L)active = 3/1. (Note: The quantitative data on the plot below does not apply specifically to this problem!) (20 pts)
Assume the NMOS and PMOS devices are to have effective electrical W/L ratios of 5/1 and 10/1, respectively. You may assume
Weff = Wmask - DW and Leff = Lmask - DL,
where DW = 0 and DL = 0.40 um. Please use color-coded mask levels as suggested in class (Brown=Nwell, Green=Nactive, Yellow=Pactive, Red=Poly, Blue=Metal1, etc.), or identify each mask level clearly with a label. (20 pts)
R. W. Knepper
Feb. 6, 2002