||Design of power amplifier requires a precise large-signal device model to accurately simulate large-signal performance and design impedance matching network. In this thesis, a measurement-based large-signal model, Root model, is extracted and utilized. DC and various large-signal simulations are performed to compare Root model and BSIM3.1 model with measured results. The comparison shows that Root model can give more accurate DC and large-signal simulations such as Pout and PAE and IMD3 than BSIM3.1 model. With the growing demand of high-speed transmission, modern wireless communication systems utilize more sophisticated digital modulations that usually generate signals with varying signal envelope. Therefore, linear transceiver is required to process these signals linearly to ensure integrity of data transmitted. Since power amplifier is the most nonlinear functional block in a transceiver, it has the most detrimental effect to signal distortion. With low cost device such as CMOS employed in power amplifier, linearity will be even worse. Therefore, low cost implementation of linear power amplifiers requires extra linearization techniques. In this thesis, a linearization technique called predistortion is applied to linearize a CMOS power amplifier operated in 5GHz. The predistorter consists of cascode devices that are suitably biased to obtain different gain expansion and phase variation for compensating the amplifier characteristics at subsequent stage. Unlike some passive predistorter in the literature, this structure provides gain and can work as the first stage of multistage power amplifier. Measurement shows that the predistorter can achieve +4dB gain expansion. The measured 1dB compression point of the power amplifier with predistorter is 3dB higher than that of conventional design. The measured output power and PAE are 11dBm and 10% respectively.