Issue No.02 - February (1980 vol.29)
K.W. Current , Department of Electrical Engineering, University of California
It is well known that multiple valued logic can theoretically provide a greater logical packing density than binary logic. In this correspondence, a useful quaternary logic arithmetic circuit is discussed in its combinational and synchronous sequential forms. The results of applying this circuit in proposed implementations of digital parallel counters are then compared to all-binary designs. A significant savings in integrated devices and thus increased packing density could be obtained in each case.
K.W. Current, "High Density Integrated Computing Circuitry with Multiple Valued Logic", IEEE Transactions on Computers, vol.29, no. 2, pp. 191-195, February 1980, doi:10.1109/TC.1980.1675542