Figure 1 shows a sample VHDL design, design_one.vhd, which illustrates component inference with the DesignWare interface for FLEX 8000 devices.
|Figure 1. VHDL Design File (design_one.vhd)|
| This design illustrates the sum of A + B.
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL;
ENTITY design_one IS PORT (a,b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); f : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END design_one;
ARCHITECTURE add_design OF design_one IS
BEGIN f <= a + b; END add_design;
When the VHDL Compiler or the HDL Compiler for Verilog software analyzes and elaborates the design, it replaces the "+" operator with its synthetic operator equivalent.
Figure 2 shows the design as it appears in the Design Analyzer software after it has been analyzed and elaborated by the VHDL Compiler software.
Figure 2. design_one.vhd after Analysis & Elaboration
When you synthesize a design, the Design Compiler or FPGA Compiler software uses the synthetic library to match the synthetic operator to the FLEX-optimized logical implementation in the technology library. The Synopsys Design Compiler or FPGA Compiler software then instantiates and interconnects the correct number of
flex_carry functions to produce the 8-bit adder shown in Figure 1. When you save a compiled design as a VHDL, Verilog HDL or EDIF file, the file preserves the number of
flex_carry functions, as well as their interconnections. Consequently, area and performance predictions that you make in the Synopsys design environment closely match the final
Table 2 lists functions included in the DesignWare FLEX 6000, FLEX 8000, and FLEX 10K synthetic libraries.
|Table 2. FLEX 6000, FLEX 8000, and FLEX 10K Synthetic Library Functions|
||Sum of A, B, and Carry-In|
|Carry of A, B, and Carry-In|
||Difference of A, B, and Borrow-In|
|Borrow of A, B, and Borrow-In|
|Greater than (|
|Greater than Carry|
|Less than (|
|Less than Carry|
|Greater than or equal to (|
|Greater than or equal to Carry|
||Incrementer (Count = Count + 1)|
|Incrementer Carry (Count = Count + 1)|
||Decrementer (Count = Count - 1)|
|Decrementer Carry (Count = Count - 1)|
|Less than or equal to (|
|Less than or equal to Carry|
Figure 3 shows design_one.vhd after it has been synthesized with the Design Compiler.
Figure 3. design_one.vhd Synthesized & Resolved for FLEX 6000, FLEX 8000 & FLEX 10K Architecture
After you save the design as an EDIF Input File (.edf) and process it with the MAX+PLUS II Compiler, the Compiler replaces instances of
flex_carry with FLEX-optimized versions, as shown in Figure 4. The MAX+PLUS II Compiler maps these functions into a single logic element (LE). The result is a high-speed 8-bit adder that fits into 8 LEs.
Figure 4. One Slice of the design_one 8-bit Adder Design with Optimized FLEX 8000 Functions
- Refer to the following sources for related information on DesignWare and the Synopsys VHDL Compiler:
- Synopsys DesignWare Databook
- VHDL Compiler Reference Manual
- Go to FLEX Devices, which is available on the web, for additional information.
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