Venice Core Innovations
Dual Stress Liner (DSL) Technology
Before we start talking about the new potential of the Athlon 64 processors in terms of clock rates, we have to pay due attention to those CPU features that made this frequency growth possible.
In the end of 2004 AMD and IBM announced another technological breakthrough in the transistor performance field. The technology jointly developed by the engineers from both companies called Dual Stress Liner allowed them to improve the response time of semiconductor transistors by 24%.
The idea behind this technology is fairly simple. In fact, Dual Stress Liner is very similar to strained silicon technology introduced by Intel together with their new 90nm production process. In other words, Dual Stress Liner implies the use of silicon with transformed atomic lattice so that the transistors made of it could boast faster response time and lower heat generation. In one case the silicon atoms are “stretched” and in another case – “squeezed” by moving them onto a nitride capping layer with either stretched or squeezed atomic lattice. Unlike strained silicon used by Intel, Dual Stress Liner from AMD and IBM can be used for both types of transistors: NMOS and PMOS (with n- and p-channels) without the use of exotic silicon-germanium layer, would add cost and possibly hurt the yield of the chips.
This twofold character of the Dual Stress Liner, makes it more efficient than Intel’s strained silicon. Dual Stress Liner allows improving the transistors speed by 24%, while the strained silicon provides the maximum improvement on only 15-20%. And what is also very important, the new technology from AMD and IBM doesn’t reduce the production yields and doesn’t affect the production cost per die.
The new Venice processor core appeared AMD’s first practical experience with Dual Stress Liner technology for desktop PC CPUs. This new technology used together with the successful SOI (Silicon-on-Insulator) technology allowed Venice based processors to reach higher working core clock frequencies. According to AMD engineers’ expectations, Dual Stress Liner and SOI together should ensure about 16% increase in the frequency potential of Athlon 64 processors. In other words, Venice based CPUs should have their nominal frequencies reach 2.8GHz.
Moving from the changes in the production process over to some more tangible things, we should first of all point out that Venice processor core acquired extended SIMD instructions support. Now new Athlon 64 on Venice core support SSE3 instructions, just like the Prescott based Pentium 4 processors. However, it would be good to remind you that SSE3 is not a complete set of instructions, but an addition to the SSE2 instructions set.
Thus, SSE3 instructions set introduced in Venice includes 11 new instructions:
- ADDPS, HSUBPS, HADDPD, HSUBPD – horizontal operations with SSE2 registers, which have been left out during SSE2 set development for some reason. These instructions can be extremely helpful for 3D graphics processing, as they simplify significantly the calculation of scalar vector product.
- ADDSUBPS, ADDSUBPD, MOVSHDUP, MOVSLDUP, MOVDDUP – instructions for work with complex numbers. These commands can be very helpful for calculation of wave processes and sound processing, i.e. in all tasks using fast discrete Fourier transforms.
- FISTTP – this is a new arithmetic co-processor instruction transforming the co-processor stack into the integer type. For some unknown reason this instruction used to be absent in the x87 instructions set.
- LDDQU – this instruction loads 128-bit unaligned data. It can be very helpful for faster video compression.
Two more SSE3 instructions implemented in Pentium 4, MONITOR and MWAIT, are absent in the Venice core because they are intended only for work with Hyper-Threading technology.
As a result, new Athlon 64 processors on Venice core boast the today’s biggest SIMD instructions set including 3DNow!, SSE2 and SSE3. However, we can hardly expect SSE3 instructions set to boost up the performance of the new Athlon 64 processors that much. The list of applications using SSE3 instructions is unfortunately still too short and pretty specific.