The definition of what FPGA really means has changed dramatically over the last two decades. Whether blazing the trail or being on the trailing edge of Moore’s Law, this is an exciting time to be an FPGA Designer. New opportunities bring new challenges for the FPGA market. As devices grow and become more complex resembling complete systems, the task of verifying such a system becomes daunting. In this section you will find timely, unbiased information from subject-matter experts that will help you navigate through this ever-changing landscape.
The modern FPGA designer faces many different challenges while working on his or her project. Fortunately, there are many solutions to choose from and more powerful, user-friendly tools available. Come back to this section often for new information and stay ahead of your competition.
FPGA Verification Courses
FPGA Verification Resources
VHDL-2008: Why It Matters.
VHDL-2008 (IEEE 1076-2008) is here! It is time to start using the new language features to simplify your RTL coding and facilitate the creation of advanced verification environments. VHDL-2008 is the largest change to VHDL since 1993.
Improving FPGA Debugging with Assertions.
Here's one reason why FPGA design starts dwarf ASIC design starts: choosing flexible, inexpensive and readily available FPGAs is one fairly obvious way to reduce risk when designing complex SoCs for everything from mobile devices and smartphones to automobile electronics. In fact, Gartner reported that FPGAs now have a 30-to-1 edge over ASICs in terms of new design starts. This ratio is startling since FPGAs have traditionally been relegated to glue logic, low-volume production, or prototype parts used for analysis. But the landscape is changing.
FPGA Verification With Assertions: Why Bother?
The benefits assertion-based verification (ABV) have been talked about for years. However, for many FPGA engineers with little time available to learn newer advanced functional verification techniques, assertions seem overly complex—and the method of creating them remains a mystery. This paper provides a practical, easy, step-by-step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting simulation debugging time in half, as well as finding very complex bugs that are likely to escape traditional simulation without assertions.
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