Efficient hardware implementations of low bit depth motion estimation algorithms
Çelebi, Anıl and Urhan, Oğuzhan and Hamzaoğlu, İlker and Ertürk, Sarp (2009) Efficient hardware implementations of low bit depth motion estimation algorithms. IEEE Signal Processing Letters, 16 (6). pp. 513-516. ISSN 1070-9908
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Official URL: http://dx.doi.org/10.1109/LSP.2009.2017222
In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures.
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