This page is intended to provide an informal overview of the internals of the RISC OS kernel, to help inform OS maintainers of how everything fits together.
The kernel source is located at castle/RiscOS/Sources/Kernel in CVS. There are two main branches of interest:
Other branches (e.g. Cortex, RPi) are typically development branches that have fulfilled their original purpose and have been merged into a parent branch and closed.
There are five main parts to the kernel source:
The kernel workspace is defined in hdr.KernelWS. There are two workspace layouts available:
The type of workspace in use is selected via the HighProcVecs option in hdr.Options.
Although the majority of the kernel workspace is kept private, there are several locations exported publicly to the rest of the OS in hdr.PublicWS. However only the legacy locations are exported here; for compatibility with kernels that use zero page relocation, programs should first attempt to query the address using OS_ReadSysInfo 6 before falling back on the legacy address.
Significant workspace locations are listed below:
CursorChunkAddress marks the start of a second area of workspace (currently) located at &FAFF0000. This area is used for the cursor & sound DMA buffers, along with the OSCLI workspace and SWI/IRQ dispatchers.
The SWI despatcher is a small routine that gets copied out of ROM (see SVCDespatcher in s.Kernel).
The default IRQ dispatcher is a small routine that gets copied out of ROM (see DefaultIRQ1Vcode in s.NewIRQs).
The CAM is a data structure used to track the allocation of physical RAM pages. It’s implemented as a simple table indexed by the physical page number. Each entry in the table is two words long; the first word contains the logical address which the page is currently mapped to (or the special value of ‘DuffEntry’ if unmapped), and the second word contains the PPL (“Page protection level”) and additional flags (see below table). The PhysRamTable is used to map the physical RAM page numbers to and from physical RAM addresses.
|0-15||PPL, cacheable/noncacheable, flags, etc. Same as bits 0-15 of the Memory Page Access Flags.|
|16-19||“Temporary count of uncacheability”, used by DMAManager|
|20||“Unavailable” flag. Used to mark pages that have been requested by a dynamic area PreGrow handler, but haven’t yet been moved.|
|21||“Required” flag. Used to mark pages that have been specifically requested by dynamic areas. This guarantees that the page won’t be used for another purpose until the dynamic area releases it, e.g. for hardware IO buffers.|
The above flags are all defined in s.ChangeDyn, at the DynamicAreaSWI code.