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With the development of technology, as it is scaling towards nanometer regime, for optimizations like physical synthesis and static timing analysis, accurate interconnect delay and slew computation has become critical. The timing verification of digital integrated circuits has become an extremely difficult task due to statistical variations in the gate and wire delays. Statistical timing analysis techniques are being developed to tackle this important problem. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. So efficient interconnect delay and slew computation has become critical in this era. Slew rate determines the ability of a device to handle the varying signals. Determination of slew rate to a good proximity is very much essential for efficient design of high speed CMOS integrated circuits. This work presents an accurate and efficient model to compute the slew metric of on-chip interconnect of high speed CMOS circuits. Our slew metric assumption is based on the Beta Distribution function. The Beta distribution is used to characterize the normalized homogeneous portion of the step response. For a generalized RC interconnect model, the stability of the Beta Distribution model is guaranteed.