San Jose, Calif. Cadence Design Systems, Inc. has released its Cadence Allegro system interconnect design platform to optimize and accelerate high-performance, high-density interconnect designs. The new platform combines best-of-breed design and analysis tools with a new co-design methodology across three design domains for the IC, package and PC-board.
This new platform supports a new generation of co-design methodology that promotes collaboration across the entire system design chain, which will minimize design iterations within and among the design domains of the IC, package and PC-board design, said the company.
The term "system interconnect" refers to the logical, physical, and electrical connection of a signal, its associated return path, and power delivery system, said the company. It travels between different IC I/O buffers and traverses die bump pads, package substrates, connectors, and PC-boards.
Traditionally, the design and analysis of the system interconnect is performed using a highly fragmented set of design processes across three different domains: IC, IC packaging, and PC-board.
However, the Allegro platform supports a new methodology that provides for the design, modeling and analysis of the system interconnect across the IC, IC packaging and PC-board. The methodology takes the system interconnect from specification through exploration, design, implementation, verification, manufacture, and correlation, said the company.
Based on feedback from its IC and systems customers, Cadence has found that the system interconnect design between today's complex ICs is a major bottleneck which delays time to market.
As a result, the new platform provides a common constraint-driven flow across design entry, signal and power integrity, and addresses the implementation of system interconnects.
At the heart of this methodology is a virtual system interconnect(VSIC) model defined by Cadence that describes the entire interconnect. The VSIC model is used to capture the original design intent and is matured throughout the design process as various segments of the interconnect are implemented. Through the VSIC model, engineers can design and implement their portion of the system interconnect within the context of the whole system.
The platform includes the Allegro Package Designer, Allegro Package SI and PCI Express design chain.
The Allegro Package Designer and Allegro Package SI are new generation technologies that support the feasibility analysis and design of the IC's bump array or die pads, taking into account I/O buffer placement, package technology rules and electrical performance targets.
The Allegro Package Designer also supports an engineering change process, which ensures that the interface between IC and package is exactly the same in both design domains, eliminating the risk of mask re-spins.
Cadence has also introduced a new approach to silicon design-in kits with its PCI Express design chain solution. This will give system designers a starting point for their PC-board implementations, based on the Allegro system interconnect platform, that will be refined as the actual PC-board interconnect is implemented.
The design chain also supports the plug-in of silicon design-in kits for specific ICs. With this release, customers can design with Intel's next-generation chipsets, Altera's Stratix GX FPGA, and the Cadence Services PCI Express Serdes. To learn more about the PCI Express design chain, please visit www.allegrosi.com
The Cadence Allegro platform supports Windows, Sun Solaris, HP-UX, IBM AIX, and Red Hat Linux platforms. Specific operating system support varies by product. U.S. pricing for a 1-year license starts at $54,000 for the Allegro Package Designer, $45,000 for the Allegro Package SI and $25,200 for the Allegro PCB SI. The platform also includes enhanced versions of all existing products, such as Concept HDL, SPECCTRAQuest, and the Allegro platform. The PCI Express design chain for use with the Allegro PCB SI is available for free downloading at www.allegrosi.com
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