Nagpal, Rahul and Srikant, YN (2007) Compiler-assisted instruction decoder energy optimization for clustered VLIW architectures. In: 14th International Conference on High Performance Computing (HiPC 2007), DEC 18-21, 2007, Goa.
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Traditionally, an instruction decoder is designed as a monolithic structure that inhibit the leakage energy optimization. In this paper, we consider a split instruction decoder that enable the leakage energy optimization. We also propose a compiler scheduling algorithm that exploits instruction slack to increase the simultaneous active and idle duration in instruction decoder. The proposed compiler-assisted scheme obtains a further 14.5% reduction of energy consumption of instruction decoder over a hardware-only scheme for a VLIW architecture. The benefits are 17.3% and 18.7% in the context of a 2-clustered and a 4-clustered VLIW architecture respectively.
|Item Type:||Conference Paper|
|Additional Information:||Copyright of this article belongs to Springer.|
|Department/Centre:||Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)|
|Date Deposited:||25 Mar 2010 06:07|
|Last Modified:||19 Sep 2010 05:57|
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