The VLIW DSP IP Core is suited for large multi-core systems-on-chip (SoC). The VLIW DSP can also be used as DSP accelerator in combination with a General Purpose Pro-cessor.
The VLIW DSP offers high computational power at low power and small footprint. Advanced loop control mechanisms reduce code size and increase energy efficiency by switching off idle components during loop execution. Use of tightly coupled data memory further increases power and processing efficiency.
- Fixed point architecture supporting floating point emulation;
- Versatile: building block for multi-core SoC as well as DSP accelerator core for general purpose processor;
- Small silicon footprint;
- High instruction-level parallelism with 10 execution slots;
- 32/40-bit scalar and two 16-bit element vector operations;
- Easy integration in NoC-based or bus-based SoC;
- Energy efficient due to advanced control logic and loop techniques;
- Customizable RTL soft core with configurable memory sizes, datapath width and instruction-set customization to optimize for a specific application.
- Versatile DSP accelerator IP core;
- Convenient for multi- and many-core Systems-on-Chip;
- Excellent combination of small silicon footprint, computational power and low power consumption;
- Efficient hardware and control;
- Predictable and deterministic behavior.
- Xentium® synthesizable RTL soft core
- Software development tools
- Product documentation
Block Diagram of the VLIW DSP IP Core