by Anton Shilov
06/16/2010 | 11:55 PM
Historically Intel Corp. has achieved remarkable density of cache inside its microprocessors, which allows it to pack in more SRAM memory than competitors while retaining decent size of the die. at the 2010 Symposia on VLSI Technology and Circuits the world’s largest maker of central processors will reveal its attitude towards technologies that can make cache even more dense.
Today's central processing units typically contain large amounts of on-chip cache memory, which speeds up access to code and data, thereby improving overall performance and reducing power. Intel engineers are looking for ways to make these memories more dense than they are today, to either increase their capacity (for improved performance) or reduce their size (for lower manufacturing cost). Floating body cell (FBC) is one candidate to one day replace the 6-transistor SRAM cells in use today. In two presentations at the 2010 Symposia on VLSI Technology and Circuits this week, Intel is presenting progress in developing this FBC.
One paper describes the development of a 22nm FBC memory on a bulk wafer of the kind in use in high volume manufacturing today – earlier results were on much more expensive SOI (silicon on insulator) wafers. Another paper describes a procedure for selectively doping (introducing impurities) into an FBC's back gate, without contaminating other parts of the device . quite a challenge, given its size.