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Image text transcribed for accessibility: Given a positive edge-triggered D flip-flop, show how to construct A positive edge-triggered SR flip-flop. A positive edge-triggered JK flip-flop. In the circuit below all gates, including the inverter, have an inertial delay of 10ns. Print and submit your code. Write VHDL code that gives a dataflow description of the circuit. All delays should be inertial delays.