Lattice Semiconductor has introduced its second generation of Power Manager II devices along with details of the first device available, the ispPAC-POWR1220AT8. The Power Manager II family is a functional superset of Lattice’s earlier ispPAC Power Manager mixed-signal devices that provide a complete power management solution for printed circuit boards (PCBs) through an optimized set of programmable digital and analog functions.
All Power Manager devices provide a standard, off-the-shelf programmable mixed-signal solution for power management that enhances reliability and speeds time-to-market. Analog features such as input comparator thresholds and digital functions such as supply control sequences are programmed into non-volatile E2CMOS elements on the devices using an IEEE1149.1 protocol. The new Power Manager II devices add power supply margining and trimming to first generation device features such as power supply voltage sequencing and monitoring.
The POWR1220AT8 device integrates a 48 Macrocell ruggedized CPLD, dual precision voltage monitoring comparators with an accuracy of 0.5 percent, a 10-bit analog-to-digital converter (ADC) for voltage measurements, and eight 8-bit digital-to-analog Converters (DACs) for trimming power supplies. The integrated I2C interface enables a microcontroller, such as an IPMC, to read the status of all the comparators (inputs and outputs) as well as control the power supply voltage level across its entire operating range. Additionally, the controller can measure not only locally generated voltages, but current levels as well.
New margin and trim block provides accurate supply voltage control
The ispPAC POWR1220AT8 device integrates a unique Margin and Trim Block (MTB) that provides a flexible mechanism for both setting and maintaining the output voltage of a power supply to within 1 percent of its set value ("trimming"), as well as the ability to vary a power supply voltage to +/- 5 percent of its target value for quality control purposes ("margining"). The MTB consists of 8 TrimCells to simultaneously control the power supply voltages of up to 8 supplies. Each TrimCell has an 8-bit DAC and 6 DAC registers for margining and trimming flexibility. Accuracy of the trimmed voltage across operating temperature, load, and age of the power supply is achieved through a Digital Closed Loop Trim control circuit.
Designs for the ispPAC-POWR1220AT8 device are implemented using Lattice's Windows-based PAC-Designer Software version 4.0. The embedded LogiBuilder software module in PAC-Designer supports the implementation of multiple control sequence algorithms: for example, IPMC command response, Payload power management, and AMC management required in ATCA applications. Designers are able to implement complex algorithms using 7 types of instructions. With an extremely intuitive design flow, users can learn its operation and complete designs in minutes.
Further enhancing its ease-of-use, the Margin and Trim macro embedded in PAC-Designer 4.0 automatically determines the resistor network for a given power supply based on the required output voltage.
Pricing and availability
The PAC-Designer 4.0 software is available for download free of charge from the Lattice website. High volume (10KU+) pricing for the ispPAC POWR1220AT8 devices in the 100-pin TQFP package and industrial temperature range is $5.50. Samples are available now. More information is available at www.latticesemi.com.