My main research effort involves the design of future generations of high-performance and low-power computer systems, including both microprocessors and multiprocessors. I am interested in issues related to their machine architectures, programming models, compilation techniques and system software.
In the design of future generations of microprocessors, we focus on multi-threaded, multi-core architectures that exploit both thread-level and instruction-level parallelism, possibly with speculation support, to achieve high performance with reduced power consumption. The targeted systems range from large-scale parallel machines to application-specific embedded systems.
Our compiler effort is centered on a profile-based approach that supports both medium-grained (loop iteration-level) and fine-grained (instruction-level) parallelism with speculation, low power, and latency hiding schemes. In this research area, we investigate both static (at compile time) and dynamic (at runtime) compilation techniques. We also study binary translation techniques that support cross-platform execution. New parallel programming models that support specific applications of domain experts are another area of interest.
In system software research, we currently focus on operating system support for multi-core embedded systems, and on supporting virtualization for various applications.
We adopt an experimental approach to the above design issues, with on-going development of compiler and architectural simulation infrastructures to support our research efforts.