Challenges and Solutions for Future Main Memory
May 26, 2010 // Rambus // 0 commentsDownload White Paper 1Mo
This whitepaper presents an architectural concept for a future memory system that addresses the anticipated demand for higher bandwidth with higher data rates, lower power, higher throughput and higher capacity. The future memory architectural concept, employing Rambus innovations, doubles data rates over current DDR3 memory and substantially improves throughput and transfer efficiency with 64Byte accesses. The architecture reduces standby, IO and core power, and can natively support higher capacities per memory channel.
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To ensure you have a good start in 2015, Freescale is giving away five of its QorIQ TWR-LS1021A Tower system modules, worth USD269 each, for EETimes Europe's readers to win.
The module is the most feature-rich and high-performance Tower system offered by Freescale, enabling compatibility and interoperability with the growing list of Tower expansion modules, offering an easily accessible and interchangeable suite of capabilities and features to support rapid prototyping as well as software development programs.Built around the QorIQ LS1021A processor, incorporating dual ARM Cortex-A7 cores running up to 1GHz and delivering more than 5,000 Coremarks of performance, the TWR-LS1021A is engineered to enable a wide range of applications, from IoT gateways to industrial controllers, secure access points and asset management systems. MORE INFO AND LAST MONTH' WINNERS...
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Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.