Milpitas, Calif.--June 23, 1998--Virage Logic Corp. (Milpitas) announced that it has successfully completed the development of what is believed to be the industry's first erasable programmable read-only memory (EPROM) compiler. The compiler utilizes the 0.6-m embedded EPROM process from Tower Semiconductor, Ltd.
The Tower EPROM delivers a One Time Programmable (OTP) array. With a cell size of 1.7 m squared, it's about half the size of competitive technologies, and allows for optimal ramp-up to ROM. The compiler provides blocks in a variety of configurations from 32 kbits to 512 kbits.
The Virage EPROM compiler is for use by Tower foundry customers who design ICs and ASICs with embedded non-volatile memory. These ICs are used in a wide variety of microcontroller and other embedded applications. Tower customers are already embedding compiled arrays in their designs, in applications such as general purpose micro-controllers and consumer products.
The compiler provides ASIC developers with all the views they need to integrate the EPROM block into their designs. It also generates modes and vectors for EPROM testing. This helps reduce time-to-market, while optimizing the customers' designs for the memory technology. The compiler instances have been tested on silicon validating the accuracy of the compiler.
Virage Logic Corp.
1641A South Main Street
Milpitas, CA 95035
Fax: (408) 263-9523
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