Issue No.01 - January-March (1997 vol.14)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.573368
ASIC (Application-Specific Integrated Circuit) testability, troubleshooting access and visibility of internal circuitry are the primary targets of test engineering analysis. The widely applied boundary-scan technique does not solve all problems connected with the PBA (Printed Board Assembly) manufacturing process. This paper presents an extension of the boundary-scan technique currently implemented to provide ASIC testability. The concept of Collateral ASIC Test (method and logic) implemented in a boundary-scan device is described as well as the test process standardization implied by this new approach to ASIC design and testing.
ASIC Test, Boundary-scan Test, Reading Status, Test Cost Reduction, Test Standardization
Al Bailey, Tim Lada, Jim Preston, "Collateral ASIC Test", IEEE Design & Test of Computers, vol.14, no. 1, pp. 55-63, January-March 1997, doi:10.1109/54.573368