Optimizing power in a chip is one thing, but you still have to get power to where power is needed and that is the difficult job of the power delivery network...
It has already been stated that most chips have off-chip voltage regulators today but with the need for these voltage domains to respond faster to the demand current, on-die regulators are increasingly being used. Dermott Lynch, VP Marketing, Silicon Frontline Technology says power devices typically operate in the 70-90% efficiency range which results in a loss of 10-30% of overall system power.
Ely Tsern, VP and CTO for Rambus’ Semiconductor Business Group points out that more aggressive system power mode transitions, with finer grain power domains, will result in faster transitioning local supply currents, which in turn can induce greater di/dt supply noise for sensitive local circuits.
Arvind Shanmugavel, Director of Applications Engineering for Apache/Ansys reminds us that under all conditions, the power delivery network (PDN) should be able to sustain the load without compromising on the voltage integrity. For example, when a global clock-gate is turned on and a functional unit turns on to perform a task there is a transient current demand at this point. This transient current can be 3x-5x that of the nominal current, depending on the functional block. This places an enormous load on the PDN. The transient voltage noise on the PDN needs to be validated under these circumstances.
Wake-up scenarios when using power-gating techniques are also very important to analyze. Rapid turn on of power-gates in a block or chip during wake-up can lead to a very high instantaneous in-rush current. This in-rush current can affect the ability of the voltage regulator to supply the current or couple to the neighboring power domains and affect its voltage integrity. During such scenarios it is imperative to simulate the operation with the impact of the package and board on the die.
With the increasing usage of DVFS the change in frequency can affect the time at which logic switches, thereby increasing or decreasing the demand current. The placement of decoupling cells, selection of package PDN density and regulator design should be designed with these operating scenarios in mind.
Brad Griffin, director, product marketing, Silicon Realization at Cadence adds that system level considerations cannot be forgotten. He says that chip designers are under increasing pressure to insure that their packaged devices can be designed into a minimum layer PCB. Proper attention to the system level PDN is key to creating a proper reference design that insures system integrators can meet cost and performance requirements. To meet stringent target PDN impedance requirements, chip designers are looking at full chip-package-board PDN modeling solutions that validate sufficient and stable power can be delivered to the chip while keeping the package and PCB cost minimized.
The thermal envelope is also another critical factor for the operating of these devices. Low-power mobile devices are sensitive to temperature, especially due to the tight physical constraints and lack of forced cooling. Thermal characteristics should be studied for various power conditions of such devices with the context of the package, board and chassis.
Other parts of this series include:
Design Article: Power delivery network design requires chip-package-system co-design approach
- Aveek Sarkar, vice president of product engineering and support, Apache Design Solutions Inc. (San Jose, Calif.)
Book: Signal and power integrity – simplified (second edition)
- Eric Bogatin
Brought to you by Brian Bailey
If you spot an error, would like to propose an improvement or addition to this entry, or anything within this power archive, please let me know by sending me an email
. Your comments will be added, and your name will be preserved in the document indicating your participation in its improvement.
Go back to the root of the EDA Designline Power Series.