US 7934031 B2
An asynchronous logic family of circuits which communicate on delay-insensitive flow-controlled channels with 4-phase handshakes and 1 of N encoding, compute output data directly from input data using domino logic, and use the state-holding ability of the domino logic to implement pipelining without additional latches.
1. A circuit comprising a plurality of pipeline stages, each of the plurality of pipeline stages comprising:
at least one asynchronous, delay-insensitive input channel, each input channel being operable to communicate with a preceding one of the pipeline stages by waiting for input data on the input channel, asserting an input acknowledge signal in response to the input data, waiting for the input channel to be set neutral, and deasserting the input acknowledge signal in response to the input channel being set neutral;
at least one asynchronous, delay-insensitive output channel, each output channel being operable to communicate with a subsequent one of the pipeline stages by waiting for an output acknowledge signal associated with the subsequent pipeline stage to be deasserted, transmitting output data on the output channel in response to deassertion of the output acknowledge signal, waiting for the output acknowledge signal to be asserted, and setting the output channel neutral in response to assertion of the output acknowledge signal;
input completion circuitry configured to generate an input completion signal indicative of validity of the input data;
output completion circuitry configured to generate an output completion signal indicative of validity of the output data;
enable circuitry configured to generate the input acknowledge signal and an internal enable signal using the input completion signal and the output completion signal as input; and
domino logic configured to compute the output data directly from the input data, the domino logic being configured to hold a state of the output data until reset in response to the output acknowledge signal associated with the subsequent pipeline stage and the internal enable signal.
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The present application is a continuation application of and claims priority under 35 U.S.C. 120 to U.S. patent application Ser. No. 10/294,044 filed on Jul. 18, 2001 (abandoned), which is a continuation of U.S. patent application Ser. No. 09/501,638 filed on Feb. 10, 2000 (abandoned), which is a continuation of U.S. patent application Ser. No. 09/360,468 filed on Jul. 22, 1999 (abandoned), which claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 60/093,840 filed on Jul. 22, 1998, the entire disclosure of each of which is incorporated herein by reference for all purposes.
This application may have received funding under U.S. Government Grant No. DAAH-04-94-G-0274 awarded by the Department of the Army.
This specification describes communicating sequential processes (CSP) which are implemented as quasi delay insensitive asynchronous circuits. More specifically the present specification teaches reshuffling communication sequences and combining computation with buffering to produce pipelined circuits.
Asynchronous processors are known as described in U.S. Pat. No. 5,752,050. These processors process an information stream without a global clock synchronizing the operation.
An asynchronous processor pipeline scheme uses the basic layout shown in
The request between 110 and 120 is the R wire (104), and the acknowledge is Ra (106).
This is a basic request, acknowledge system. The request [L] is acknowledged (La), then acted on R↑, then acknowledged again (Ra).
Pipelined asynchronous circuits are known as “Bundled-Data” or “Micropipelines” and have a synchronous style data path which is “clocked” by asynchronous self-timed control elements. These control elements handshake between pipeline stages with a request/acknowledge pair. The delay of the datapath logic is estimated with a delay-element in the control, so that the request to the next pipeline state is not made until the data is assumed to be valid.
The alternative style involves (quasi) delay-insensitive circuits, for which no delay assumptions are made. In this style, the prior art is embodied in the Caltech Asynchronous Microprocessor patent. Datapaths are still separated from control, as in the bundled-data case, but completion detection circuitry is added instead of delay lines to detect when the data is valid. Communication between processes occurs via delay-insensitive channels with a 4 phase handshake. In between latches or buffers, logic can be performed by unpipelined weak-condition logic blocks.
The present system teaches a way of pipelining this handshake to allow certain processes to occur closer to simultaneously. The disclosed system is a delay insensitive system that uses a combination of logic and buffering to resequence certain operations.
A new way of pipelining quasi-delay-insensitive circuits is disclosed in which control is not explicitly separated from the datapath. No extra buffers or latches are added between logic blocks. Instead, the state-holding property of a buffer is combined directly with a dual-rail domino logic computation. The tokens travel through the pipeline as in the case of simple buffers. The tokens also carry values which are computed upon. By not separating control from data, and by carefully designing the circuit parts which handle the handshakes, higher throughput is expected. The extra handshake circuitry typically adds no more than 50% area.
The supporting circuitry which handles the handshake takes place in precharge domino logic of a type that is common in synchronous design. Additional circuits detect the validity of the input and output channels (common in asynchronous design). An acknowledge circuit acknowledges the inputs and precharges the logic.
The circuit implementations disclosed in this patent include components for logic computation, plus components to detect the validity of the input and output data, and another component to generate the acknowledges and precharge the logic. The details and composition of these pieces generate fast quasi delay insensitive circuits superior to the prior art.
This patent also includes further enhancements of this combined buffer/logic cell. These include the ability to conditionally communicate on either inputs or outputs, so as to implement routing functionality. Also, mechanisms for efficiently implementing internal state variables are described.
These and other aspects will now be described in detail with reference to the accompanying drawings, wherein:
The present system is based on a way of pipelining the information in the
The present system teaches a way of dealing with this issue by reshuffling the communication sequence, storing certain information within the sequence, and enabling more efficient pipelining information.
A “pipeline” is a linear sequence of buffers where the output of one buffer connects to the input of the next buffer as shown in
For synchronous pipelines, the tokens usually advance through one stage on each clock cycle. For asynchronous pipelines there is no global clock to synchronize the movement. Instead, each token moves forward down the pipeline where there is an empty cell in front of it; otherwise, the token stalls. Effectively, the tokens have similar behavior to cars on a freeway.
The buffer capacity or “slack” of an asynchronous pipeline is proportional to the maximum number of tokens that can be packed into the pipeline without stalling the input end of the pipeline. The “throughput” is the number of tokens per second which pass a given stage in the pipeline. The “forward latency” is the time it takes a given token to travel the length of the pipeline.
A single rail buffer has the Communication Sequential Process “CSP” specification *[L;R]. Using a passive protocol for L and a lazy active protocol for R, the buffer will have the handshaking expansion (HSE):
in English, the handshaking expansion for this buffer is as follows: Wait for L to become true. Set La true. Wait for L to become false. Set La false. Wait for Ra to become false. Set R true. Wait for Ra to become true. Set R false. Repeat infinitely.
The present system recognizes that certain sequences are the most interesting among these sequences. The present application reshuffles the sequence in order to do these first.
In effect, equation 1 represents a four phase protocol. The first two actions [L]; La↑, represent waiting for L to become active, and acknowledging that. The second two actions represent L becoming inactive. The third two actions represent waiting for R to become active. The fourth two actions represent R inactive.
The environment will perform *[[
Direct implementation of this handshaking expression can use a state variable to distinguish the first half from the second half. This represents a large amount of sequencing in each cycle.
Another option is to reshuffle the waits and events to reduce the amount of sequencing and the number of state variables, in order to maximize the throughput and minimize the latency of the pipeline.
The first requirement for a valid reshuffling is that the Handshaking expression maintains the handshaking protocols on L and R. That is, the projection on the L channel is *[[L]; La↑; [
Although these three requirements are sufficient to guarantee a correct implementation, one more is useful. The L and R channels may be expanded to encode data. If the reshuffling moves the R↑ past the corresponding La↑, then the “L” data would disappear before R↑ is done. The data here is saved in a buffer, here implemented as an internal state variable proportional to the number of bits on R or L. That data would need to be saved in internal state bits, since the L data may disappear as soon as La+ occurs. These additional internal state bits are undesirable, so La↑ will follow R↑.
There are nine valid reshufflings, each labeled below:
It takes two state variables to implement the MSFB reshuffling. The PCFB, B1, B2, B3, B4, and B5 reshufflings all require one state variable en (short for enable) with en ↓ inserted after La↓ and en↑ inserted before the end.
Selection of which of these reshufflings is the best can assume that the goal is fewer transistors and faster operation. By that metric, the present inventors believe that B3, B4, and B5 are always inferior to PCFB. They all require the same state variable. They produce only a subset of the trade-off PCFB, with additional waits that may be unnecessary. These waits add extra transistors and slow the circuit down, compared to PCFB. They also slow the circuit down as compared with PCFB, which adds extra transistors.
B1 and B2 are also very similar to PCFB, except they have more sequencing. However, that extra sequencing simplifies the production rule for en: to
The MSFB has the least possible sequencing of any of these reshufflings. However, MSFB requires two state variables and has more complicated production rules than PCFB. It has a possible advantage in speed since it allows R↓ to happen a little earlier. If one counts transitions, it turns out that the next buffer in the pipeline (if it is reshuffled similarly) will not even raise Ra until after La↓ occurs. This might not really be an advantage at all.
That leaves three most interesting reshufflings, WCHB, PCHB, and PCFB. The names are derived from characteristics of the circuit implementations. WC indicates weak-condition logic. PC indicates precharge logic. HB indicates a halfbuffer (slack ½), and FB indicates a fullbuffer (slack 1).
In the halfbuffer reshufflings, only every other stage can have a token on its output channel, since a token on that channel blocks the previous stage from producing an output token. In practice, each of these reshufflings has advantages for certain applications, so they are all useful. With state variables inserted, the three best reshufflings are:
Note that the first three parts of the reshuffling are the same.
Logic with Buffering
Suppose it is desired to implement a unit with CSP of the form:
P≡*[A?a,B?b, . . . ;X!f(a,b, . . . ),Y!g(a,b, . . . ), . . . ] where A?a means receive data a on channel A and y!g means send data g on channel y.
On each cycle, P receives some inputs, then sends out functions computed from these inputs. The channels A, B, X, and Y must encode some data. The usual way to do this is using sets of 1-of-N rails for each channel. For instance, to send two bits, one could use two 1-of-2 rails with one acknowledge, or one 1-of-4 rails with one acknowledge.
As a notational convention, a rail is identified by the channel name with a superscript for the 1-of-N wire which is active, and a subscript for what group of 1-of-N wires it belongs to (if there is more than one group in the channel). The corresponding acknowledge will be the channel name with a “a” superscript, or an “e” superscript if it is used in the inverted sense.
As in the single rail buffer case, P could be implemented by expanding each channel communication into a handshaking expansion. Direct implementation of this handshaking expansion requires state variables for the a, b variables and more. It could produce an enormously big and slow circuit. Some reshuffling is desired. The PCFB, PCHB, and WCHB reshufflings will be the most useful ones.
The correspondence between the single rail “templates” for PCFB, PCHB, and WCHB and a process like P is as follows. The L and La represent all the input data and acknowledges. The R and Ra represent all the output data and acknowledges. [L] indicates a wait for the validity of all inputs, and [
Unfortunately, the inventors have recognized that this simple translation may introduce more sequencing than necessary. Of the various actions which occur in parallel like setting all the outputs valid (R↑), each action might need to wait for only a portion of the preceding guard ([
The PCFB version of a P with dual rail channels would therefore be:
In this Handshaking expansion, the f0,f1, g0, and g1 are boolean expansions in the data rails of the input channels. They are derived from the f and g of the CSP and indicate the conditions for raising the various data rails of the output channels. Note that each output channel waits only for its own acknowledge, which is less sequenced than a direct translation of the PCFB template would be.
In P it is seen that Aa and Ba tend to switch at about the same time. They could actually be combined into a single ABa which would wait for the conjunction of the guards on Aa and Ba. Combining the acknowledges tends to reduce the area of the circuit, but might slow it down. The best decision depends on the circumstances.
Examples of Logic with Buffering
To put the previous section into practice, several CSP processes with the same form as P are compiled into pipelined circuits. The simplest CSP buffer that encodes data has a dual rail input L, and a dual rail output R. The CSP is *[L?x;R!x]. Three Handshaking expansion reshufflings for this process are:
After bubble-reshuffling (which suggests using the inverted acknowledges, Le and Re), the production rules for the WCHB-BUF follow. The circuit diagram for a WCHB is shown in
The other Handshaking expansions can be implemented similarly, but they are both somewhat bigger. For this reshuffling, the validity and neutrality of the output data R implies the neutrality of the input data L. Logic which has this property is called “weak-condition”. It means that the L does not need to be checked anywhere else, besides in R. The WCHB also gets some of its semicolons implemented for free. The semicolon between La↑; [Ra
This WCHB_BUF bubble-reshuffling has 2 transitions forward latency and 3 transitions “backward” latency (for the path from the right acknowledge to the left acknowledge). Combining these times for the whole handshake yields 2+3+2+3=10 transitions per cycle.
Extra inverters can be added to WCHB_BUF to get 10 transitions per cycle. These inverters can actually speed up the throughput, despite the increased transition count, because inverters have high gain. Also, the 6 transitions per cycle buffer would invert the senses of the data and acknowledges after every stage, which is highly inconvenient when composing different pipelined cells. As a standard practice, most pipelined logic cells will be done with 2 transitions of forward latency, but more complicated circuits will have 5, 7 or even 9 transitions backward latency, yielding transitions per cycle from 10 to 22 (even numbers only, of course).
Next consider a full adder, with the CSP *[A?a, B?b, C?c; S!XOR(a,b,c), D!MAJ(a,b,c)]. The A,B,C,S and D channels are dual rail. The acknowledges for A,B, and C are combined into a single Fe. Inverted acknowledges are used from the start. The three Handshaking expansion reshufflings are:
In the WCHB_FA, the validity of the outputs S and D implies the validity of the inputs, because the S must check all of A,B, and C. The test for the neutrality of the inputs is split between S↓ and D↓. This works as long as both S↓ and D↓ check at least one input's neutrality completely, and both rails of S and D wait for the same expansion. In both PCHB_FA and PCFB_FA, the expansion for the neutrality of the inputs is obviously too large to implement as a single production rule. Instead, the neutrality test must be decomposed into several operators. The usual decomposition is “nor” gates for each dual rail input, followed by a 3-input c-element. Fe↓ must now wait for the validity of the inputs just to acknowledge the internal transitions. However, this means the logic for S and D no longer needs to fully check validity of the inputs; it is not required to be weak-condition.
The bubble-reshuffled and decomposed production rules for WCHB_FA are:
The circuit diagram is shown in
The present systems uses the “precharge-logic” reshufflings, PCHB_FA or PCFB_FA. These test the neutrality of the inputs in a different place, which is more easily decomposed into manageable gates, and does not slow the forward latency. The PCHB_FA reshuffling has the production rules:
This circuit can be made faster by adding two inverters to Fe and then two more to produce the Fe used internally (which is now called en). This circuit is shown in
Comparing the three fulladder reshufflings, the WCHB_FA has only 10 transitions per cycle, while the PCHB_FA has 14 and the PCFB_FA has 12 (7 on the setting phase, but 5 on the resetting phase, since the L and R handshakes reset in parallel). Although the WCHB_FA has fewer transistors, to make it reasonably fast, the 4 P-transistors in series must be made very large. Despite the lower transition count of tile WCHB_FA, both PCHB_FA and PCFB_FA are substantially faster in throughput and latency. PCFB_FA is the fastest of all, since it relies heavily on n-transistors and saves 2 transitions on the reset phase. However PCFB_FA can be larger than PCHB_FA, due to the extra state variable en and the extra completion SDv If the speed of the fulladder is not critical, the PCHB FA seems to be the best choice.
In general, the WCHB reshuffling tends to be best only for buffers and copies ([L?x;R!x,S!x]). The PCHB is the workhorse for most applications; it is both small and fast. When exceptional speed is called for, the PCFB dominates. It is also especially good at completing 1-of-N codes where N is very large, since the completion can be done by a circuit which looks like a tied-or pulldown as opposed to many stages of combinational logic. The reshuffling can actually be mixed together, with each channel in the cell using a different one. This is most commonly useful when a cell computes on some inputs using PCHB, but also copies some inputs directly to outputs using WCHB. In this case, the neutrality detection for the WCHB outputs is only one p-gate, which is no worse than an extra en gate.
Another common class of logic circuits use shared control inputs to process multi-bit words. This is similar to a fulladder. The control is just another input, which happens to have a large fallout to many output channels. Since the outputs only sparsely depend on the inputs (usually with a bit to bit correspondence), the number of gates in series in the logic often does not become prohibitive. However, if the number of bits is large e.g., 32, the completion of all the inputs and outputs will take many stages in a c-element tree, which adds to the cycle time, as does the load on the broadcast of the control data. To make high throughput datapath logic, it can be better to break the datapath up into manageable chunks (perhaps 4 or 8 bits), and send buffered copies of the control tokens to each chunk. This cuts down the cycle time, but does not change the high-level meaning, except to introduce extra slack.
Conditionally Producing Outputs
Although the cells discussed in the previous section can be shown to be Turing complete (they can be turned into a Von Neumann state machine, with some outputs fed back through buffers to store state), they are clearly inefficient for many applications. A very useful extension is the ability to skip a communication on a channel on a given cycle. This turns out to require only a few minor modifications to the scheme as presented so far.
Suppose the process completes at most one communication per cycle on the outputs, but always receives all its inputs. The CSP would be:
As above, this can reshuffle like WCHB, PCHB, or PCFB. The selection statements for the outputs expand into exclusive selections for setting the output rails, plus a new case for producing no output at all on the channel. A dual-rail version of P1 with a PCFB reshuffling is:
Note that the resetting of the output channels X and Y must accommodate the cases when those channels were not used. Since they produce no outputs, they must not wait for the acknowledges. Adding in the
An interesting choice arises from the use of the skip. A skip causes no visible change in state, so the next statements in sequence (Aa↑,Ba, . . . ) must actually look directly at the boolean expansion for
The completion condition for setting the outputs would be en
Another approach is to introduce a new variable to represent the
Finally, there are many cases were some expansion of the outputs is sufficient to produce the output completion expansion without reference to the inputs. For instance, if one input is used to decide if a certain output is used, but is also copied to another output, the copied output could be used to check the completion of the optional output. Similarly, if two output channels are used exclusively, such that one or the other will be used each cycle, the completion for both is just the or of each one's completion.
To put this discussion into practice, a split is implemented, a fundamental routing process which uses one control input to route a data input to one of two output channels. The simple one-bit CSP is *[S?s, L?x;[
The first two selection statements are known to be finished when A0
The circuit is shown in
Conditionally Reading Inputs
It is also highly useful to be able to conditionally read inputs. Normally the condition is read in on a separate unconditional channel, but in general it could be any expansion of the rails of the inputs. A CSP template for type of cell this would be:
The Ā in this context refers to a probe of the value of A, not just its availability. This is not standard in CSP, but is a useful extension which is easily implemented in Handshaking expansion. Basically, the booleans for do_a, do_b, no_a, and no_b may inspect the rails of A and B in order to decide whether to actually receive from the channels. The selection statements will suspend until either do_a or no_a are true. These expansions are required to be stable; that is, as additional inputs show up, they may not become false as a result.
For the Handshaking expansion, instead of assigning “unused” to an internal variable, the f and g expansions examine the inputs directly. The results of the do_a/no_a and do_b/no_b expansions must be latched into internal variables u and v, so that A and B may be acknowledged in parallel without destabilizing the guards of do_a and the like. The PCFB version of the Handshaking expansion is:
Similarly to the conditional output Handshaking expansion, the guards for Aa↓ and Ba↓ are weakened to allow the vacuous case. The skip again can pose a problem, since it makes no change in the state. However. with the u0 and v0 variables it is possible to infer the skip and generate the correct guard for en. On the reset phase, the u and v must return to the neutral state. There are several places to put this, but the symmetric placement which sequences them with the Aa↓ and Ba↓ simplifies the PRS.
In many cases, this general template can be greatly simplified. For instance, if a set of unconditional inputs completely controls the conditions for reading the others, these can be thought of as the “control” inputs. If raising the acknowledges of the various inputs is sequenced so that the conditional ones precede the control ones, then the variables u and v may be eliminated without causing stability problems. Also in some cases the u and v may be substituted with an expansion of the outputs, instead of stored separately.
As a concrete example, the circuit for the merge process reverses the split of the last section by conditionally reading one of two data input channels (A and B) to the single output channel R based on a control input M. The CSP is *[M?m; [
A subtle simplification used here is to make Ae↑ and Be↑ check the corresponding
As usual for PCHB reshuffling, of the work is done in a large network of n transistors. The circuit is shown in
Another extension to this design style is the ability to store internal state from one cycle to the next. A CSP template for a state holding process with state variable s is:
This can be implemented in a variety of ways. The simplest, which requires no new circuits, is to feed an output of a normal pipelined cell back around to an input, via several buffer stages. One of these feedback buffers is initialized containing a token with the value of the initial state. Enough buffers must be used to avoid deadlock, and even more are needed to maximize the throughput. Therefore, this solution can be quite large. For control circuitry, where area is less of an issue, this is often adequate. As an added benefit, the feed forward portion of the state machine can be implemented as several sequential stages of pipelined logic, which correspondingly reduces the number of feedback buffers necessary and allows far more complicated functions.
Aside from using feedback buffers, there are three main approaches to retaining state, of increasing generality and complexity. First, pipelining channels by themselves store state. Usually, these values move forward down the pipeline, passing each stage only once. However, if a stage uses but does not acknowledge its input, the input value will still be there on the next cycle. Essentially, the token is stopped and sampled many times. In CSP, this can be expressed with the probe of the value of the channel. A conditional input type of circuit is used, which uses an input to produce outputs without acknowledging that input. This technique can be used for certain problems. For example, a loop unroller could take an instruction on the input channel, and produce many copies of it on an output channel based on a control input. Of course, this type of state variable can never be set, only read one or more times from an input.
If the state variable is exclusively set or used in a cycle, a simple modification of the standard pipelined reshuffling will suffice. The state variable, s is assigned to a dual-rail value at the same time the outputs are produced. On the reset phase, it remains stable. Unlike the usual return-to-zero variables, s will only briefly transition through neutrality between valid states. If s doesn't change, it does not go through a neutral state at all. The CSP for this behavior is expressed just like P3, except the semicolon before the assignment to s is replaced with a comma. This is made possible by the assumption that s only changes when the outputs X and Y do not depend on it; this avoids any stability problems.
The only tricky thing about deriving the Handshaking expansion for this is the assignment statement. Basically, the assignment is done by lowering the opposite rail first, then raising the desired rail. This guarantees that the variable passes through neutral when it changes, and also bubble-reshuffles nicely. The completion detection of this assignment is basically equivalent to checking that the value of s corresponds to the inputs to s. So s:=x becomes [x0→s1↓; s1↑[ ]x1→s0↓s1↑]; [x0
It is often desirable to decompose the completion detection of the state variable into a 4 phase completion variable sv which detects the completion of the assignment on the set phase and is cleared on the reset phase. This makes it easier to have multiple state variables. One thing to note is that the assignment sequence and completion has 3 transitions if it changes state, and therefore often takes more transitions than a typical output channel. However, on the reset phase or if the state is unchanged, this only takes 1 transition. Another caveat is that the state variable shown here works best for only dual rail 1 bit state variables.
As an example of this type of state variable, consider the “register” process x:=0;*[C?c;[c→R!x[ ]
The PCHB version of the Handshaking expansion is:
The PRS has a few tricky features. Due to the exclusive pattern of the communications the rules for Ce can be simplified. The decomposed and bubble reshuffled PRS follows. The circuit is shown in
The most general form of state holding cell is one where the state variable can be used and set in any cycle. In order to do this, it is necessary to have separate storage locations for the new state and the old state. This may be done by introducing an extra state variable t which holds the new state until s is used. The CSP for this is:
When this is converted into an Handshaking expansion, there are several choices for where to put the assignment s:=t. It works best to do this assignment on the reset phase of the channel handshakes. After the assignment s:=t, t returns to neutral just like a channel. The PCFB version of this type of cell is:
The assignment statements may be compiled into production rules as before. Of special interest is the compilation of the sequence [t0→s1↓; s0↑; t0↓[ ] t1→s0↓; s1↑; t1↓]. Due to correlations of the data, this compiles into the simple (bubble-reshuffled) production rules:
The s0 and s1 should also be reset to the correct initial value. The completion of this sequence is just the normal check for to
In addition, extensions to these cells which allow for conditionally receiving inputs or conditionally sending outputs were explained. Finally, various approaches to storing internal state in the cells are disclosed.
The prior state of the art was to use un-pipelined weak condition logic. Extra buffers or registers would be added between blocks of logic to add some pipelining. This approach was smaller, but much slower. The extra buffers also increased the forward latency. Essentially, in the limit of using more and more buffers, they should eventually be merged into the logic and all cells should be “maximally” pipelined. That is, any discrete state of logic gets its own pipelining, so that no more slack could be added without just adding excess buffers. In practice, the cost of such fine pipelining amounts to a 50% to 100% increase in area over a completely un-pipelined circuit. It reduces the latency (since no separate buffers are added), and, of course, increases the throughput. At this natural limit of pipelining, all handshakes between neighboring cells require a small number of transmissions per cycle, typically 14 to 18. The internal cycles usually keep up. This yields a very high peak throughput (comparable to 14 transition per cycle hyper-pipelined synchronous designs like the DEC Alpha) but is more easily composable. However, composing fast pipelined cells in various patterns can yield much lower system throughputs unless special care is taken to match the latencies as well as the throughputs of the units.
Several simple modifications to these pipelined circuit templates are also useful and novel.
1. Go Signal
In the PCHB, it is possible to separate out the “en & re” expressions for the logic pulldown and “˜en & ˜re” for the logic pullup into a 2-input c-element of “en” and “re” which generates a single “go” signal used to precharge and enable the logic. This improves the forward latency and analog safety of the logic, although it adds 4 transitions to the handshake on the output channel.
With more care, this “go” signal may be added to a PCFB as well. In this case, the “go” signal must also be checked before producing the left enables, or instabilities will result. This has the side effect of reducing the slack to one half, but this is irrelevant when the goal is high speed.
When a “go” signal is used with conditional outputs, the “go-” must not wait for the right enable (re) to go down since it won't (as no data was sent on the last cycle). Instead of a c-element this gives the PRS: “en & re & ˜no_r->go+” and “˜en & (no_r|˜re)->go-”.
2. Shared Input/Output Completion
In most of these examples, the output completion is taken before the inverters, since this allows the use of a NAND gate instead of a NOR gate and gets the completion done a transition earlier. However, it is possible to complete from after the inverters as well. This is particularly useful when you can share the output completion circuit of one cell with the input completion of the next cell in the pipeline.
3. Timing Assumptions
Although this patent primarily presents asynchronous circuits in a quasi-delay-insensitive framework, it may prove desirable to introduce timing assumptions in order to simplify or speed up the circuit. Several useful non-QDI circuits can be derived simply by omitting transistors from a QDI WCHB, PCHB, or PCFB circuit. It is preferred if the introduced timing assumptions can be met entirely by estimating the delays within the cell, without making assumptions on the delays of its environment. Several simple modifications can satisfy this property.
For example, in a PCFB with a single “go” signal, it can be assumed that the output will precharge quickly after the “go” goes low. The fact that “go” is low can be taken to imply that the output data is precharged, or soon will be. This “implied neutrality” timing assumption can eliminate many transistors of completion detection, and allow the next cycle to begin earlier. In a similar fashion, the input validity can sometimes be ignored if the output validity implies that all input channels are valid.
Of the various types of state-holding cells, the more restricted versions generally have simpler and faster implementations, and should therefore be used if possible. For the most general case, either a pair of state variables should be used, or if area is not an issue, a feedback loop of buffers.
Three main types of handshaking reshuffling have proved superior for different circumstances. The weak-condition half-buffer variety works well for buffers and copies without logic. The precharge-logic half-buffering is the simplest good way to implement most logic cells. The precharge-logic full-buffering has an advantage in speed and is good at decoupling the handshakes of neighboring units. It should be used when necessary to improve the throughput.
Although only a few embodiments have been described in detail above, other embodiments are contemplated by the inventor and are intended to be encompassed within the following claims. In addition, other modifications are contemplated and are also intended to be covered.