I remember designing my first ASIC back in the very early 1980s. By today's standards, that was a tiny device containing only around 2,000 equivalent gates. On the other hand, 2,000 is a lot of gates when you are capturing your design in the form of hand-drawn gate/register-level schematics.
At that time, we performed timing analysis by hand. We identified what we believed to be the critical paths and then added all the delays in those paths. We didn’t have access to any form of prototyping or verification technology. Functional verification was performed by gathering a group of one's peers, sitting them around a table, and walking them through your gate-level design. Assuming no one spotted any problems, you were "good to go."
Today, of course, ASICs (which I take to include ASSPs and SoCs) can comprise tens of millions of equivalent gates. Modern design practices include capturing the design at a high-level of abstraction, coupled with synthesis technology, all augmented by the use of third-party intellectual property (IP) cores.
Meanwhile, one of the more popular forms of verification for one's ASIC designs is to use an FPGA-based prototyping system. There are a number of such systems around, each offering various advantages and capabilities. For example, Pro Design's products and services include the proFPGA family of ASIC prototyping systems.
The proFPGA system offers a modular, scalable, multi-FPGA solution. The latest addition to the proFPGA family is the cost-optimized proFPGA uno Virtex 7 FPGA-based prototyping system, which is ideal for tasks like IP verification and pre-silicon software development.
In addition to the proFPGA uno motherboard, various pluggable FPGA-based modules can be added as required. These modules employ different Xilinx Virtex 7 FPGA devices, such as the XC7VX330T, XC7V585T, XC7VX690T, and XC7V2000T, thereby allowing the user to select the desired capacity and performance.
— Max Maxfield, Editor of All Things Fun & Interesting