This article is from the third quarter edition 2012 of the Xcell Journal, by Xilinx Inc.
Current and future NASA robotic-flight missions to outer planets and asteroids require avionics systems, computers, controllers and data-processing units capable of enduring the extreme low-temperature environments of deep space and lunar and Martian surfaces. With recent technological advances in FPGAs, it has become possible to architect a complete system-on-a-chip (SoC) using a single FPGA. Large FPGAs that are radiation-hardened by design (RHBD) have increased the number of gates per square inch, reduced power consumption per gate and included microprocessors, soft and hard IP, arithmetic modules, sizable onboard memory and analog-to-digital converters.
B&A Engineering (BAENG) conducted studies with the Xilinx Virtex-5 mixed-signal RHBD FPGA to address NASA’s need for protected, reliable data-acquisition controllers and computer electronics able to operate in cryogenic temperatures. This RHBD FPGA will be the workhorse of future NASA computer and data-handling systems targeted for outer-planet landing, orbiting and sample-retrieval missions.
To conduct the experiment, BAENG designed and built a test board based on a commercial Xilinx XC5VLX30 FPGA and support circuitry (resistors, capacitors and oscillator), as shown in Figure 1
. What’s remarkable is that we found that the chip works at temperatures well below spec for a commercial part and even well below spec for a space-grade Xilinx FPGA.
Figure 1 – The Xilinx Virtex-5, XC5VLX30 test board
The FPGA included circuits using internal phase-locked loops (PLLs), as well as a ring oscillator and a number of basic circuits built from LUTs. During the test, we monitored both circuit functionality and FPGA power consumption.
We disabled all the regulators, switches, resets and configuration-mode pins on the board with the exception of the 100-MHz oscillator. We simulated FPGA and external flash memory voltages and currents, switches, resets and configuration-mode pins and monitored them using external test equipment and power supplies.
The FPGA was reconfigured at every 10-degree decrement of temperature, from room temperature down to -150°C, from both the JTAG interface (Xilinx IMPACT) and flash (XCF08). We erased and reprogrammed onboard flash during each temperature measurement. Additionally, using Xilinx’s ChipSope Pro and the internal FPGA system monitor, we monitored Xilinx die temperature, along with 2.5V auxiliary and 1.0V internal voltages. This data provided additional reference points to the chamber and test equipment monitoring. The internal system monitor can be accessed preconfiguration through the JTAG interface.