Why Use DSP?Digital Signal Processing 101 An introductory course in DSP system design: Part 1 Also see: (Part 2) (Part 3) (Part 4)
by David Skolnick and Noam Levine
What is [a] DSP? In brief, DSPs are processors or microcomputers whose hardware, software, and instruction sets are optimized for high-speed numeric processing applications an essential for processing digital data representing analog signals in real time. What a DSP does is straightforward. When acting as a digital filter, for example, the DSP receives digital values based on samples of a signal, calculates the results of a filter function operating on these values, and provides digital values that represent the filter output; it can also provide system control signals based on properties of these values. The DSPs high-speed arithmetic and logical hardware is programmed to rapidly execute algorithms modelling the filter transformation.
The combination of design elements arithmetic operators, memory handling, instruction set, parallelism, data addressing that provide this ability forms the key difference between DSPs and other kinds of processors. Understanding the relationship between real-time signals and DSP calculation speed provides some background on just how special this combination is. The real-time signal comes to the DSP as a train of individual samples from an analog-to-digital converter (ADC). To do filtering in real-time, the DSP must complete all the calculations and operations required for processing each sample (usually updating a process involving many previous samples) before the next sample arrives. To perform high-order filtering of real-world signals having significant frequency content calls for really fast processors.
WHY USE A DSP?
Useful additions would include: passband tuning and width control stopband rolloff control.
As Figure 1 shows, an analog approach using second-order filters would require quite a few staggered high-Q sections; the difficulty of tuning and adjusting it can be imagined.
Figure 1. An ideal bandpass filter and second-order approximations.
Figure 2. Filter equations and delay-line representation.
Approximating an ideal filter consists of applying a transfer function with appropriate coefficients and a high enough order, or number of taps (considering the train of input samples as a tapped delay line). Figure 3 shows the response of a 90-tap FIR filter compared with sharp-cutoff Chebyshev filters of various orders. The 90-tap example suggests how close the filter can come to approximating an ideal filter. Within a DSP system, programming a 90-tap FIR filter like the one in Figure 3 is not a difficult task. By comparison, it would not be cost-effective to attempt this level of approximation with a purely analog circuit. Another crucial point in favor of using a DSP to approximate the ideal filter is long-term stability. With an FIR (or an IIR having sufficient resolution to avoid truncation-error buildup), the programmable DSP achieves the same response, time after time. Purely analog filter responses of high order are less stable with time.
Figure 3. 90-tap FIR filter response compared with those of sharp cutoff Chebyshev filters.
Real-world phenomena are analog the continuously changing energy levels of physical processes like sound, light, heat, electricity, magnetism. A transducer converts these levels into manageable electrical voltage and current signals, and an ADC samples and converts these signals to digital for processing. The conversion rate, or sampling frequency, of the ADC is critically important in digital processing of real-world signals.
This sampling rate is determined by the amount of signal information that is needed for processing the signals adequately for a given application. In order for an ADC to provide enough samples to accurately describe the real-world signal, the sampling rate must be at least twice the highest-frequency component of the analog signal. For example, to accurately describe an audio signal containing frequencies up to 20 kHz, the ADC must sample the signal at a minimum of 40 kHz. Since arriving signals can easily contain component frequencies above 20 kHz (including noise), they must be removed before sampling by feeding the signal through a low-pass filter ahead of the ADC. This filter, known as an anti-aliasing filter, is intended to remove the frequencies above 20 kHz that could corrupt the converted signal.
However, the anti-aliasing filter has a finite frequency rolloff, so additional bandwidth must be provided for the filters transition band. For example, with an input signal bandwidth of 20 kHz, one might allow 2 to 4 kHz of extra bandwidth.
Figure 4. Antialiasing filter ideal response.
The ADC sampling rate depends on the bandwidth of the analog signal being sampled. This sampling rate sets the pace at which samples are available for processing. Once the system bandwidth requirements have established the A/D converter sampling rate, the designer can begin to explore the speed requirements of the DSP processor.
Processing speed at a required sample rate is influenced by algorithm complexity. As a rule, the DSP needs to finish all operations relating to the first sample before receiving the second sample. The time between samples is the time budget for the DSP to perform all processing tasks. For the audio example, a 48-kHz sampling rate corresponds to a 20.833-µs sampling interval. Figure 5 relates the analog signal and digital sampling rate.
Figure 5. Sampling train and processing time.
Thus if all of the time between samples is available for operations to implement the algorithm, a processor with a performance level of 2.4 MOPS is required. Note that the two common ratings for DSPs, based on operations per second (MOPS) and instructions per second (MIPS), are not the same. A processor with a 10-MIPS rating that can perform 8 operations per instruction has basically the same performance as a faster processor with a 40 MIPS rating that can only perform 2 operations per instruction.
SAMPLING VARIOUS REAL-WORLD SIGNALS
Figure 6. Example of continuous processing of samples in digital filter.
Frame-based systems, like a spectrum analyzer, which determines the frequency components of a time-varying waveform, acquire a frame (or block of samples). Processing occurs on the entire frame of data and results in a frame of transformed data, as shown in Figure 7.
Figure 7. Example of batch processing of a block of data.
For an audio sampling rate of 48 kHz, a processor working on a frame of 1024 samples has a frame acquisition interval of 21.33 ms (i.e., 1024 x 20.833 µs = 21.33 ms). Here the DSP has 21.33 ms to complete all the required processing tasks for that frame of data. If the system handles signals in real time, it must not lose any data; so while the DSP is processing the first frame, it must also be acquiring the second frame. Acquiring the data is one area where special architectural features of DSPs come into play: Seamless data acquisition is facilitated by a processors flexible data-addressing capabilities in conjunction with its direct memory-accessing (DMA) channels.
RESPONDING TO REAL-WORLD SIGNALS
Interrupt latency (response delay) depends on several factors; the most dominant is the DSP architectures instruction pipelining. An instruction pipeline consists of the number of instruction cycles that occur between the time an interrupt is received and the time that program execution resumes. More pipeline levels in a DSP result in longer interrupt latency. For example, if a processor has a 20-ns cycle time and requires 10 cycles to respond to an interrupt, 200 ns elapse before it executes any signal-processing instructions.
When data is acquired one sample at a time, this 200-ns overhead will not hurt if the DSP finishes the processing of each sample before the next arrives. When data is acquired sample-by-sample while processing a frame at a time, however, an interrupted system wastes processor instruction cycles. For example, a system with a 200-ns interrupt response time running a frame-based algorithm, such as the FFT, with a frame size of 1024 samples, would require 204.8 µs of overhead. That amounts to more than 10,000 instruction cycles wasted to latency productive time when the DSP could be performing signal processing. This waste is easy to avoid in DSPs having architectural features such as DMA and dual memory access; they let the DSP receive and store data without interrupting the processor.
DEVELOPING A DSP SYSTEM
Figure 8. Putting together elements of a DSP system.
Note how few components make up the DSP system, because so much of the systems functionality comes from the programmable DSP. Converters funnel data into and out of the DSP; the ADC timing is controlled by a precise sampling clock. To simplify system design, many converter devices available today combine some or all of the following: an A/D converter, a D/A converter, a sampling clock, and filters for anti-aliasing and anti-imaging. The clock oscillator in these types of I/O components is separately controlled by an external crystal. Here are some important points about the data flow in this sort of DSP system:
Analog Input: The analog signal is appropriately band-limited by the anti-aliasing filter and applied to the input of the ADC. At the selected sampling time, the converter interrupts the DSP processor and makes the digital sample available. The choice between serial and parallel interfacing between the ADC and DSP depends on the amount of data, design complexity trade-offs, space, power, and price.
Digital Signal Processing: The incoming data is handled by the DSPs algorithm software. When the processor completes the required calculations, it sends the result to the DAC. Because the signal processing is programmable, considerable flexibility is available in handling the data and improving system performance with incremental programming adjustments.
Analog Output: The DAC converts the DSPs output into the desired analog output at the next sample clock. The converters output is smoothed by a low-pass, anti-imaging filter (also called a reconstruction filter), to produce the reconstructed analog signal.
Host Interface: An optional host interface lets the DSP communicate with external systems, sending and receiving data and control information.
REVIEW AND PREVIEW
Because these issues involve many valuable levels of detail that we could not do justice to in this brief article, you should consider reading Richard Higginss text, Digital Signal Processing in VLSI (see References below). This text provides a complete overview of DSP theory, implementation issues, and reduction to practice (with devices available at the time it was published), plus exercises and examples. The Reference section below also contains other sources that further amplify this articles issues. To prepare for the next articles in this series, you might want to get free copies of the ADSP-2100 Family Users Manual* and the ADSP-2106x SHARC Users Manual.* These texts provide information on Analog Devicess fixed- and floating-point DSP architectures, a major topic in these articles. The next article will cover the following territory:
DSP architecture: The article will discuss the nature and functioning of the DSPs arithmetic-logic unit (ALU), multiply-accumulator (MAC), barrel-shifter, and memory busses and describe the numeric operations that support DSP functions.
DSP programming concepts: A discussion of programming will bring together theory and practice (math and architecture). Finally, it will lay out the main parameters for a series-length DSP design project, provided as an example.
Higgins, R. J. Digital Signal Processing in VLSI, Englewood Cliffs, NJ: Prentice Hall, 1990. DSP basics. Includes a wide-ranging bibliography. Available for purchase from ADI.
Mar, A., ed. Digital Signal Processing Applications Using the ADSP-2100 Family Volume 1, Englewood Cliffs, NJ: Prentice Hall, 1992. Available for purchase from ADI.
Mar, A., Babst, J., eds. Digital Signal Processing Applications Using the ADSP-2100 Family Volume 2, Englewood Cliffs, NJ: Prentice Hall, 1994. Available for purchase from ADI.
Dearborn, G., ed. Digital Signal Processing Applications Using the ADSP-21000 Family Volume 1, Norwood, MA: Analog Devices, Inc., 1994. Available for purchase from ADI.
*Mar, A., Rempel, H., eds. ADSP-2100 Family Users Manual, Norwood, MA: Analog Devices, Inc., 1995. Free.
Mar, A., Rempel, H., eds. ADSP-21020 Family Users Manual, Norwood, MA: Analog Devices, Inc., 1995. Free.
*Rempel, H., ed. ADSP-21060/62 SHARC Users Manual, Norwood, MA: Analog Devices, Inc., 1995. Free.