SAN FRANCISCO - Spin torque MRAM is a nonvolatile memory technology said to combine high speed operations with low power.
During the International Electron Device Meeting (IEDM) here, IBM, Samsung and the Hynix-Grandis duo presented papers on the topic. Spin torque MRAM, or STT RAM, is a next-generation MRAM technology.
At IEDM, the IBM-MagIC MRAM Alliance-the joint MRAM venture between IBM and TDK Corp.-disclosed details of its technology-a perpendicular spin torque MRAM. ''We report data from 4-kbit spin torque MRAM arrays using tunnel junctions (TJs) with magnetization perpendicular to the wafer plane,'' according to the paper.
''We show for the first time the switching distribution of perpendicular spin torque junctions,'' according to the paper. ''The percentage switching voltage width, alpha(Vc)/<Vc> = 4.4 percent, is sufficient to yield a 64-Mb chip,'' according to the paper.
''Furthermore we report switching probability curves down to error probabilities of 5x10-9 per pulse which do not show the anomalous switching seen in previous studies of in-plane magnetized bits,'' according to the paper. ''We have examined in detail the requirements for a 64 Mb MRAM in 90-nm technology with 2-bit error correction code (ECC). Write currents need to be limited to of order 350 µA in order to keep the cell size reasonable.''
Samsung Electronics Co. Ltd. is taking another approach. ''Feasibility of STT-MRAM as next generation nonvolatile memory has been tested for the replacement of DRAM and NOR flash,'' according to Samsung.
''We report that the cell characteristics of on-axis STT-MRAM with 6 ~ 8F2 are similar to those of off-axis STT-MRAM with 12 ~ 16F2. In addition, we suggest a novel MTJ (magnetic tunnel junction) with the operation current density of 0.8 MA/cm2,'' according to the company. ''These results open a way to scale STT-MRAM down to sub-30-nm technology node using present technology. By further material engineering of ferromagnetic electrode and MTJ structure design, the usage of present technology could be extended down to sub-20-nm node.''
The team of Hynix Semiconductor Inc. and Grandis Inc. are taking another approach. ''A compact STT (spin-Transfer Torque)-RAM with a 14F2 cell was integrated using modified DRAM processes at the 54-nm technology node,'' according to the firms. 'The basic switching performance (RH and R-V) of the MTJs and current drivability of the access transistors were characterized at the single bit cell level.''
Unlike IBM, Hynix and Grandis ''used in-plane MTJs rather than PMA (perpendicular magnetic anisoatropy) MTJs. Although many research groups have tried to develop productive PMA MTJs, the PMA MTJ still has several technical hurdles such as difficult PMA film growth and high damping constant. Also, we do not yet have confidence that PMA MTJs can have better scalability than in-plane MTJs in terms of thermal stability and switching current.''
@uhrmannt, thanks a lot for explaining the differences between the two technologies...it helps me a lot!
How are the Everspin devices performing in the field? Any idea how reliable they are and any technical advantage the offer compared to traditional semiconductor technology?
Indeed Everspin is on the market with MRAM already for a couple of years. However, their technology is highly different to the STT technology, despite relying on the same tunneling magneto resistance (TMR) effect.
Everspin uses TMR junctions with a size being in the size of couple of hundred nanometers. These mainly elliptical junctions face that problem that their remagnetization/switching field is increasing largely when shrinked down (where the socalled paramagnetic state marks the fundamental limit). This issue of a increasing switching field in combination with their matrix grid switching (a current pulse is applied to a wire grid, where the wires cross the oersted field superposes to a value high enough to switch the cell underneath) introduce the scaling down border of this technology.
For SST the switching is by usage of the spin torque effect. In this case the current density of spin polarized current transversing the tunnel junctions has to be huge in order to reverse or change the magentic state and therefore store the information. Mostly the material issues as well as reliability are stating the issues of this new technology.
Everspin (spin-off of Freescale Semiconductor Inc) already has MRAM chips in their product portfolio for quite some time. The density is upto 16Mb for the 16-bit devices. I don't understand the technologies well, but my guess is that the STT-MRAM is a new technology targeted to scale it down, increase its density enough for it to be capable of replacing the DRAM. If I understand correctly, I feel this manufacturers are desperate to overcome the last few hurdles and lunch these products commercially in not more than 2 years. Any different opinion?
I wonder how long will it take for spin based devices to be used in real products...this will mark a major breakthrough in EE: instead of currents, voltages or charges we will be relying on something quite esoteric as a spin of electron...anyone taking bets how many years to production? Kris