The objective is to get the least amount of impedance (inductance)
between the power consumer (asic) and charge storage (capacitor).
That is usually accomplished by placing vias from the cap to the power
planes, and then vias from the power planes to the asic. Traces
make a lot of inductance. Manufacturing soldering rules generally
do not allow you to put a via directly under a surface mount pad
for an asic or a capacitor (at least with IR reflow).