|Publication number||US7122849 B2|
|Application number||US 10/707,018|
|Publication date||Oct 17, 2006|
|Filing date||Nov 14, 2003|
|Priority date||Nov 14, 2003|
|Also published as||CN1879227A, CN100468785C, EP1683187A2, EP1683187A4, EP1683187B1, US7488658, US20050106799, US20080064172, WO2005050701A2, WO2005050701A3, WO2005050701A8|
|Publication number||10707018, 707018, US 7122849 B2, US 7122849B2, US-B2-7122849, US7122849 B2, US7122849B2|
|Inventors||Bruce B Doris, Michael P Belyansky, Diane C Boyd, Dureseti Chidambarrao, Oleg Gluschenkov|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (101), Non-Patent Citations (17), Referenced by (2), Classifications (41), Legal Events (4) |
|External Links: USPTO, USPTO Assignment, Espacenet|
Stressed semiconductor device structures having granular semiconductor material
US 7122849 B2
A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.
1. A semiconductor device structure, comprising:
a first semiconductor device having a first gate stack, and
a second semiconductor device having a second gate stack; wherein said first gate stack includes a first semiconductor material having an average grain size of less than approximately 30 nm, and wherein said second gate stack includes a second semiconductor material having an average grain size of greater than approximately 30 nm, said structure further comprising a first channel disposed below said first gate stack, and a second channel disposed below said second gate stack; wherein the second gate stack imparts a compressive stress to the second channel in a range of approximately −200 MPa to approximately −600 MPa, while the first gate stack imparts a compressive stress to the first channel in a range of approximately −10 MPa to approximately −100 MPa.
2. The structure as claimed in claim 1, wherein said first semiconductor material is a grained polysilicon.
3. The structure as claimed in claim 1, wherein said first semiconductor device is an FET and said second semiconductor device is a pFET.
4. The structure as claimed in claim 1, further comprising an isolation region disposed between said first semiconductor device and said second semiconductor device.
5. The structure as claimed in claim 1, wherein said second semiconductor material is a grained polysilicon.
6. The structure as claimed in claim 1, further comprising a third semiconductor material and a fourth semiconductor material, wherein said first semiconductor material is disposed on said third semiconductor material and wherein said second semiconductor material is disposed on said fourth semiconductor material.
7. The structure as claimed in claim 6, wherein said third semiconductor material is a small grained polysilicon and said fourth semiconductor material is a small grained polysilicon.
BACKGROUND OF INVENTION
The present invention relates to semiconductor device structures, such as a CMOS device structure including both FET and pFET devices.
Mobility enhancements are important to future semiconductor, e.g. CMOS device technologies. Performance improvements from conventional process technologies are becoming extremely difficult to achieve. Methods to stress Si channels include: using SiGe which imparts stress from the bottom of the channel; different shallow trench isolation (STI) material choices which impart stresses from various sides, and SiN etch stop layers which also impart longitudinal stress from the sides. Drawbacks from the SiGe buffer layer or implanted-anneal-buffer approach with a strained Si cap layer are well known. Drawbacks include dislocations that impact yield severely, along with significant difficulty controlling As diffusion enhancements. Further, the process is quite complicated and costly. The STI approach is less costly but is not self-aligned to the gate and has RX size sensitivity. The less costly approach of using nitride etch stop layers to create stress does produce some benefit, but the benefit is believed to be relatively marginal.
SUMMARY OF INVENTION
The present invention improves device performance using channel mobility enhancement. The present invention improves mobility from the top of the channel by using the stress properties of properly modulated polysilicon gate stacks. Prior to the prevent invention these stress properties were very difficult to control. However, the present invention includes a method and structure which use small grain polysilicon to control stress properties. The present invention provides a method and a structure to impart compressive stress to the pFET channel and a tensile stress to the FET channel. Other embodiments include imparting compressive stress to the pFET channel while preventing compressive stress from being imparted to the FET channel. Another embodiment of this invention includes imparting tensile stress to the FET channel while preventing the tensile stress from being imparted to the pFET channel.
The method of the present invention disposes (e.g., deposits) small grain poly Si films in gate electrode stacks, which films become highly tensile as a result of annealing. The tensile film stress can be suppressed by annealing with a low temperature deposited SiN film disposed on top of the poly Si film.
It is a principal object of the present invention to enhance channel mobility in semiconductor devices.
According to the present invention, a method of fabricating a semiconductor device structure includes providing a substrate; providing an electrode on the substrate; forming a recess in the electrode, the recess having an opening; disposing a small grain semiconductor material within the recess; covering the opening to contain the small grain semiconductor material within the recess, and then annealing the resultant structure. The present invention also includes a semiconductor device structure.
Further and still other objects of the present invention will become more readily apparent in light of the following detailed description when taken in conjunction with the accompanying drawing figures.
BRIEF DESCRIPTION OF DRAWINGS
FIGS. 1–9 are side schematic views of process steps according to a preferred embodiment of the present invention.
FIG. 10 is a diagram showing simulated stress contours in the gate and channel of the preferred inventive structure.
Turning now to the figures, and FIG. 1 in particular, a semiconductor substrate 1 is provided. The semiconductor substrate is a bulk Si substrate, an SOI substrate, or a stressed (strained) Si substrate. Alternatively, the substrate is a hybrid substrate which includes more than one surface orientation. The substrate alternatively includes a semiconductor material other than Si, such as Ge or any combination of Group III–V elements or Group II–V elements.
After an initial substrate cleaning procedure (conventional), an isolation scheme is carried out. As is well known in semiconductor manufacturing, the isolation scheme is used to separate selected devices electrically from each other. The isolation scheme may be a standard or a modified shallow trench isolation (STI) scheme. The STI 2 is shown in FIG. 1. Alternatively, the isolation is accomplished using a LOCOS process or mesa isolation scheme, as is well known in the art of fabricating semiconductor devices. For various known or conventional processes for fabricating semiconductor devices, see VLSI Technology, 2nd Edition, by S. M. Sze, (McGraw Hill Publishing Co., 1988).
After isolation 2 is formed, a conventional gate oxide pre-cleaning process is performed. As is the case in high performance logic fabrication processes, various conventional gate oxide processes may be used to fabricate devices having different gate oxide thicknesses. The gate oxide 3 is formed, for example, using a conventional thermal oxidation process. The oxide 3 is formed using N20, NO, O2 or any combination of them. The oxide may be nitridized using a conventional plasma process. Alternatively, the gate oxide may be formed using a base oxide followed by deposition of a high k gate dielectric such as aluminum oxide, or hafnium oxide, or another high k gate dielectric. The gate dielectric material 3 has an approximately (+10%) uniform thickness in the range of about (+10%) 0.6 nm to about 7 nm.
Next, a film 4 is deposited over the entire wafer structure 1, 2, 3. The film 4 is used as a disposable (removable) or semi-disposable gate electrode material. In a preferred embodiment, the film 4 includes a polysilicon (poly Si) material having an approximately uniform thickness or height (T) in the range of about 80 nm to about 150 nm. A deposition technique such as low pressure chemical vapor deposition (LPCVD) or rapid thermal chemical vapor deposition (RPCVD) is used to deposit the removable gate electrode material 4. The resulting structure is shown in FIG. 1. The poly Si layer 4 preferably has a standard grain size in a range of about one nm to about 40 nm.
Next, a conventional lithography process is used to pattern photoresist images on the top of the removable gate electrode material 4. The photoresist images, not shown in the figures, are used to transfer desired features into the removable gate electrode material 4 by using a conventional dry etching process. The dry etching process includes or several chemistries capable of etching the removable gate electrode material 4 selectively with respect to the gate oxide material 3. The structure shown in FIG. 2 shows the fully patterned removable gate electrode 5 for a FET gate stack 3,5 and a removable gate electrode 6 for a pFET gate stack 3,6.
A conventional gate reoxidation process, not shown in the figures, is then used, as is commonly done in high performance logic manufacturing processes. The reox is formed by using a thermal oxidation process to achieve an approximately uniform thickness from about one nm to about 7 nm. Following the reox process, a block mask is patterned over the pFET regions, using a conventional photolithography process. The block (e.g., resist) mask (not shown in the figures) is used to block or prevent the pFET regions from being implanted, while the appropriate FET regions are being implanted. The FET extensions 7 and halos (not shown) are implanted using a low energy As and B implant, respectively. The resist mask is then removed using a dry or wet process. Another block mask (not shown) is patterned over the FET regions. The pFET extensions 8 and halos (not shown) are implanted using a low energy BF2 or B implant and As implant, respectively. The extension implant profiles 7,8 for the FET and the pFET are shown in FIG. 2.
After the extension and halo implantation, a dielectric liner layer 9 is formed over the entire wafer structure (FIG. 3). The dielectric film to be used as the liner layer 9 is preferably SiN which is deposited by CVD or RTCVD or any other suitable deposition technique. A purpose of the liner layer 9 is to provide a CMP stop layer for the next process. Additionally, the SiN liner 9 will be etched, at a later point in the process flow, to form a source-drain spacer. The resulting structure is shown in FIG. 3.
The next step in the process flow is to deposit an oxide film 10. The oxide film 10 is deposited and planarized using chemical mechanical polishing (CMP). The film 10 is deposited using, for example a high density plasma (HDP) process. The top of the liner 9 over the removable gate electrode 5 is removed by using a dry etching process that is capable of etching silicon nitride but does not etch appreciable amounts of oxide or poly Si. The planarized oxide film 10 and SiN liner 9 structure is shown in FIG. 4, after the top portion of the liner layer 9 has been removed.
An important aspect of this invention is that, at this point in the inventive process flow, a gate recess process is used to remove the poly Si, either completely or partially, from the gate electrodes 5, 6. A preferred embodiment in which the poly Si is partially removed is shown in FIG. 5. The poly Si is recessed using any suitable dry or wet etch process. A portion 12 and a portion 13 of the original poly Si is left remaining, and has an approximately uniform thickness in a range of about one nm to about 20 nm. A recessed portion 12 of the FET gate electrode and a recessed portion 13 of the pFET gate electrode are shown in FIG. 5. In another embodiment (not shown), the poly Si is completely removed. If this embodiment is used, then a conventional gate oxide pre-clean process followed by a conventional gate oxidation process is next performed.
Another important aspect of this invention is that, following the gate recess process, a small grain poly Si is deposited over the entire wafer. Small grain polysilicon is known from Shimizu, S. et al. Proceedings of the 1997 Symposium on VLSI Technology, Kyoto, Japan 10–12 Jun. 1997, and also from Silicon Processing for The VLSI Era, Vol 1—Process Technology, by S. Wolf, 1999. The grain structure preferably is in a range of about one nm to about 50 nm. A more preferable grain size is a substantially uniform size in a range of about five nm to 30 nm. The polySi is deposited by RTCVD or LPCVD. Next, the polySi is planarized and recessed from the top of the oxide layer 10 using, for example, CMP and a dry etch. Both CMP and dry etch processes are capable of removing the poly Si selectively relative to the SiO2 layer 10. After CMP and dry etch, the inventive gate electrode structure 14, 12 for the FET and the inventive gate electrode structure 13, 18 for the pFET are shown in FIG. 6.
At this point in the inventive method, a hard mask 15 shown in FIG. 7 is patterned over the FET region. The mask 15 is patterned using a dielectric film including SiN and a conventional photolithography procedure. The hard mask 15 is deposited using a low temperature deposition process such as plasma enhanced chemical vapor deposition with a temperature in the range of about 350° C. to about 700° C. Preferably, the material which forms the hard mark 15 is deposited at a temperature below 550° C. or lower, to prevent re-growth of the poly Si grains. The whole structure is next subjected to an anneal using a temperature from about 500° C. to about 600° C. for about one hour. Alternatively, a rapid thermal anneal may be carried out at about 700° C. to about 1000° C. for about one second to about seven seconds. In another embodiment, the structure 12, 14 is annealed at a future point in the process. The small grain poly Si remains small, in the range preferably of about five nm to about 30 nm for the FET gate electrode portion 17 because the SiN cap layer 15 is present. However, the grains in the pFET gate electrode portion 18 grow significantly to grain sizes of greater than about 30 nm.
The present inventors believe that the inventive process (e.g., with respect to FIG. 7) represents a notable departure from conventional process technology. If the small grain poly Si is subjected to the standard thermal budget, then the poly Si grain growth causes a severe increase in tensile stress. The tensile stress creates a compressive stress in the channel region which degrades electron mobility and limits the performance for the FET. See the simulations of FIG. 10. The inventors believe that the grain growth and resulting severe increase in tensile stress is almost completely eliminated by annealing with the SiN hard mask 15 disposed over the FET region. The grain structure can be optimized for each device independently by depositing the small grain poly Si into the recess and annealing the FET with the SiN hard mask. This step appears to result in a notable improvement in FET device performance.
The next step in the inventive process is to remove the SiN hard mask 15 from the entire horizontal part of the oxide film 10 or from the entire horizontal part (except over the portion 17, as shown in FIG. 8). Because the poly Si was recessed as described previously, a portion 19 of the hard mask 15 is left remaining (disposed) in the recessed hole as shown in FIG. 8. The purpose of the structure 19 is to prevent the grains from growing during subsequent conventional thermal cycles common in standard state-of-the art semiconductor manufacturing process technology. After the SiN etch, the oxide film 10 is removed using a suitable dry or wet etch process capable of removing the SiO2 film selectively relative to the SiN and the poly Si materials. A dry directional etch process is next performed on the liner layer 9 to form the spacers 20, 25 as shown in FIG. 8. Although not essential for the present invention, the spacers 20 of the pFET and the spacers 25 of the FET may have differing heights as shown. A similar block mask and implant process as was used to form the FET and pFET extension regions 7, 8 is used to form the FET source-drain regions 21 and the pFET source-drain region 22 shown in FIG. 8. A rapid thermal anneal is next performed to activate the junctions. Because the FET continues to have the SiN layer 19 present, grain growth in the FET gate is suppressed, thereby minimizing the tension in the gate electrode stack 3, 12, 17 and subsequent compression in the channel region below the stack.
The remaining portion 19 over the gate electrode stack is next removed using a wet or dry etch process. Next, a suicide pre-cleaning process is carried out followed by a conventional silicide process. See FIG. 9 and silicide 23. Standard back-end-of-line processing is done including pre-metal dielectric deposition and planarization, contact etch, contact liner formation and contact formation, followed by metal wiring and final chip fabrication, all not shown.
Simulation results indicate that the tensile stress level in uncapped polySi increases by about 600 MPa to about 1200 MPa as a result of annealing for about one hour at a temperature of about 600° C., while the capped polySi increases in tensile stress by only about 10 MPa. Our simulation results show that about 33% to about 50% of the stress in the gate material (with the opposite sign with respect to the gate stress) can be translated into the channel region. Thus, the uncapped gate stack imparts−200 MPa to −300 MPa, while the capped gate stack translates little or no stress into the channel region. One simulation of stress contours is shown in the diagram of FIG. 10.
While there has been shown and described what is at present considered the preferred embodiments of the present invention, it will be apparent to those killed in the art that various changes and modifications may be made therein without departing from the spirit and scope of the present invention which shall be limited only by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3602841||Jun 18, 1970||Aug 31, 1971||Ibm||High frequency bulk semiconductor amplifiers and oscillators|
|US4665415||Apr 24, 1985||May 12, 1987||International Business Machines Corporation||Field-effect transistor|
|US4853076||Jul 9, 1987||Aug 1, 1989||Massachusetts Institute Of Technology||Heat treatment while crystallizing to produce tensile stress which produces electron mobility|
|US4855245||Oct 4, 1988||Aug 8, 1989||Siemens Aktiengesellschaft||Method of manufacturing integrated circuit containing bipolar and complementary MOS transistors on a common substrate|
|US4952524||May 5, 1989||Aug 28, 1990||At&T Bell Laboratories||Diffusion barrier layer; thermal stress-relieving layer|
|US4958213||Jun 12, 1989||Sep 18, 1990||Texas Instruments Incorporated||Method for forming a transistor base region under thick oxide|
|US5006913||Nov 2, 1989||Apr 9, 1991||Mitsubishi Denki Kabushiki Kaisha||Stacked type semiconductor device|
|US5060030||Jul 18, 1990||Oct 22, 1991||Raytheon Company||Pseudomorphic HEMT having strained compensation layer|
|US5081513||Feb 28, 1991||Jan 14, 1992||Xerox Corporation||Electronic device with recovery layer proximate to active layer|
|US5108843||Nov 27, 1989||Apr 28, 1992||Ricoh Company, Ltd.||Thin film semiconductor and process for producing the same|
|US5134085||Nov 21, 1991||Jul 28, 1992||Micron Technology, Inc.||Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories|
|US5310446||Jul 13, 1992||May 10, 1994||Ricoh Company, Ltd.||Single crystal semiconductor films superimposed to form multilayer element, applying energy to melt and cooling|
|US5354695||Apr 8, 1992||Oct 11, 1994||Leedy Glenn J||Membrane dielectric isolation IC fabrication|
|US5371399||Aug 9, 1993||Dec 6, 1994||International Business Machines Corporation||Compound semiconductor having metallic inclusions and devices fabricated therefrom|
|US5391510||Apr 7, 1994||Feb 21, 1995||International Business Machines Corporation||A diamond-like-carbon layer is used as masking structure to protect gate dielectric layer from contamination during high temperature annealing, removal by plasma etching, forming metal gate electrode in space vacated by masking layer|
|US5459346||Nov 17, 1994||Oct 17, 1995||Ricoh Co., Ltd.||Semiconductor substrate with electrical contact in groove|
|US5471948||May 11, 1994||Dec 5, 1995||International Business Machines Corporation||Method of making a compound semiconductor having metallic inclusions|
|US5557122||May 12, 1995||Sep 17, 1996||Alliance Semiconductors Corporation||Semiconductor electrode having improved grain structure and oxide growth properties|
|US5561302||Sep 26, 1994||Oct 1, 1996||Motorola, Inc.||Enhanced mobility MOSFET device and method|
|US5565697||Jun 2, 1995||Oct 15, 1996||Ricoh Company, Ltd.||Semiconductor structure having island forming grooves|
|US5571741||Jun 7, 1995||Nov 5, 1996||Leedy; Glenn J.||Membrane dielectric isolation IC fabrication|
|US5592007||Jun 7, 1995||Jan 7, 1997||Leedy; Glenn J.||Membrane dielectric isolation transistor fabrication|
|US5592018||Jun 7, 1995||Jan 7, 1997||Leedy; Glenn J.||Membrane dielectric isolation IC fabrication|
|US5670798||Mar 29, 1995||Sep 23, 1997||North Carolina State University||Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same|
|US5679965||Nov 9, 1995||Oct 21, 1997||North Carolina State University||Continuously graded layers of aluminum gallium nitride to reduce or eliminate conduction band or valence band offsets|
|US5683934||May 3, 1996||Nov 4, 1997||Motorola, Inc.||Enhanced mobility MOSFET device and method|
|US5840593||Mar 10, 1997||Nov 24, 1998||Elm Technology Corporation||Membrane dielectric isolation IC fabrication|
|US5861651||Feb 28, 1997||Jan 19, 1999||Lucent Technologies Inc.||Second layer of doped polycrystalline silicon separated by nitrogen doped silicon oxide|
|US5880040||Apr 15, 1996||Mar 9, 1999||Macronix International Co., Ltd.||Gate dielectric based on oxynitride grown in N2 O and annealed in NO|
|US5940736||Mar 11, 1997||Aug 17, 1999||Lucent Technologies Inc.||Method for forming a high quality ultrathin gate oxide layer|
|US5946559||Jun 7, 1995||Aug 31, 1999||Elm Technology Corporation||Method of forming a field effect transistor|
|US5960297||Jul 2, 1997||Sep 28, 1999||Kabushiki Kaisha Toshiba||Shallow trench isolation structure and method of forming the same|
|US5989978||Jul 16, 1998||Nov 23, 1999||Chartered Semiconductor Manufacturing, Ltd.||Shallow trench isolation of MOSFETS with reduced corner parasitic currents|
|US6008126||Feb 23, 1998||Dec 28, 1999||Elm Technology Corporation||Membrane dielectric isolation IC fabrication|
|US6025280||Apr 28, 1997||Feb 15, 2000||Lucent Technologies Inc.||Use of SiD4 for deposition of ultra thin and controllable oxides|
|US6046464||Aug 13, 1997||Apr 4, 2000||North Carolina State University||Integrated heterostructures of group III-V nitride semiconductor materials including epitaxial ohmic contact comprising multiple quantum well|
|US6066545||Dec 7, 1998||May 23, 2000||Texas Instruments Incorporated||Birdsbeak encroachment using combination of wet and dry etch for isolation nitride|
|US6090684||Jul 29, 1999||Jul 18, 2000||Hitachi, Ltd.||Method for manufacturing semiconductor device|
|US6107143||Sep 10, 1998||Aug 22, 2000||Samsung Electronics Co., Ltd.||Method for forming a trench isolation structure in an integrated circuit|
|US6117722||Feb 18, 1999||Sep 12, 2000||Taiwan Semiconductor Manufacturing Company||SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof|
|US6133071||Oct 15, 1998||Oct 17, 2000||Nec Corporation||Semiconductor device with plate heat sink free from cracks due to thermal stress and process for assembling it with package|
|US6165383||Oct 15, 1998||Dec 26, 2000||Organic Display Technology||Anthracene derivatives having at least one reactive silyl group that is effective to form siloxane bonds|
|US6221735||Feb 15, 2000||Apr 24, 2001||Philips Semiconductors, Inc.||Method for eliminating stress induced dislocations in CMOS devices|
|US6228694||Jun 28, 1999||May 8, 2001||Intel Corporation||Method of increasing the mobility of MOS transistors by use of localized stress regions|
|US6246095||Sep 3, 1998||Jun 12, 2001||Agere Systems Guardian Corp.||System and method for forming a uniform thin gate oxide layer|
|US6255169||Feb 22, 1999||Jul 3, 2001||Advanced Micro Devices, Inc.||Process for fabricating a high-endurance non-volatile memory device|
|US6261964||Dec 4, 1998||Jul 17, 2001||Micron Technology, Inc.||Material removal method for forming a structure|
|US6265317||Jan 9, 2001||Jul 24, 2001||Taiwan Semiconductor Manufacturing Company||Top corner rounding for shallow trench isolation|
|US6274444||Aug 10, 1999||Aug 14, 2001||United Microelectronics Corp.||Method for forming mosfet|
|US6281532||Jun 28, 1999||Aug 28, 2001||Intel Corporation||Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering|
|US6281559||Mar 3, 1999||Aug 28, 2001||Advanced Micro Devices, Inc.||Gate stack structure for variable threshold voltage|
|US6284623||Oct 25, 1999||Sep 4, 2001||Peng-Fei Zhang||Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect|
|US6284626||Apr 6, 1999||Sep 4, 2001||Vantis Corporation||Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench|
|US6319794||Oct 14, 1998||Nov 20, 2001||International Business Machines Corporation||Structure and method for producing low leakage isolation devices|
|US6361885||Nov 19, 1998||Mar 26, 2002||Organic Display Technology||Anodes and cathodes for electroluminescent device|
|US6362082||Jun 28, 1999||Mar 26, 2002||Intel Corporation||Methodology for control of short channel effects in MOS transistors|
|US6368931||Mar 27, 2000||Apr 9, 2002||Intel Corporation||Thin tensile layers in shallow trench isolation and method of making same|
|US6403486||Apr 30, 2001||Jun 11, 2002||Taiwan Semiconductor Manufacturing Company||Method for forming a shallow trench isolation|
|US6403975||Apr 8, 1997||Jun 11, 2002||Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev||Components have faborable optical and electrical properties and are suitable for integration on a si substrate.|
|US6406973||Jun 29, 2000||Jun 18, 2002||Hyundai Electronics Industries Co., Ltd.||Forming separation layer|
|US6461936||Jan 4, 2002||Oct 8, 2002||Infineon Technologies Ag||Double pullback method of filling an isolation trench|
|US6476462||Dec 7, 2000||Nov 5, 2002||Texas Instruments Incorporated||MOS-type semiconductor device and method for making same|
|US6483171||Aug 13, 1999||Nov 19, 2002||Micron Technology, Inc.||Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same|
|US6493497||Sep 26, 2000||Dec 10, 2002||Motorola, Inc.||Electro-optic structure and process for fabricating same|
|US6498358||Jul 20, 2001||Dec 24, 2002||Motorola, Inc.||Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating|
|US6501121||Nov 15, 2000||Dec 31, 2002||Motorola, Inc.||Semiconductor structure|
|US6506652||Dec 9, 1999||Jan 14, 2003||Intel Corporation||Method of recessing spacers to improved salicide resistance on polysilicon gates|
|US6509618||Jan 4, 2000||Jan 21, 2003||Intel Corporation||Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates|
|US6521964||Aug 30, 1999||Feb 18, 2003||Intel Corporation||Device having spacers for improved salicide resistance on polysilicon gates|
|US6531369||Feb 14, 2002||Mar 11, 2003||Applied Micro Circuits Corporation||Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe)|
|US6531740||Jul 17, 2001||Mar 11, 2003||Motorola, Inc.||Integrated impedance matching and stability network|
|US6621392||Apr 25, 2002||Sep 16, 2003||International Business Machines Corporation||Micro electromechanical switch having self-aligned spacers|
|US6635506||Nov 7, 2001||Oct 21, 2003||International Business Machines Corporation||Method of fabricating micro-electromechanical switches on CMOS compatible substrates|
|US6787827||Apr 26, 2002||Sep 7, 2004||Kabushiki Kaisha Toshiba||Semiconductor device and method for manufacturing the same|
|US6825529||Dec 12, 2002||Nov 30, 2004||International Business Machines Corporation||Stress inducing spacers|
|US6831292||Sep 20, 2002||Dec 14, 2004||Amberwave Systems Corporation||Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same|
|US6974981||Dec 12, 2002||Dec 13, 2005||International Business Machines Corporation||Isolation structures for imposing stress patterns|
|US6977194||Oct 30, 2003||Dec 20, 2005||International Business Machines Corporation||Structure and method to improve channel mobility by gate electrode stress modification|
|US7015082||Nov 6, 2003||Mar 21, 2006||International Business Machines Corporation||High mobility CMOS circuits|
|US20010009784||Feb 14, 2001||Jul 26, 2001||Yanjun Ma||Preparing substrate, isolating active region, depositing gate oxide, depositing first and second selective etchable layers over gate oxide layer, etching to undercut first etchable layer, implanting ions, etching, depositing oxide, metallizing|
|US20010039107 *||Jun 11, 2001||Nov 8, 2001||Kabushiki Kaisha Toshiba||Semiconductor device and method of manufacture thereof|
|US20020063292||Nov 29, 2000||May 30, 2002||Mark Armstrong||CMOS fabrication process utilizing special transistor orientation|
|US20020074598||Nov 9, 2001||Jun 20, 2002||Doyle Brian S.||Methodology for control of short channel effects in MOS transistors|
|US20020086472||Dec 29, 2000||Jul 4, 2002||Brian Roberds||Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel|
|US20020086497||Dec 6, 2001||Jul 4, 2002||Kwok Siang Ping||Beaker shape trench with nitride pull-back for STI|
|US20020090791||Jun 28, 1999||Jul 11, 2002||Brian S. Doyle||Method for reduced capacitance interconnect system using gaseous implants into the ild|
|US20020142566 *||May 23, 2002||Oct 3, 2002||Intel Corporation||Silicon wafers for CMOS and other integrated circuits|
|US20030032261||Aug 8, 2001||Feb 13, 2003||Ling-Yen Yeh||Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation|
|US20030040158||Aug 21, 2002||Feb 27, 2003||Nec Corporation||Semiconductor device and method of fabricating the same|
|US20030057184||Sep 22, 2001||Mar 27, 2003||Shiuh-Sheng Yu||Method for pull back SiN to increase rounding effect in a shallow trench isolation process|
|US20030067035||Sep 28, 2001||Apr 10, 2003||Helmut Tews||Gate processing method with reduced gate oxide corner and edge thinning|
|US20040113174||Dec 12, 2002||Jun 17, 2004||International Business Machines Corporation||Isolation structures for imposing stress patterns|
|US20040113217||Dec 12, 2002||Jun 17, 2004||International Business Machines Corporation||Stress inducing spacers|
|US20040238914||Jan 5, 2004||Dec 2, 2004||International Business Machines Corporation||STI stress modification by nitrogen plasma treatment for improving performance in small width devices|
|US20040262784||Jun 30, 2003||Dec 30, 2004||International Business Machines Corporation||High performance cmos device structures and method of manufacture|
|US20050040460||Sep 7, 2004||Feb 24, 2005||Dureseti Chidambarrao||Stress inducing spacers|
|US20050082634||Oct 16, 2003||Apr 21, 2005||International Business Machines Corporation||High performance strained cmos devices|
|US20050093030||Oct 30, 2003||May 5, 2005||Doris Bruce B.||Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers|
|US20050098829||Nov 6, 2003||May 12, 2005||Doris Bruce B.||High mobility CMOS circuits|
|US20050106799||Nov 14, 2003||May 19, 2005||International Business Machines Corporation||Stressed semiconductor device structures having granular semiconductor material|
|US20050145954||Jan 5, 2004||Jul 7, 2005||International Business Machines Corporation||Structures and methods for making strained mosfets|
|1||A. Shimizu, et al., "Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement", International Electron Devices Meeting, IEEE, Mar. 2001.|
|2||B. Doyle, G.J. Dunn, "Recovery of Hot-Carrier Damage in Reoxidized Nitrided Oxide MOSFETs". IEEE Electron Device Letters, vol. 13, No. 1, Jan. 1992, pp. 38-40.|
|3||C.J. Huang, C.J. Sun, T.A. Grotjohn, D.K. Reinhard, "Temperature Dependence and Post-Stress Recovery of Hot Electron Degradation Effects in Bipolar Transistors". IEEE 1991 Bipolar Circuits and Technology Meeting 7.5, pp. 170-173.|
|4||F. Ootsuka, et al., "A Highly Dense, High-Performance 130nm node CMOS Technology for Large Scale System-on-a-Chip Application", International Electron Devices Meeting, 23.5.1, IEEE, Apr. 2000.|
|5||G. Zhang, J. Cressler, G. Niu, A. Joseph, "A New 'Mixed-Mode'Reliability Degradation Mechanism in Advanced Si and SiGe Biploar Transistors". IEEE Transactions on Electron Devices, vol. 49, No. 12, Dec. 2002, pp. 2151-2156.|
|6||Gregory Scott, et al., "NMOS Drive Current Reduction Caused by Transitor Layout and Trench Isolation Induced Stress", International Electron Devices Meeting, 34.4.1, IEEE, Sep. 1999.|
|7||H. Li, H.M. Rein, T. Suttorp, "Design of W-Band VCOs with High Output Power for Potential Application In 77 GHz Automotive Radar Systems". 2003 IEEE GaAs Digest, pp. 263-266.|
|8||H. Wurzer, R. Mahakopf, H. Klose, "Annealing of Degraded opn-Transistors-Mechanisms and Modeling". IEEE Transactions on Electron Devices, vol. 41, No. 4, Apr. 1994, pp. 533-538.|
|9||H.S. Momose, H. Iwai, "Analysis of the Temperature Dependence of Hot-Carrier-Induced Degradation in Bipolar Transistors for B1-CMOS". IEEE Transactions on Electron Devices, vol. 41, No. 6, Jun. 1994, pp. 978-987.|
|10||H.S. Momose, Y. Niitsu, H. Iwai, K. Maeguchi, "Temperature Dependence of Emitter-Base Reverse Stress Degradation and its Mechanism Analyzed by MOS Structures". Paper 6.2, pp. 140-143.|
|11||International Search Report and Written Opinion, International Appl. No. PCT/US2004/037434, International Filing Date Nov. 9, 2004.|
|12||K. Ota, et al. "Novel Locally Strained Channel Technique for high Performance 55nm CMOS", International Electron Devices Meeting, 2.2.1, IEEE, Feb. 2002.|
|13||Kem Rim et al., "Characteristics and Device Design of Sub-100 nm Strained Si N- and PMOSFETs", 2002 Symposium On VLSI Technology Digest of Technical Papers, IEEE, pp. 98-99.|
|14||Kem Rim, et al., "Transconductance Enhancement in Deep Submicron Strained-Si n-MOSFETs", International Electron Devices Meeting, 26, 8, 1, IEEE, Sep. 1998.|
|15||S.R. Sheng, S.P. McAllister, J.P. McCaffrey, S. Kovacle, "Degradation and Recovery of SIGe HBTs Following Radation and Hot-Carrier Stressing". pp. 14-15.|
|16||Shinya Ito, et al., "Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design", International Electron Devices Meeting, 10.7.1, IEEE, Apr. 2000.|
|17||Z. Yang, P. Gaurin, E. Hostetter, G. Freeman, "Avalanche Current Induced Hot Carrier Degradation in 200GHz SIGe Heterojunction Bipolar Transistors". pp. 1-5.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7355256 *||Apr 11, 2006||Apr 8, 2008||Nec Electronics Corporation||MOS Devices with different gate lengths and different gate polysilicon grain sizes|
|US7560341 *||Jan 18, 2007||Jul 14, 2009||Sony Corporation||Semiconductor device and manufacturing method therefor|
| || |
|U.S. Classification||257/288, 257/E29.063, 257/408, 257/E21.197, 257/E21.193, 257/E29.155, 257/E21.324, 257/E21.637, 257/E21.444, 257/E21.336, 257/E21.633, 257/410|
|International Classification||H01L31/119, H01L31/062, H01L29/76, H01L29/94, H01L31/113, H01L21/8238|
|Cooperative Classification||H01L21/823842, H01L21/28247, H01L29/665, H01L29/517, H01L29/66545, H01L21/28167, H01L21/823807, H01L21/28035, H01L29/6659, H01L21/324, H01L21/26513, H01L29/4925, H01L29/1083, H01L29/7845|
|European Classification||H01L29/66M6T6F11B3, H01L29/66M6T6F8, H01L29/78R3, H01L21/8238C, H01L21/28E2P, H01L21/324, H01L29/49C2, H01L21/28E2B2, H01L21/8238G4|
|Dec 7, 2010||FP||Expired due to failure to pay maintenance fee|
Effective date: 20101017
|Oct 17, 2010||LAPS||Lapse for failure to pay maintenance fees|
|May 24, 2010||REMI||Maintenance fee reminder mailed|
|Nov 14, 2003||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DORIS, BRUCE B;BELYANSKY, MICHAEL P;BOYD, DIANE C;AND OTHERS;REEL/FRAME:014127/0340;SIGNING DATES FROM 20031107 TO 20031113