ONLY DO part 4!!Image text transcribed for accessibility: A k-bit Carry-Lookahead Circuit (k-bit CLA) relates the output carry Ci + k to input carry ci using the block generate (Gi) and block propagate (Pi) signals: ci + k = Gi + Pici. In class we used the example of k = 4. Assume k = 4. Write down the relation between C7 and C3. The inputs are the signals gj and pj, 4 le j le 7. Rearrange the equations as necessary to design a fast circuit to compute Gi and Pi for each block, using 4-input AND and OR gates only. Show the gate design. You need only show it for G3 and P3 for the assignment. Note that the design in class required 6 gate delays for computing Gi and 2 gate delays for Pi, using 2-input gates. Assuming the gates have a delay of 100 ps what is the delay tpG-Block for your 4-bit CLA design. Repeat part (a) for the case k = 8. You only need to show the equation and logic circuit for G7 and P7. Its inputs are gj, Pj, 8s le j le 15. Note, the AND and OR gates are still 4-input gates. A 32-bit Carry Lookahead Adder is to be built using 4-bit CLA's of Question 2. The CLAs are chained together to determine the c3, c7, etc., by serially propagating the carries using the Gi, Pi blocks. The sums within each block are then computed with 4-bit Ripple Carry Adders. (This is the same design as done in class and in the textbook). Use the 4-bit CLA designs of Q2(a). Find the time required to do the complete the addition. Assume that a k-bit Ripple-Carry Adder requires (100 + 50k) ps. Repeat Question 3 for k = 8 using the 8-bit CLA designs of part 2(b).