Arthur Cole spoke with Joseph Ashwood, inventor of the Ashwood Architecture.
Cole: Your new memory architecture is being described as a multicore memory system. What can you tell us about it?
Ashwood: While I can't give details about the internal design without an NDA, by saying this is "multicore memory," I mean that on a given clock-edge, several hundred instructions could begin simultaneously. That is why I say the Ashwood Architecture uniquely provides concurrency. This is directly comparable to the multiple cores in CPUs, each being able to begin processing instructions in each of their cores simultaneously. It is simply a convenient short-hand for the clock-edge concurrency.
Cole: Reports say that it shares some features with Fibre Channel. Can you explain what those features might be, and does this mean it won't be compatible with Ethernet or iSCSI systems?
Ashwood: The Ashwood Architecture is very compatible with those and can also be easily used with SATA, PATA, SAS, SCSI, Ethernet, Fibre over Ethernet, etc.-even USB thumbdrives could make use of it. The only reason I singled out Fibre Channel is because of the deep Command Queueing. The deep queueing allows for maximum concurrency to be achieved more often, delivering a more consistent data throughput.
This brings me to your earlier concern regarding "whether the overhead needed for parallel access will slow performance more than the parallelism will enhance it." Actually, the Ashwood Architecture will increase performance significantly. The protocol overhead is already built into the current data connections. The major component in this increased performance is the concurrency (Command Queueing) involved. This concurrency allows instructions to be performed simultaneously, lowering the effective access time by a larger factor compared to current Flash, delivering far greater performance.
Cole: What sort of real-world applications do you see the system fulfilling, and how soon before there is a working prototype?
Ashwood: The features of the Ashwood Architecture (GBs per second, TB in less than a cubic inch, scalability, concurrency, etc.) allow for improvement in virtually all applications from data farms to cell phones. A working prototype can be done within three months with a semiconductor company.