This is our third installment in the look at the impact that jitter will have on emerging 5- to 6.25-Gbit XAUI backplane designs. In Part 1, we examined how designers can analyze backplanes in the time and frequency domains. In Part 2, we looked at the impact of deterministic jitter and receive-end equalization on designs. Now, we'll provide a set of practical test platforms for evaluating next-generation platforms.
It's important to note that in this article real channels were used in conjunction with an active receive equalization device to examine the impact of various passive characteristics on the performance of the channel/equalizer combination. S-parameter measurements of the channels under consideration will be presented to provide a qualitative understanding of channel variance. Quantitative analysis using tools that accurately predict channel performance out to a bit error rate (BER) of 10-12 were also performed on channels running at 5 Gbit/s.
Passive, Active Interactions
To better understand the interactions between passive and active components, we've set up test platforms that present various channels to an equalizer and analyzes the jitter content at its output. The basic set-up is shown in Figure 13. Three different test platforms were used that consisted of various materials, trace conditions, layer connections, and board thicknesses.
Figure 13: Measurement setup.
For the purpose of this paper two basic platforms were chosen. A Material variation of one platform was also used in order to include the effect of material changes.
Platforms 1 and 2 were set up to show interoperability between the XAUI and HM-Zd backplanes. These are the same, with the Platform 1 backplane being composed of Nelco 4000-2, and the Platform 2 backplane being composed of Nelco 4000-6. A conceptual diagram of these platforms is shown in Figure 14.
Figure 14: XAUI HM-Zd interoperability platform.
The platform shown in Figure 14 consists of two line cards that provide SMA access and the Z-PACK HM Zd based backplane. Each line card is 0.093-in. (nominal) thick and consists of 14 layers. Note: platform 1 is fabricated using Nelco 4000-2 material.
There are four signal layers distributed throughout the entire stackup where the 100-ohm differential geometries are based on 0.006-in. (nominal) wide traces. The trace length from the SMA to the Z-PACK HM-Zd connector is 2 in.
The backplane is 0.200-in. (nominal) thick, consists of 14 layers, and is also fabricated using 4000-2 material. There are four signal layers distributed throughout the entire stackup where the 100-ohm differential geometries are based on 0.010-in. (nominal) wide traces. On the backplane there are three sets of trace lengths: 1, 16, and 30 in. Thus, for the platform, there are overall system lengths of 5, 20, and 34 in. To examine the impact of better materials for the backplane on overall performance, Tyco Electronics fabricated the backplane only in Nelco 4000-6 (in Platform 2).
Platform 3 is a quad route design technique based on the Z-PACK HM-Zd connector. This connector, which has 2.5-mm spacing between signal columns and two differential pairs based on 4.5-mil wide traces, can be routed between the signal columns with enough isolation to minimize crosstalk between the two pair. The use of the quad route technique reduces signal layer count by half, which can economically justify the use of higher performance materials to reduce the predictable losses associated with dielectric losses. Furthermore, this routing density can help minimize overall board thickness, which helps minimize connector footprint noise and the associated unpredictable losses caused by the connector/PWB interface. This results in predictable behavior for all signal layers throughout the entire backplane.
The HM-Zd quad route backplane is 0.125-in. thick and includes 20 layers, eight of which are reserved for signaling. The routing density that is enabled by the quad route technique gives this backplane the same capacity as a backplane that has 16 signal layers, which would be 0.250-in. thick. As discussed in detail, the associated stub capacitance of such a backplane thickness will drive performance variability across the stackup of the backplane. The minimal stub capacitance of the 0.125-in. thick backplane results in minimal performance variability.
Figure 15 illustrates the performance of the layer extremes of all three platforms for the 30-inch link. For platform 3, there is minimal difference between the two layer extremes, as compared to the other two platforms. Reduced channel ripple is also evident for the quad route backplane. Furthermore, the quad route backplane doesn't go below -30 dB for the top-layer connection all the way up to 6 GHz, which neither of the two XAUI backplanes achieved.
Figure 15: Figure 15: SDD21 data for layer extremes for all platforms.
Three different patterns were chosen for backplane testing PRBS 27-1, 210-1, and CJTPATto cover a wide range of traffic characteristics. The basic test setup is shown in Figure 13. Measurements were taken at 5-Gbit/s over a 30-inch link (+2x2 inch on line cards) on all three boards, going through the stack-up from top layer to bottom layer. The test equipment was used to obtain the total jitter out to a bit error rate (BER) of 10-12 to give more quantitive results than eye diagrams.
Crosstalk impacts were briefly investigated on one link at 5Gbit/s. Measurements were taken over the 30-inch link on Platform 1. The victim signal was input to IN_C1, and the aggressor signal was input to OUT_C1 on the receiving daughter card to achieve the more damaging NEXT. The selected pins neighbor each other in adjacent signal columns and are representative of typical pinout conditions in a system environment. The aggressor signal had the same data rate as the desired signal, and was set at 4 times the desired signal to emulate the effect of multiple aggressors.
The total jitter out of the pattern generator for the three data patterns used is given in Table 1.
The additive jitter is defined as the total jitter at a BER of 10-12 at the output of the equalizer minus the BER at 10-12 out of the pattern generator. Data recovery was not performed on the data since this will hide the margin available to the data recovery unit. Figures 16 to 18 show the additive jitter at for a 30-in. backplane link for each of the three platforms.
Figure 16: Additive jitter after equalizer for 30-in. link over platform 1.
Figure 17: Additive jitter after equalizer for 30-in. link over platform 2.
Figure 18: Additive jitter after equalizer for 30-in. link over platform 3.
As mentioned previously, crosstalk results were taken. The difference in total jitter was less than 0.01UI, and is well within the measurement repeatability.
Discussion of Results
The maximum additive jitter out of all the measurements was just over 0.14UI. Clearly, with the XAUI transmit jitter allowance of 0.35UI, transmission over these channels at 5 Gbit/s using receive end analog equalization methods is easily doable, even considering crosstalk. The layer effect appears to be minimal at this data rate with actually some unexpectedly low additive jitters on the top layer of the XAUI 4000-6 and quad route boards for the PRBS patterns. The CJTPAT pattern is relatively insensitive to layering. These anomalies may be a chance combination of data pattern affect on the adaptation algorithm, plus channel and equalizer frequency responses that match extremely well.
Another trend to note is that the additive jitters for the quad route board average about 0.03UI less than the other two boards, despite having a higher attenuation. The increase in jitter due to crosstalk at this data rate is negligible. Figure 9 from Part 2 shows a crosstalk margin (S21 of desired signal minus S21 of crosstalk signal) of around 30 B at the 2.5GHz half data rate frequency. With aggressor levels of 4X the desired signal, or 12 dB, the margin for this case is closer to 20 dB. This measurement illustrates that crosstalk margins much less than 20 dB (including all crosstalk degradations) are supportable.
That finishes our discussion on the impact on source jitter on emerging 5- to 6.25-Gbit/s XAUI backplane designs. To view Part 1 of this series, click here. To view Part 2, click here.
Editor's Note: A previous version of this article was presented at DesignCon 2003. It has been republished with permission of the IEC (www.iec.org).
About the Authors
Ken Lazaris-Brunner is a product definition specialist with Gennum Corporation. He holds a B.Sc. (Honors, Physics) degree from Queen's University (Kingston, Canada) and a M.Eng from McMaster University (Hamilton, Ontario). Ken can be reached at firstname.lastname@example.org.
John D'Ambrosia is the manager of semiconductor relations for Tyco Electronics. He received a B.S. in Electrical Engineering Technology from the Pennsylvania State University and a Master's Degree in Engineering Management from the National Technology University. John can be reached at email@example.com
John Patrin is currently the director of product marketing at Wavecrest. He received a BS in physics from St. John's University in Collegeville, MN and a Ph.D. in Materials Science from the University of Minnesota in Minneapolis. John can be reached at firstname.lastname@example.org.
Craig Emmerich is currently product marketing engineer at Wavecrest. He received a BS in Electrical Engineering from the University of Minnesota in Minneapolis. Craig can be reached at email@example.com.