A new organization for a perceptron-based branch predictor and its FPGA implementation
Cadenas , O., Megson, G. and Jones, D. (2005) A new organization for a perceptron-based branch predictor and its FPGA implementation. In: Smailagic, A. and Ranganathan, N. (eds.) IEEE Computer Society Annual Symposium on VLSI, Proceedings - NEW FRONTIERS IN VLSI DESIGN. IEEE Computer Soc, Los Alamitos, pp. 305-306. ISBN 076952365X
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An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget.