/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2018 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef GOYA_BLOCKS_H_
#define GOYA_BLOCKS_H_

#define mmPCI_NRTR_BASE                            0x7FFC000000ull
#define PCI_NRTR_MAX_OFFSET                        0x608
#define PCI_NRTR_SECTION                           0x4000
#define mmPCI_RD_REGULATOR_BASE                    0x7FFC004000ull
#define PCI_RD_REGULATOR_MAX_OFFSET                0x74
#define PCI_RD_REGULATOR_SECTION                   0x1000
#define mmPCI_WR_REGULATOR_BASE                    0x7FFC005000ull
#define PCI_WR_REGULATOR_MAX_OFFSET                0x74
#define PCI_WR_REGULATOR_SECTION                   0x3B000
#define mmMME1_RTR_BASE                            0x7FFC040000ull
#define MME1_RTR_MAX_OFFSET                        0x608
#define MME1_RTR_SECTION                           0x4000
#define mmMME1_RD_REGULATOR_BASE                   0x7FFC044000ull
#define MME1_RD_REGULATOR_MAX_OFFSET               0x74
#define MME1_RD_REGULATOR_SECTION                  0x1000
#define mmMME1_WR_REGULATOR_BASE                   0x7FFC045000ull
#define MME1_WR_REGULATOR_MAX_OFFSET               0x74
#define MME1_WR_REGULATOR_SECTION                  0x3B000
#define mmMME2_RTR_BASE                            0x7FFC080000ull
#define MME2_RTR_MAX_OFFSET                        0x608
#define MME2_RTR_SECTION                           0x4000
#define mmMME2_RD_REGULATOR_BASE                   0x7FFC084000ull
#define MME2_RD_REGULATOR_MAX_OFFSET               0x74
#define MME2_RD_REGULATOR_SECTION                  0x1000
#define mmMME2_WR_REGULATOR_BASE                   0x7FFC085000ull
#define MME2_WR_REGULATOR_MAX_OFFSET               0x74
#define MME2_WR_REGULATOR_SECTION                  0x3B000
#define mmMME3_RTR_BASE                            0x7FFC0C0000ull
#define MME3_RTR_MAX_OFFSET                        0x608
#define MME3_RTR_SECTION                           0x4000
#define mmMME3_RD_REGULATOR_BASE                   0x7FFC0C4000ull
#define MME3_RD_REGULATOR_MAX_OFFSET               0x74
#define MME3_RD_REGULATOR_SECTION                  0x1000
#define mmMME3_WR_REGULATOR_BASE                   0x7FFC0C5000ull
#define MME3_WR_REGULATOR_MAX_OFFSET               0x74
#define MME3_WR_REGULATOR_SECTION                  0xB000
#define mmMME_BASE                                 0x7FFC0D0000ull
#define MME_MAX_OFFSET                             0xBB0
#define MME_SECTION                                0x8000
#define mmMME_QM_BASE                              0x7FFC0D8000ull
#define MME_QM_MAX_OFFSET                          0x310
#define MME_QM_SECTION                             0x1000
#define mmMME_CMDQ_BASE                            0x7FFC0D9000ull
#define MME_CMDQ_MAX_OFFSET                        0x310
#define MME_CMDQ_SECTION                           0x1000
#define mmACC_MS_ECC_MEM_0_BASE                    0x7FFC0DA000ull
#define ACC_MS_ECC_MEM_0_MAX_OFFSET                0x0
#define ACC_MS_ECC_MEM_0_SECTION                   0x1000
#define mmACC_MS_ECC_MEM_1_BASE                    0x7FFC0DB000ull
#define ACC_MS_ECC_MEM_1_MAX_OFFSET                0x0
#define ACC_MS_ECC_MEM_1_SECTION                   0x1000
#define mmACC_MS_ECC_MEM_2_BASE                    0x7FFC0DC000ull
#define ACC_MS_ECC_MEM_2_MAX_OFFSET                0x0
#define ACC_MS_ECC_MEM_2_SECTION                   0x1000
#define mmACC_MS_ECC_MEM_3_BASE                    0x7FFC0DD000ull
#define ACC_MS_ECC_MEM_3_MAX_OFFSET                0x0
#define ACC_MS_ECC_MEM_3_SECTION                   0x1000
#define mmSBA_ECC_MEM_BASE                         0x7FFC0DE000ull
#define SBA_ECC_MEM_MAX_OFFSET                     0x0
#define SBA_ECC_MEM_SECTION                        0x1000
#define mmSBB_ECC_MEM_BASE                         0x7FFC0DF000ull
#define SBB_ECC_MEM_MAX_OFFSET                     0x0
#define SBB_ECC_MEM_SECTION                        0x21000
#define mmMME4_RTR_BASE                            0x7FFC100000ull
#define MME4_RTR_MAX_OFFSET                        0x608
#define MME4_RTR_SECTION                           0x4000
#define mmMME4_RD_REGULATOR_BASE                   0x7FFC104000ull
#define MME4_RD_REGULATOR_MAX_OFFSET               0x74
#define MME4_RD_REGULATOR_SECTION                  0x1000
#define mmMME4_WR_REGULATOR_BASE                   0x7FFC105000ull
#define MME4_WR_REGULATOR_MAX_OFFSET               0x74
#define MME4_WR_REGULATOR_SECTION                  0xB000
#define mmSYNC_MNGR_BASE                           0x7FFC110000ull
#define SYNC_MNGR_MAX_OFFSET                       0x4400
#define SYNC_MNGR_SECTION                          0x30000
#define mmMME5_RTR_BASE                            0x7FFC140000ull
#define MME5_RTR_MAX_OFFSET                        0x608
#define MME5_RTR_SECTION                           0x4000
#define mmMME5_RD_REGULATOR_BASE                   0x7FFC144000ull
#define MME5_RD_REGULATOR_MAX_OFFSET               0x74
#define MME5_RD_REGULATOR_SECTION                  0x1000
#define mmMME5_WR_REGULATOR_BASE                   0x7FFC145000ull
#define MME5_WR_REGULATOR_MAX_OFFSET               0x74
#define MME5_WR_REGULATOR_SECTION                  0x3B000
#define mmMME6_RTR_BASE                            0x7FFC180000ull
#define MME6_RTR_MAX_OFFSET                        0x608
#define MME6_RTR_SECTION                           0x4000
#define mmMME6_RD_REGULATOR_BASE                   0x7FFC184000ull
#define MME6_RD_REGULATOR_MAX_OFFSET               0x74
#define MME6_RD_REGULATOR_SECTION                  0x1000
#define mmMME6_WR_REGULATOR_BASE                   0x7FFC185000ull
#define MME6_WR_REGULATOR_MAX_OFFSET               0x74
#define MME6_WR_REGULATOR_SECTION                  0x3B000
#define mmDMA_NRTR_BASE                            0x7FFC1C0000ull
#define DMA_NRTR_MAX_OFFSET                        0x608
#define DMA_NRTR_SECTION                           0x4000
#define mmDMA_RD_REGULATOR_BASE                    0x7FFC1C4000ull
#define DMA_RD_REGULATOR_MAX_OFFSET                0x74
#define DMA_RD_REGULATOR_SECTION                   0x1000
#define mmDMA_WR_REGULATOR_BASE                    0x7FFC1C5000ull
#define DMA_WR_REGULATOR_MAX_OFFSET                0x74
#define DMA_WR_REGULATOR_SECTION                   0x3B000
#define mmSRAM_Y0_X0_BANK_BASE                     0x7FFC200000ull
#define SRAM_Y0_X0_BANK_MAX_OFFSET                 0x4
#define SRAM_Y0_X0_BANK_SECTION                    0x1000
#define mmSRAM_Y0_X0_RTR_BASE                      0x7FFC201000ull
#define SRAM_Y0_X0_RTR_MAX_OFFSET                  0x334
#define SRAM_Y0_X0_RTR_SECTION                     0x3000
#define mmSRAM_Y0_X1_BANK_BASE                     0x7FFC204000ull
#define SRAM_Y0_X1_BANK_MAX_OFFSET                 0x4
#define SRAM_Y0_X1_BANK_SECTION                    0x1000
#define mmSRAM_Y0_X1_RTR_BASE                      0x7FFC205000ull
#define SRAM_Y0_X1_RTR_MAX_OFFSET                  0x334
#define SRAM_Y0_X1_RTR_SECTION                     0x3000
#define mmSRAM_Y0_X2_BANK_BASE                     0x7FFC208000ull
#define SRAM_Y0_X2_BANK_MAX_OFFSET                 0x4
#define SRAM_Y0_X2_BANK_SECTION                    0x1000
#define mmSRAM_Y0_X2_RTR_BASE                      0x7FFC209000ull
#define SRAM_Y0_X2_RTR_MAX_OFFSET                  0x334
#define SRAM_Y0_X2_RTR_SECTION                     0x3000
#define mmSRAM_Y0_X3_BANK_BASE                     0x7FFC20C000ull
#define SRAM_Y0_X3_BANK_MAX_OFFSET                 0x4
#define SRAM_Y0_X3_BANK_SECTION                    0x1000
#define mmSRAM_Y0_X3_RTR_BASE                      0x7FFC20D000ull
#define SRAM_Y0_X3_RTR_MAX_OFFSET                  0x334
#define SRAM_Y0_X3_RTR_SECTION                     0x3000
#define mmSRAM_Y0_X4_BANK_BASE                     0x7FFC210000ull
#define SRAM_Y0_X4_BANK_MAX_OFFSET                 0x4
#define SRAM_Y0_X4_BANK_SECTION                    0x1000
#define mmSRAM_Y0_X4_RTR_BASE                      0x7FFC211000ull
#define SRAM_Y0_X4_RTR_MAX_OFFSET                  0x334
#define SRAM_Y0_X4_RTR_SECTION                     0xF000
#define mmSRAM_Y1_X0_BANK_BASE                     0x7FFC220000ull
#define SRAM_Y1_X0_BANK_MAX_OFFSET                 0x4
#define SRAM_Y1_X0_BANK_SECTION                    0x1000
#define mmSRAM_Y1_X0_RTR_BASE                      0x7FFC221000ull
#define SRAM_Y1_X0_RTR_MAX_OFFSET                  0x334
#define SRAM_Y1_X0_RTR_SECTION                     0x3000
#define mmSRAM_Y1_X1_BANK_BASE                     0x7FFC224000ull
#define SRAM_Y1_X1_BANK_MAX_OFFSET                 0x4
#define SRAM_Y1_X1_BANK_SECTION                    0x1000
#define mmSRAM_Y1_X1_RTR_BASE                      0x7FFC225000ull
#define SRAM_Y1_X1_RTR_MAX_OFFSET                  0x334
#define SRAM_Y1_X1_RTR_SECTION                     0x3000
#define mmSRAM_Y1_X2_BANK_BASE                     0x7FFC228000ull
#define SRAM_Y1_X2_BANK_MAX_OFFSET                 0x4
#define SRAM_Y1_X2_BANK_SECTION                    0x1000
#define mmSRAM_Y1_X2_RTR_BASE                      0x7FFC229000ull
#define SRAM_Y1_X2_RTR_MAX_OFFSET                  0x334
#define SRAM_Y1_X2_RTR_SECTION                     0x3000
#define mmSRAM_Y1_X3_BANK_BASE                     0x7FFC22C000ull
#define SRAM_Y1_X3_BANK_MAX_OFFSET                 0x4
#define SRAM_Y1_X3_BANK_SECTION                    0x1000
#define mmSRAM_Y1_X3_RTR_BASE                      0x7FFC22D000ull
#define SRAM_Y1_X3_RTR_MAX_OFFSET                  0x334
#define SRAM_Y1_X3_RTR_SECTION                     0x3000
#define mmSRAM_Y1_X4_BANK_BASE                     0x7FFC230000ull
#define SRAM_Y1_X4_BANK_MAX_OFFSET                 0x4
#define SRAM_Y1_X4_BANK_SECTION                    0x1000
#define mmSRAM_Y1_X4_RTR_BASE                      0x7FFC231000ull
#define SRAM_Y1_X4_RTR_MAX_OFFSET                  0x334
#define SRAM_Y1_X4_RTR_SECTION                     0xF000
#define mmSRAM_Y2_X0_BANK_BASE                     0x7FFC240000ull
#define SRAM_Y2_X0_BANK_MAX_OFFSET                 0x4
#define SRAM_Y2_X0_BANK_SECTION                    0x1000
#define mmSRAM_Y2_X0_RTR_BASE                      0x7FFC241000ull
#define SRAM_Y2_X0_RTR_MAX_OFFSET                  0x334
#define SRAM_Y2_X0_RTR_SECTION                     0x3000
#define mmSRAM_Y2_X1_BANK_BASE                     0x7FFC244000ull
#define SRAM_Y2_X1_BANK_MAX_OFFSET                 0x4
#define SRAM_Y2_X1_BANK_SECTION                    0x1000
#define mmSRAM_Y2_X1_RTR_BASE                      0x7FFC245000ull
#define SRAM_Y2_X1_RTR_MAX_OFFSET                  0x334
#define SRAM_Y2_X1_RTR_SECTION                     0x3000
#define mmSRAM_Y2_X2_BANK_BASE                     0x7FFC248000ull
#define SRAM_Y2_X2_BANK_MAX_OFFSET                 0x4
#define SRAM_Y2_X2_BANK_SECTION                    0x1000
#define mmSRAM_Y2_X2_RTR_BASE                      0x7FFC249000ull
#define SRAM_Y2_X2_RTR_MAX_OFFSET                  0x334
#define SRAM_Y2_X2_RTR_SECTION                     0x3000
#define mmSRAM_Y2_X3_BANK_BASE                     0x7FFC24C000ull
#define SRAM_Y2_X3_BANK_MAX_OFFSET                 0x4
#define SRAM_Y2_X3_BANK_SECTION                    0x1000
#define mmSRAM_Y2_X3_RTR_BASE                      0x7FFC24D000ull
#define SRAM_Y2_X3_RTR_MAX_OFFSET                  0x334
#define SRAM_Y2_X3_RTR_SECTION                     0x3000
#define mmSRAM_Y2_X4_BANK_BASE                     0x7FFC250000ull
#define SRAM_Y2_X4_BANK_MAX_OFFSET                 0x4
#define SRAM_Y2_X4_BANK_SECTION                    0x1000
#define mmSRAM_Y2_X4_RTR_BASE                      0x7FFC251000ull
#define SRAM_Y2_X4_RTR_MAX_OFFSET                  0x334
#define SRAM_Y2_X4_RTR_SECTION                     0xF000
#define mmSRAM_Y3_X0_BANK_BASE                     0x7FFC260000ull
#define SRAM_Y3_X0_BANK_MAX_OFFSET                 0x4
#define SRAM_Y3_X0_BANK_SECTION                    0x1000
#define mmSRAM_Y3_X0_RTR_BASE                      0x7FFC261000ull
#define SRAM_Y3_X0_RTR_MAX_OFFSET                  0x334
#define SRAM_Y3_X0_RTR_SECTION                     0x3000
#define mmSRAM_Y3_X1_BANK_BASE                     0x7FFC264000ull
#define SRAM_Y3_X1_BANK_MAX_OFFSET                 0x4
#define SRAM_Y3_X1_BANK_SECTION                    0x1000
#define mmSRAM_Y3_X1_RTR_BASE                      0x7FFC265000ull
#define SRAM_Y3_X1_RTR_MAX_OFFSET                  0x334
#define SRAM_Y3_X1_RTR_SECTION                     0x3000
#define mmSRAM_Y3_X2_BANK_BASE                     0x7FFC268000ull
#define SRAM_Y3_X2_BANK_MAX_OFFSET                 0x4
#define SRAM_Y3_X2_BANK_SECTION                    0x1000
#define mmSRAM_Y3_X2_RTR_BASE                      0x7FFC269000ull
#define SRAM_Y3_X2_RTR_MAX_OFFSET                  0x334
#define SRAM_Y3_X2_RTR_SECTION                     0x3000
#define mmSRAM_Y3_X3_BANK_BASE                     0x7FFC26C000ull
#define SRAM_Y3_X3_BANK_MAX_OFFSET                 0x4
#define SRAM_Y3_X3_BANK_SECTION                    0x1000
#define mmSRAM_Y3_X3_RTR_BASE                      0x7FFC26D000ull
#define SRAM_Y3_X3_RTR_MAX_OFFSET                  0x334
#define SRAM_Y3_X3_RTR_SECTION                     0x3000
#define mmSRAM_Y3_X4_BANK_BASE                     0x7FFC270000ull
#define SRAM_Y3_X4_BANK_MAX_OFFSET                 0x4
#define SRAM_Y3_X4_BANK_SECTION                    0x1000
#define mmSRAM_Y3_X4_RTR_BASE                      0x7FFC271000ull
#define SRAM_Y3_X4_RTR_MAX_OFFSET                  0x334
#define SRAM_Y3_X4_RTR_SECTION                     0xF000
#define mmSRAM_Y4_X0_BANK_BASE                     0x7FFC280000ull
#define SRAM_Y4_X0_BANK_MAX_OFFSET                 0x4
#define SRAM_Y4_X0_BANK_SECTION                    0x1000
#define mmSRAM_Y4_X0_RTR_BASE                      0x7FFC281000ull
#define SRAM_Y4_X0_RTR_MAX_OFFSET                  0x334
#define SRAM_Y4_X0_RTR_SECTION                     0x3000
#define mmSRAM_Y4_X1_BANK_BASE                     0x7FFC284000ull
#define SRAM_Y4_X1_BANK_MAX_OFFSET                 0x4
#define SRAM_Y4_X1_BANK_SECTION                    0x1000
#define mmSRAM_Y4_X1_RTR_BASE                      0x7FFC285000ull
#define SRAM_Y4_X1_RTR_MAX_OFFSET                  0x334
#define SRAM_Y4_X1_RTR_SECTION                     0x3000
#define mmSRAM_Y4_X2_BANK_BASE                     0x7FFC288000ull
#define SRAM_Y4_X2_BANK_MAX_OFFSET                 0x4
#define SRAM_Y4_X2_BANK_SECTION                    0x1000
#define mmSRAM_Y4_X2_RTR_BASE                      0x7FFC289000ull
#define SRAM_Y4_X2_RTR_MAX_OFFSET                  0x334
#define SRAM_Y4_X2_RTR_SECTION                     0x3000
#define mmSRAM_Y4_X3_BANK_BASE                     0x7FFC28C000ull
#define SRAM_Y4_X3_BANK_MAX_OFFSET                 0x4
#define SRAM_Y4_X3_BANK_SECTION                    0x1000
#define mmSRAM_Y4_X3_RTR_BASE                      0x7FFC28D000ull
#define SRAM_Y4_X3_RTR_MAX_OFFSET                  0x334
#define SRAM_Y4_X3_RTR_SECTION                     0x3000
#define mmSRAM_Y4_X4_BANK_BASE                     0x7FFC290000ull
#define SRAM_Y4_X4_BANK_MAX_OFFSET                 0x4
#define SRAM_Y4_X4_BANK_SECTION                    0x1000
#define mmSRAM_Y4_X4_RTR_BASE                      0x7FFC291000ull
#define SRAM_Y4_X4_RTR_MAX_OFFSET                  0x334
#define SRAM_Y4_X4_RTR_SECTION                     0xF000
#define mmSRAM_Y5_X0_BANK_BASE                     0x7FFC2A0000ull
#define SRAM_Y5_X0_BANK_MAX_OFFSET                 0x4
#define SRAM_Y5_X0_BANK_SECTION                    0x1000
#define mmSRAM_Y5_X0_RTR_BASE                      0x7FFC2A1000ull
#define SRAM_Y5_X0_RTR_MAX_OFFSET                  0x334
#define SRAM_Y5_X0_RTR_SECTION                     0x3000
#define mmSRAM_Y5_X1_BANK_BASE                     0x7FFC2A4000ull
#define SRAM_Y5_X1_BANK_MAX_OFFSET                 0x4
#define SRAM_Y5_X1_BANK_SECTION                    0x1000
#define mmSRAM_Y5_X1_RTR_BASE                      0x7FFC2A5000ull
#define SRAM_Y5_X1_RTR_MAX_OFFSET                  0x334
#define SRAM_Y5_X1_RTR_SECTION                     0x3000
#define mmSRAM_Y5_X2_BANK_BASE                     0x7FFC2A8000ull
#define SRAM_Y5_X2_BANK_MAX_OFFSET                 0x4
#define SRAM_Y5_X2_BANK_SECTION                    0x1000
#define mmSRAM_Y5_X2_RTR_BASE                      0x7FFC2A9000ull
#define SRAM_Y5_X2_RTR_MAX_OFFSET                  0x334
#define SRAM_Y5_X2_RTR_SECTION                     0x3000
#define mmSRAM_Y5_X3_BANK_BASE                     0x7FFC2AC000ull
#define SRAM_Y5_X3_BANK_MAX_OFFSET                 0x4
#define SRAM_Y5_X3_BANK_SECTION                    0x1000
#define mmSRAM_Y5_X3_RTR_BASE                      0x7FFC2AD000ull
#define SRAM_Y5_X3_RTR_MAX_OFFSET                  0x334
#define SRAM_Y5_X3_RTR_SECTION                     0x3000
#define mmSRAM_Y5_X4_BANK_BASE                     0x7FFC2B0000ull
#define SRAM_Y5_X4_BANK_MAX_OFFSET                 0x4
#define SRAM_Y5_X4_BANK_SECTION                    0x1000
#define mmSRAM_Y5_X4_RTR_BASE                      0x7FFC2B1000ull
#define SRAM_Y5_X4_RTR_MAX_OFFSET                  0x334
#define SRAM_Y5_X4_RTR_SECTION                     0x14F000
#define mmDMA_QM_0_BASE                            0x7FFC400000ull
#define DMA_QM_0_MAX_OFFSET                        0x310
#define DMA_QM_0_SECTION                           0x1000
#define mmDMA_CH_0_BASE                            0x7FFC401000ull
#define DMA_CH_0_MAX_OFFSET                        0x200
#define DMA_CH_0_SECTION                           0x7000
#define mmDMA_QM_1_BASE                            0x7FFC408000ull
#define DMA_QM_1_MAX_OFFSET                        0x310
#define DMA_QM_1_SECTION                           0x1000
#define mmDMA_CH_1_BASE                            0x7FFC409000ull
#define DMA_CH_1_MAX_OFFSET                        0x200
#define DMA_CH_1_SECTION                           0x7000
#define mmDMA_QM_2_BASE                            0x7FFC410000ull
#define DMA_QM_2_MAX_OFFSET                        0x310
#define DMA_QM_2_SECTION                           0x1000
#define mmDMA_CH_2_BASE                            0x7FFC411000ull
#define DMA_CH_2_MAX_OFFSET                        0x200
#define DMA_CH_2_SECTION                           0x7000
#define mmDMA_QM_3_BASE                            0x7FFC418000ull
#define DMA_QM_3_MAX_OFFSET                        0x310
#define DMA_QM_3_SECTION                           0x1000
#define mmDMA_CH_3_BASE                            0x7FFC419000ull
#define DMA_CH_3_MAX_OFFSET                        0x200
#define DMA_CH_3_SECTION                           0x7000
#define mmDMA_QM_4_BASE                            0x7FFC420000ull
#define DMA_QM_4_MAX_OFFSET                        0x310
#define DMA_QM_4_SECTION                           0x1000
#define mmDMA_CH_4_BASE                            0x7FFC421000ull
#define DMA_CH_4_MAX_OFFSET                        0x200
#define DMA_CH_4_SECTION                           0x20000
#define mmCPU_CA53_CFG_BASE                        0x7FFC441000ull
#define CPU_CA53_CFG_MAX_OFFSET                    0x218
#define CPU_CA53_CFG_SECTION                       0x1000
#define mmCPU_IF_BASE                              0x7FFC442000ull
#define CPU_IF_MAX_OFFSET                          0x134
#define CPU_IF_SECTION                             0x2000
#define mmCPU_TIMESTAMP_BASE                       0x7FFC444000ull
#define CPU_TIMESTAMP_MAX_OFFSET                   0x1000
#define CPU_TIMESTAMP_SECTION                      0x3C000
#define mmMMU_BASE                                 0x7FFC480000ull
#define MMU_MAX_OFFSET                             0x44
#define MMU_SECTION                                0x10000
#define mmSTLB_BASE                                0x7FFC490000ull
#define STLB_MAX_OFFSET                            0x50
#define STLB_SECTION                               0x10000
#define mmNORTH_THERMAL_SENSOR_BASE                0x7FFC4A0000ull
#define NORTH_THERMAL_SENSOR_MAX_OFFSET            0xE64
#define NORTH_THERMAL_SENSOR_SECTION               0x1000
#define mmMC_PLL_BASE                              0x7FFC4A1000ull
#define MC_PLL_MAX_OFFSET                          0x444
#define MC_PLL_SECTION                             0x1000
#define mmCPU_PLL_BASE                             0x7FFC4A2000ull
#define CPU_PLL_MAX_OFFSET                         0x444
#define CPU_PLL_SECTION                            0x1000
#define mmIC_PLL_BASE                              0x7FFC4A3000ull
#define IC_PLL_MAX_OFFSET                          0x444
#define IC_PLL_SECTION                             0x1000
#define mmDMA_PROCESS_MON_BASE                     0x7FFC4A4000ull
#define DMA_PROCESS_MON_MAX_OFFSET                 0x4
#define DMA_PROCESS_MON_SECTION                    0xC000
#define mmDMA_MACRO_BASE                           0x7FFC4B0000ull
#define DMA_MACRO_MAX_OFFSET                       0x15C
#define DMA_MACRO_SECTION                          0x150000
#define mmDDR_PHY_CH0_BASE                         0x7FFC600000ull
#define DDR_PHY_CH0_MAX_OFFSET                     0x0
#define DDR_PHY_CH0_SECTION                        0x40000
#define mmDDR_MC_CH0_BASE                          0x7FFC640000ull
#define DDR_MC_CH0_MAX_OFFSET                      0xF34
#define DDR_MC_CH0_SECTION                         0x8000
#define mmDDR_MISC_CH0_BASE                        0x7FFC648000ull
#define DDR_MISC_CH0_MAX_OFFSET                    0x204
#define DDR_MISC_CH0_SECTION                       0xB8000
#define mmDDR_PHY_CH1_BASE                         0x7FFC700000ull
#define DDR_PHY_CH1_MAX_OFFSET                     0x0
#define DDR_PHY_CH1_SECTION                        0x40000
#define mmDDR_MC_CH1_BASE                          0x7FFC740000ull
#define DDR_MC_CH1_MAX_OFFSET                      0xF34
#define DDR_MC_CH1_SECTION                         0x8000
#define mmDDR_MISC_CH1_BASE                        0x7FFC748000ull
#define DDR_MISC_CH1_MAX_OFFSET                    0x204
#define DDR_MISC_CH1_SECTION                       0xB8000
#define mmGIC_BASE                                 0x7FFC800000ull
#define GIC_MAX_OFFSET                             0x10000
#define GIC_SECTION                                0x401000
#define mmPCIE_WRAP_BASE                           0x7FFCC01000ull
#define PCIE_WRAP_MAX_OFFSET                       0xDF4
#define PCIE_WRAP_SECTION                          0x1000
#define mmPCIE_DBI_BASE                            0x7FFCC02000ull
#define PCIE_DBI_MAX_OFFSET                        0xC04
#define PCIE_DBI_SECTION                           0x2000
#define mmPCIE_CORE_BASE                           0x7FFCC04000ull
#define PCIE_CORE_MAX_OFFSET                       0x9B8
#define PCIE_CORE_SECTION                          0x1000
#define mmPCIE_DB_CFG_BASE                         0x7FFCC05000ull
#define PCIE_DB_CFG_MAX_OFFSET                     0xE34
#define PCIE_DB_CFG_SECTION                        0x1000
#define mmPCIE_DB_CMD_BASE                         0x7FFCC06000ull
#define PCIE_DB_CMD_MAX_OFFSET                     0x810
#define PCIE_DB_CMD_SECTION                        0x1000
#define mmPCIE_AUX_BASE                            0x7FFCC07000ull
#define PCIE_AUX_MAX_OFFSET                        0x9BC
#define PCIE_AUX_SECTION                           0x1000
#define mmPCIE_DB_RSV_BASE                         0x7FFCC08000ull
#define PCIE_DB_RSV_MAX_OFFSET                     0x800
#define PCIE_DB_RSV_SECTION                        0x8000
#define mmPCIE_PHY_BASE                            0x7FFCC10000ull
#define PCIE_PHY_MAX_OFFSET                        0x924
#define PCIE_PHY_SECTION                           0x30000
#define mmPSOC_I2C_M0_BASE                         0x7FFCC40000ull
#define PSOC_I2C_M0_MAX_OFFSET                     0x100
#define PSOC_I2C_M0_SECTION                        0x1000
#define mmPSOC_I2C_M1_BASE                         0x7FFCC41000ull
#define PSOC_I2C_M1_MAX_OFFSET                     0x100
#define PSOC_I2C_M1_SECTION                        0x1000
#define mmPSOC_I2C_S_BASE                          0x7FFCC42000ull
#define PSOC_I2C_S_MAX_OFFSET                      0x100
#define PSOC_I2C_S_SECTION                         0x1000
#define mmPSOC_SPI_BASE                            0x7FFCC43000ull
#define PSOC_SPI_MAX_OFFSET                        0x100
#define PSOC_SPI_SECTION                           0x1000
#define mmPSOC_EMMC_BASE                           0x7FFCC44000ull
#define PSOC_EMMC_MAX_OFFSET                       0xF70
#define PSOC_EMMC_SECTION                          0x1000
#define mmPSOC_UART_0_BASE                         0x7FFCC45000ull
#define PSOC_UART_0_MAX_OFFSET                     0x1000
#define PSOC_UART_0_SECTION                        0x1000
#define mmPSOC_UART_1_BASE                         0x7FFCC46000ull
#define PSOC_UART_1_MAX_OFFSET                     0x1000
#define PSOC_UART_1_SECTION                        0x1000
#define mmPSOC_TIMER_BASE                          0x7FFCC47000ull
#define PSOC_TIMER_MAX_OFFSET                      0x1000
#define PSOC_TIMER_SECTION                         0x1000
#define mmPSOC_WDOG_BASE                           0x7FFCC48000ull
#define PSOC_WDOG_MAX_OFFSET                       0x1000
#define PSOC_WDOG_SECTION                          0x1000
#define mmPSOC_TIMESTAMP_BASE                      0x7FFCC49000ull
#define PSOC_TIMESTAMP_MAX_OFFSET                  0x1000
#define PSOC_TIMESTAMP_SECTION                     0x1000
#define mmPSOC_EFUSE_BASE                          0x7FFCC4A000ull
#define PSOC_EFUSE_MAX_OFFSET                      0x10C
#define PSOC_EFUSE_SECTION                         0x1000
#define mmPSOC_GLOBAL_CONF_BASE                    0x7FFCC4B000ull
#define PSOC_GLOBAL_CONF_MAX_OFFSET                0xA48
#define PSOC_GLOBAL_CONF_SECTION                   0x1000
#define mmPSOC_GPIO0_BASE                          0x7FFCC4C000ull
#define PSOC_GPIO0_MAX_OFFSET                      0x1000
#define PSOC_GPIO0_SECTION                         0x1000
#define mmPSOC_GPIO1_BASE                          0x7FFCC4D000ull
#define PSOC_GPIO1_MAX_OFFSET                      0x1000
#define PSOC_GPIO1_SECTION                         0x1000
#define mmPSOC_BTL_BASE                            0x7FFCC4E000ull
#define PSOC_BTL_MAX_OFFSET                        0x124
#define PSOC_BTL_SECTION                           0x1000
#define mmPSOC_CS_TRACE_BASE                       0x7FFCC4F000ull
#define PSOC_CS_TRACE_MAX_OFFSET                   0x0
#define PSOC_CS_TRACE_SECTION                      0x1000
#define mmPSOC_GPIO2_BASE                          0x7FFCC50000ull
#define PSOC_GPIO2_MAX_OFFSET                      0x1000
#define PSOC_GPIO2_SECTION                         0x1000
#define mmPSOC_GPIO3_BASE                          0x7FFCC51000ull
#define PSOC_GPIO3_MAX_OFFSET                      0x1000
#define PSOC_GPIO3_SECTION                         0x1000
#define mmPSOC_GPIO4_BASE                          0x7FFCC52000ull
#define PSOC_GPIO4_MAX_OFFSET                      0x1000
#define PSOC_GPIO4_SECTION                         0x1000
#define mmPSOC_DFT_EFUSE_BASE                      0x7FFCC53000ull
#define PSOC_DFT_EFUSE_MAX_OFFSET                  0x10C
#define PSOC_DFT_EFUSE_SECTION                     0x1000
#define mmPSOC_PM_BASE                             0x7FFCC54000ull
#define PSOC_PM_MAX_OFFSET                         0x4
#define PSOC_PM_SECTION                            0x1000
#define mmPSOC_TS_BASE                             0x7FFCC55000ull
#define PSOC_TS_MAX_OFFSET                         0xE64
#define PSOC_TS_SECTION                            0xB000
#define mmPSOC_MII_BASE                            0x7FFCC60000ull
#define PSOC_MII_MAX_OFFSET                        0x105C
#define PSOC_MII_SECTION                           0x10000
#define mmPSOC_EMMC_PLL_BASE                       0x7FFCC70000ull
#define PSOC_EMMC_PLL_MAX_OFFSET                   0x444
#define PSOC_EMMC_PLL_SECTION                      0x1000
#define mmPSOC_MME_PLL_BASE                        0x7FFCC71000ull
#define PSOC_MME_PLL_MAX_OFFSET                    0x444
#define PSOC_MME_PLL_SECTION                       0x1000
#define mmPSOC_PCI_PLL_BASE                        0x7FFCC72000ull
#define PSOC_PCI_PLL_MAX_OFFSET                    0x444
#define PSOC_PCI_PLL_SECTION                       0x6000
#define mmPSOC_PWM0_BASE                           0x7FFCC78000ull
#define PSOC_PWM0_MAX_OFFSET                       0x58
#define PSOC_PWM0_SECTION                          0x1000
#define mmPSOC_PWM1_BASE                           0x7FFCC79000ull
#define PSOC_PWM1_MAX_OFFSET                       0x58
#define PSOC_PWM1_SECTION                          0x1000
#define mmPSOC_PWM2_BASE                           0x7FFCC7A000ull
#define PSOC_PWM2_MAX_OFFSET                       0x58
#define PSOC_PWM2_SECTION                          0x1000
#define mmPSOC_PWM3_BASE                           0x7FFCC7B000ull
#define PSOC_PWM3_MAX_OFFSET                       0x58
#define PSOC_PWM3_SECTION                          0x185000
#define mmTPC0_NRTR_BASE                           0x7FFCE00000ull
#define TPC0_NRTR_MAX_OFFSET                       0x608
#define TPC0_NRTR_SECTION                          0x1000
#define mmTPC_PLL_BASE                             0x7FFCE01000ull
#define TPC_PLL_MAX_OFFSET                         0x444
#define TPC_PLL_SECTION                            0x1000
#define mmTPC_THEMAL_SENSOR_BASE                   0x7FFCE02000ull
#define TPC_THEMAL_SENSOR_MAX_OFFSET               0xE64
#define TPC_THEMAL_SENSOR_SECTION                  0x1000
#define mmTPC_PROCESS_MON_BASE                     0x7FFCE03000ull
#define TPC_PROCESS_MON_MAX_OFFSET                 0x4
#define TPC_PROCESS_MON_SECTION                    0x1000
#define mmTPC0_RD_REGULATOR_BASE                   0x7FFCE04000ull
#define TPC0_RD_REGULATOR_MAX_OFFSET               0x74
#define TPC0_RD_REGULATOR_SECTION                  0x1000
#define mmTPC0_WR_REGULATOR_BASE                   0x7FFCE05000ull
#define TPC0_WR_REGULATOR_MAX_OFFSET               0x74
#define TPC0_WR_REGULATOR_SECTION                  0x1000
#define mmTPC0_CFG_BASE                            0x7FFCE06000ull
#define TPC0_CFG_MAX_OFFSET                        0xE30
#define TPC0_CFG_SECTION                           0x2000
#define mmTPC0_QM_BASE                             0x7FFCE08000ull
#define TPC0_QM_MAX_OFFSET                         0x310
#define TPC0_QM_SECTION                            0x1000
#define mmTPC0_CMDQ_BASE                           0x7FFCE09000ull
#define TPC0_CMDQ_MAX_OFFSET                       0x310
#define TPC0_CMDQ_SECTION                          0x37000
#define mmTPC1_RTR_BASE                            0x7FFCE40000ull
#define TPC1_RTR_MAX_OFFSET                        0x608
#define TPC1_RTR_SECTION                           0x4000
#define mmTPC1_WR_REGULATOR_BASE                   0x7FFCE44000ull
#define TPC1_WR_REGULATOR_MAX_OFFSET               0x74
#define TPC1_WR_REGULATOR_SECTION                  0x1000
#define mmTPC1_RD_REGULATOR_BASE                   0x7FFCE45000ull
#define TPC1_RD_REGULATOR_MAX_OFFSET               0x74
#define TPC1_RD_REGULATOR_SECTION                  0x1000
#define mmTPC1_CFG_BASE                            0x7FFCE46000ull
#define TPC1_CFG_MAX_OFFSET                        0xE30
#define TPC1_CFG_SECTION                           0x2000
#define mmTPC1_QM_BASE                             0x7FFCE48000ull
#define TPC1_QM_MAX_OFFSET                         0x310
#define TPC1_QM_SECTION                            0x1000
#define mmTPC1_CMDQ_BASE                           0x7FFCE49000ull
#define TPC1_CMDQ_MAX_OFFSET                       0x310
#define TPC1_CMDQ_SECTION                          0x37000
#define mmTPC2_RTR_BASE                            0x7FFCE80000ull
#define TPC2_RTR_MAX_OFFSET                        0x608
#define TPC2_RTR_SECTION                           0x4000
#define mmTPC2_RD_REGULATOR_BASE                   0x7FFCE84000ull
#define TPC2_RD_REGULATOR_MAX_OFFSET               0x74
#define TPC2_RD_REGULATOR_SECTION                  0x1000
#define mmTPC2_WR_REGULATOR_BASE                   0x7FFCE85000ull
#define TPC2_WR_REGULATOR_MAX_OFFSET               0x74
#define TPC2_WR_REGULATOR_SECTION                  0x1000
#define mmTPC2_CFG_BASE                            0x7FFCE86000ull
#define TPC2_CFG_MAX_OFFSET                        0xE30
#define TPC2_CFG_SECTION                           0x2000
#define mmTPC2_QM_BASE                             0x7FFCE88000ull
#define TPC2_QM_MAX_OFFSET                         0x310
#define TPC2_QM_SECTION                            0x1000
#define mmTPC2_CMDQ_BASE                           0x7FFCE89000ull
#define TPC2_CMDQ_MAX_OFFSET                       0x310
#define TPC2_CMDQ_SECTION                          0x37000
#define mmTPC3_RTR_BASE                            0x7FFCEC0000ull
#define TPC3_RTR_MAX_OFFSET                        0x608
#define TPC3_RTR_SECTION                           0x4000
#define mmTPC3_RD_REGULATOR_BASE                   0x7FFCEC4000ull
#define TPC3_RD_REGULATOR_MAX_OFFSET               0x74
#define TPC3_RD_REGULATOR_SECTION                  0x1000
#define mmTPC3_WR_REGULATOR_BASE                   0x7FFCEC5000ull
#define TPC3_WR_REGULATOR_MAX_OFFSET               0x74
#define TPC3_WR_REGULATOR_SECTION                  0x1000
#define mmTPC3_CFG_BASE                            0x7FFCEC6000ull
#define TPC3_CFG_MAX_OFFSET                        0xE30
#define TPC3_CFG_SECTION                           0x2000
#define mmTPC3_QM_BASE                             0x7FFCEC8000ull
#define TPC3_QM_MAX_OFFSET                         0x310
#define TPC3_QM_SECTION                            0x1000
#define mmTPC3_CMDQ_BASE                           0x7FFCEC9000ull
#define TPC3_CMDQ_MAX_OFFSET                       0x310
#define TPC3_CMDQ_SECTION                          0x37000
#define mmTPC4_RTR_BASE                            0x7FFCF00000ull
#define TPC4_RTR_MAX_OFFSET                        0x608
#define TPC4_RTR_SECTION                           0x4000
#define mmTPC4_RD_REGULATOR_BASE                   0x7FFCF04000ull
#define TPC4_RD_REGULATOR_MAX_OFFSET               0x74
#define TPC4_RD_REGULATOR_SECTION                  0x1000
#define mmTPC4_WR_REGULATOR_BASE                   0x7FFCF05000ull
#define TPC4_WR_REGULATOR_MAX_OFFSET               0x74
#define TPC4_WR_REGULATOR_SECTION                  0x1000
#define mmTPC4_CFG_BASE                            0x7FFCF06000ull
#define TPC4_CFG_MAX_OFFSET                        0xE30
#define TPC4_CFG_SECTION                           0x2000
#define mmTPC4_QM_BASE                             0x7FFCF08000ull
#define TPC4_QM_MAX_OFFSET                         0x310
#define TPC4_QM_SECTION                            0x1000
#define mmTPC4_CMDQ_BASE                           0x7FFCF09000ull
#define TPC4_CMDQ_MAX_OFFSET                       0x310
#define TPC4_CMDQ_SECTION                          0x37000
#define mmTPC5_RTR_BASE                            0x7FFCF40000ull
#define TPC5_RTR_MAX_OFFSET                        0x608
#define TPC5_RTR_SECTION                           0x4000
#define mmTPC5_RD_REGULATOR_BASE                   0x7FFCF44000ull
#define TPC5_RD_REGULATOR_MAX_OFFSET               0x74
#define TPC5_RD_REGULATOR_SECTION                  0x1000
#define mmTPC5_WR_REGULATOR_BASE                   0x7FFCF45000ull
#define TPC5_WR_REGULATOR_MAX_OFFSET               0x74
#define TPC5_WR_REGULATOR_SECTION                  0x1000
#define mmTPC5_CFG_BASE                            0x7FFCF46000ull
#define TPC5_CFG_MAX_OFFSET                        0xE30
#define TPC5_CFG_SECTION                           0x2000
#define mmTPC5_QM_BASE                             0x7FFCF48000ull
#define TPC5_QM_MAX_OFFSET                         0x310
#define TPC5_QM_SECTION                            0x1000
#define mmTPC5_CMDQ_BASE                           0x7FFCF49000ull
#define TPC5_CMDQ_MAX_OFFSET                       0x310
#define TPC5_CMDQ_SECTION                          0x37000
#define mmTPC6_RTR_BASE                            0x7FFCF80000ull
#define TPC6_RTR_MAX_OFFSET                        0x608
#define TPC6_RTR_SECTION                           0x4000
#define mmTPC6_RD_REGULATOR_BASE                   0x7FFCF84000ull
#define TPC6_RD_REGULATOR_MAX_OFFSET               0x74
#define TPC6_RD_REGULATOR_SECTION                  0x1000
#define mmTPC6_WR_REGULATOR_BASE                   0x7FFCF85000ull
#define TPC6_WR_REGULATOR_MAX_OFFSET               0x74
#define TPC6_WR_REGULATOR_SECTION                  0x1000
#define mmTPC6_CFG_BASE                            0x7FFCF86000ull
#define TPC6_CFG_MAX_OFFSET                        0xE30
#define TPC6_CFG_SECTION                           0x2000
#define mmTPC6_QM_BASE                             0x7FFCF88000ull
#define TPC6_QM_MAX_OFFSET                         0x310
#define TPC6_QM_SECTION                            0x1000
#define mmTPC6_CMDQ_BASE                           0x7FFCF89000ull
#define TPC6_CMDQ_MAX_OFFSET                       0x310
#define TPC6_CMDQ_SECTION                          0x37000
#define mmTPC7_NRTR_BASE                           0x7FFCFC0000ull
#define TPC7_NRTR_MAX_OFFSET                       0x608
#define TPC7_NRTR_SECTION                          0x4000
#define mmTPC7_RD_REGULATOR_BASE                   0x7FFCFC4000ull
#define TPC7_RD_REGULATOR_MAX_OFFSET               0x74
#define TPC7_RD_REGULATOR_SECTION                  0x1000
#define mmTPC7_WR_REGULATOR_BASE                   0x7FFCFC5000ull
#define TPC7_WR_REGULATOR_MAX_OFFSET               0x74
#define TPC7_WR_REGULATOR_SECTION                  0x1000
#define mmTPC7_CFG_BASE                            0x7FFCFC6000ull
#define TPC7_CFG_MAX_OFFSET                        0xE30
#define TPC7_CFG_SECTION                           0x2000
#define mmTPC7_QM_BASE                             0x7FFCFC8000ull
#define TPC7_QM_MAX_OFFSET                         0x310
#define TPC7_QM_SECTION                            0x1000
#define mmTPC7_CMDQ_BASE                           0x7FFCFC9000ull
#define TPC7_CMDQ_MAX_OFFSET                       0x310
#define TPC7_CMDQ_SECTION                          0x1037000
#define mmMME_TOP_TABLE_BASE                       0x7FFE000000ull
#define MME_TOP_TABLE_MAX_OFFSET                   0x1000
#define MME_TOP_TABLE_SECTION                      0x1000
#define mmMME0_RTR_FUNNEL_BASE                     0x7FFE001000ull
#define MME0_RTR_FUNNEL_MAX_OFFSET                 0x1000
#define MME0_RTR_FUNNEL_SECTION                    0x40000
#define mmMME1_RTR_FUNNEL_BASE                     0x7FFE041000ull
#define MME1_RTR_FUNNEL_MAX_OFFSET                 0x1000
#define MME1_RTR_FUNNEL_SECTION                    0x1000
#define mmMME1_SBA_STM_BASE                        0x7FFE042000ull
#define MME1_SBA_STM_MAX_OFFSET                    0x1000
#define MME1_SBA_STM_SECTION                       0x1000
#define mmMME1_SBA_CTI_BASE                        0x7FFE043000ull
#define MME1_SBA_CTI_MAX_OFFSET                    0x1000
#define MME1_SBA_CTI_SECTION                       0x1000
#define mmMME1_SBA_ETF_BASE                        0x7FFE044000ull
#define MME1_SBA_ETF_MAX_OFFSET                    0x1000
#define MME1_SBA_ETF_SECTION                       0x1000
#define mmMME1_SBA_SPMU_BASE                       0x7FFE045000ull
#define MME1_SBA_SPMU_MAX_OFFSET                   0x1000
#define MME1_SBA_SPMU_SECTION                      0x1000
#define mmMME1_SBA_CTI0_BASE                       0x7FFE046000ull
#define MME1_SBA_CTI0_MAX_OFFSET                   0x1000
#define MME1_SBA_CTI0_SECTION                      0x1000
#define mmMME1_SBA_CTI1_BASE                       0x7FFE047000ull
#define MME1_SBA_CTI1_MAX_OFFSET                   0x1000
#define MME1_SBA_CTI1_SECTION                      0x1000
#define mmMME1_SBA_BMON0_BASE                      0x7FFE048000ull
#define MME1_SBA_BMON0_MAX_OFFSET                  0x1000
#define MME1_SBA_BMON0_SECTION                     0x1000
#define mmMME1_SBA_BMON1_BASE                      0x7FFE049000ull
#define MME1_SBA_BMON1_MAX_OFFSET                  0x1000
#define MME1_SBA_BMON1_SECTION                     0x38000
#define mmMME2_RTR_FUNNEL_BASE                     0x7FFE081000ull
#define MME2_RTR_FUNNEL_MAX_OFFSET                 0x1000
#define MME2_RTR_FUNNEL_SECTION                    0x40000
#define mmMME3_RTR_FUNNEL_BASE                     0x7FFE0C1000ull
#define MME3_RTR_FUNNEL_MAX_OFFSET                 0x1000
#define MME3_RTR_FUNNEL_SECTION                    0x1000
#define mmMME3_SBB_STM_BASE                        0x7FFE0C2000ull
#define MME3_SBB_STM_MAX_OFFSET                    0x1000
#define MME3_SBB_STM_SECTION                       0x1000
#define mmMME3_SBB_CTI_BASE                        0x7FFE0C3000ull
#define MME3_SBB_CTI_MAX_OFFSET                    0x1000
#define MME3_SBB_CTI_SECTION                       0x1000
#define mmMME3_SBB_ETF_BASE                        0x7FFE0C4000ull
#define MME3_SBB_ETF_MAX_OFFSET                    0x1000
#define MME3_SBB_ETF_SECTION                       0x1000
#define mmMME3_SBB_SPMU_BASE                       0x7FFE0C5000ull
#define MME3_SBB_SPMU_MAX_OFFSET                   0x1000
#define MME3_SBB_SPMU_SECTION                      0x1000
#define mmMME3_SBB_CTI0_BASE                       0x7FFE0C6000ull
#define MME3_SBB_CTI0_MAX_OFFSET                   0x1000
#define MME3_SBB_CTI0_SECTION                      0x1000
#define mmMME3_SBB_CTI1_BASE                       0x7FFE0C7000ull
#define MME3_SBB_CTI1_MAX_OFFSET                   0x1000
#define MME3_SBB_CTI1_SECTION                      0x1000
#define mmMME3_SBB_BMON0_BASE                      0x7FFE0C8000ull
#define MME3_SBB_BMON0_MAX_OFFSET                  0x1000
#define MME3_SBB_BMON0_SECTION                     0x1000
#define mmMME3_SBB_BMON1_BASE                      0x7FFE0C9000ull
#define MME3_SBB_BMON1_MAX_OFFSET                  0x1000
#define MME3_SBB_BMON1_SECTION                     0x38000
#define mmMME4_RTR_FUNNEL_BASE                     0x7FFE101000ull
#define MME4_RTR_FUNNEL_MAX_OFFSET                 0x1000
#define MME4_RTR_FUNNEL_SECTION                    0x1000
#define mmMME4_WACS_STM_BASE                       0x7FFE102000ull
#define MME4_WACS_STM_MAX_OFFSET                   0x1000
#define MME4_WACS_STM_SECTION                      0x1000
#define mmMME4_WACS_CTI_BASE                       0x7FFE103000ull
#define MME4_WACS_CTI_MAX_OFFSET                   0x1000
#define MME4_WACS_CTI_SECTION                      0x1000
#define mmMME4_WACS_ETF_BASE                       0x7FFE104000ull
#define MME4_WACS_ETF_MAX_OFFSET                   0x1000
#define MME4_WACS_ETF_SECTION                      0x1000
#define mmMME4_WACS_SPMU_BASE                      0x7FFE105000ull
#define MME4_WACS_SPMU_MAX_OFFSET                  0x1000
#define MME4_WACS_SPMU_SECTION                     0x1000
#define mmMME4_WACS_CTI0_BASE                      0x7FFE106000ull
#define MME4_WACS_CTI0_MAX_OFFSET                  0x1000
#define MME4_WACS_CTI0_SECTION                     0x1000
#define mmMME4_WACS_CTI1_BASE                      0x7FFE107000ull
#define MME4_WACS_CTI1_MAX_OFFSET                  0x1000
#define MME4_WACS_CTI1_SECTION                     0x1000
#define mmMME4_WACS_BMON0_BASE                     0x7FFE108000ull
#define MME4_WACS_BMON0_MAX_OFFSET                 0x1000
#define MME4_WACS_BMON0_SECTION                    0x1000
#define mmMME4_WACS_BMON1_BASE                     0x7FFE109000ull
#define MME4_WACS_BMON1_MAX_OFFSET                 0x1000
#define MME4_WACS_BMON1_SECTION                    0x1000
#define mmMME4_WACS_BMON2_BASE                     0x7FFE10A000ull
#define MME4_WACS_BMON2_MAX_OFFSET                 0x1000
#define MME4_WACS_BMON2_SECTION                    0x1000
#define mmMME4_WACS_BMON3_BASE                     0x7FFE10B000ull
#define MME4_WACS_BMON3_MAX_OFFSET                 0x1000
#define MME4_WACS_BMON3_SECTION                    0x1000
#define mmMME4_WACS_BMON4_BASE                     0x7FFE10C000ull
#define MME4_WACS_BMON4_MAX_OFFSET                 0x1000
#define MME4_WACS_BMON4_SECTION                    0x1000
#define mmMME4_WACS_BMON5_BASE                     0x7FFE10D000ull
#define MME4_WACS_BMON5_MAX_OFFSET                 0x1000
#define MME4_WACS_BMON5_SECTION                    0x1000
#define mmMME4_WACS_BMON6_BASE                     0x7FFE10E000ull
#define MME4_WACS_BMON6_MAX_OFFSET                 0x1000
#define MME4_WACS_BMON6_SECTION                    0x4000
#define mmMME4_WACS2_STM_BASE                      0x7FFE112000ull
#define MME4_WACS2_STM_MAX_OFFSET                  0x1000
#define MME4_WACS2_STM_SECTION                     0x1000
#define mmMME4_WACS2_CTI_BASE                      0x7FFE113000ull
#define MME4_WACS2_CTI_MAX_OFFSET                  0x1000
#define MME4_WACS2_CTI_SECTION                     0x1000
#define mmMME4_WACS2_ETF_BASE                      0x7FFE114000ull
#define MME4_WACS2_ETF_MAX_OFFSET                  0x1000
#define MME4_WACS2_ETF_SECTION                     0x1000
#define mmMME4_WACS2_SPMU_BASE                     0x7FFE115000ull
#define MME4_WACS2_SPMU_MAX_OFFSET                 0x1000
#define MME4_WACS2_SPMU_SECTION                    0x1000
#define mmMME4_WACS2_CTI0_BASE                     0x7FFE116000ull
#define MME4_WACS2_CTI0_MAX_OFFSET                 0x1000
#define MME4_WACS2_CTI0_SECTION                    0x1000
#define mmMME4_WACS2_CTI1_BASE                     0x7FFE117000ull
#define MME4_WACS2_CTI1_MAX_OFFSET                 0x1000
#define MME4_WACS2_CTI1_SECTION                    0x1000
#define mmMME4_WACS2_BMON0_BASE                    0x7FFE118000ull
#define MME4_WACS2_BMON0_MAX_OFFSET                0x1000
#define MME4_WACS2_BMON0_SECTION                   0x1000
#define mmMME4_WACS2_BMON1_BASE                    0x7FFE119000ull
#define MME4_WACS2_BMON1_MAX_OFFSET                0x1000
#define MME4_WACS2_BMON1_SECTION                   0x1000
#define mmMME4_WACS2_BMON2_BASE                    0x7FFE11A000ull
#define MME4_WACS2_BMON2_MAX_OFFSET                0x1000
#define MME4_WACS2_BMON2_SECTION                   0x27000
#define mmMME5_RTR_FUNNEL_BASE                     0x7FFE141000ull
#define MME5_RTR_FUNNEL_MAX_OFFSET                 0x1000
#define MME5_RTR_FUNNEL_SECTION                    0x2BF000
#define mmDMA_ROM_TABLE_BASE                       0x7FFE400000ull
#define DMA_ROM_TABLE_MAX_OFFSET                   0x1000
#define DMA_ROM_TABLE_SECTION                      0x1000
#define mmDMA_CH_0_CS_STM_BASE                     0x7FFE401000ull
#define DMA_CH_0_CS_STM_MAX_OFFSET                 0x1000
#define DMA_CH_0_CS_STM_SECTION                    0x1000
#define mmDMA_CH_0_CS_CTI_BASE                     0x7FFE402000ull
#define DMA_CH_0_CS_CTI_MAX_OFFSET                 0x1000
#define DMA_CH_0_CS_CTI_SECTION                    0x1000
#define mmDMA_CH_0_CS_ETF_BASE                     0x7FFE403000ull
#define DMA_CH_0_CS_ETF_MAX_OFFSET                 0x1000
#define DMA_CH_0_CS_ETF_SECTION                    0x1000
#define mmDMA_CH_0_CS_SPMU_BASE                    0x7FFE404000ull
#define DMA_CH_0_CS_SPMU_MAX_OFFSET                0x1000
#define DMA_CH_0_CS_SPMU_SECTION                   0x1000
#define mmDMA_CH_0_BMON_CTI_BASE                   0x7FFE405000ull
#define DMA_CH_0_BMON_CTI_MAX_OFFSET               0x1000
#define DMA_CH_0_BMON_CTI_SECTION                  0x1000
#define mmDMA_CH_0_USER_CTI_BASE                   0x7FFE406000ull
#define DMA_CH_0_USER_CTI_MAX_OFFSET               0x1000
#define DMA_CH_0_USER_CTI_SECTION                  0x1000
#define mmDMA_CH_0_BMON_0_BASE                     0x7FFE407000ull
#define DMA_CH_0_BMON_0_MAX_OFFSET                 0x1000
#define DMA_CH_0_BMON_0_SECTION                    0x1000
#define mmDMA_CH_0_BMON_1_BASE                     0x7FFE408000ull
#define DMA_CH_0_BMON_1_MAX_OFFSET                 0x1000
#define DMA_CH_0_BMON_1_SECTION                    0x9000
#define mmDMA_CH_1_CS_STM_BASE                     0x7FFE411000ull
#define DMA_CH_1_CS_STM_MAX_OFFSET                 0x1000
#define DMA_CH_1_CS_STM_SECTION                    0x1000
#define mmDMA_CH_1_CS_CTI_BASE                     0x7FFE412000ull
#define DMA_CH_1_CS_CTI_MAX_OFFSET                 0x1000
#define DMA_CH_1_CS_CTI_SECTION                    0x1000
#define mmDMA_CH_1_CS_ETF_BASE                     0x7FFE413000ull
#define DMA_CH_1_CS_ETF_MAX_OFFSET                 0x1000
#define DMA_CH_1_CS_ETF_SECTION                    0x1000
#define mmDMA_CH_1_CS_SPMU_BASE                    0x7FFE414000ull
#define DMA_CH_1_CS_SPMU_MAX_OFFSET                0x1000
#define DMA_CH_1_CS_SPMU_SECTION                   0x1000
#define mmDMA_CH_1_BMON_CTI_BASE                   0x7FFE415000ull
#define DMA_CH_1_BMON_CTI_MAX_OFFSET               0x1000
#define DMA_CH_1_BMON_CTI_SECTION                  0x1000
#define mmDMA_CH_1_USER_CTI_BASE                   0x7FFE416000ull
#define DMA_CH_1_USER_CTI_MAX_OFFSET               0x1000
#define DMA_CH_1_USER_CTI_SECTION                  0x1000
#define mmDMA_CH_1_BMON_0_BASE                     0x7FFE417000ull
#define DMA_CH_1_BMON_0_MAX_OFFSET                 0x1000
#define DMA_CH_1_BMON_0_SECTION                    0x1000
#define mmDMA_CH_1_BMON_1_BASE                     0x7FFE418000ull
#define DMA_CH_1_BMON_1_MAX_OFFSET                 0x1000
#define DMA_CH_1_BMON_1_SECTION                    0x9000
#define mmDMA_CH_2_CS_STM_BASE                     0x7FFE421000ull
#define DMA_CH_2_CS_STM_MAX_OFFSET                 0x1000
#define DMA_CH_2_CS_STM_SECTION                    0x1000
#define mmDMA_CH_2_CS_CTI_BASE                     0x7FFE422000ull
#define DMA_CH_2_CS_CTI_MAX_OFFSET                 0x1000
#define DMA_CH_2_CS_CTI_SECTION                    0x1000
#define mmDMA_CH_2_CS_ETF_BASE                     0x7FFE423000ull
#define DMA_CH_2_CS_ETF_MAX_OFFSET                 0x1000
#define DMA_CH_2_CS_ETF_SECTION                    0x1000
#define mmDMA_CH_2_CS_SPMU_BASE                    0x7FFE424000ull
#define DMA_CH_2_CS_SPMU_MAX_OFFSET                0x1000
#define DMA_CH_2_CS_SPMU_SECTION                   0x1000
#define mmDMA_CH_2_BMON_CTI_BASE                   0x7FFE425000ull
#define DMA_CH_2_BMON_CTI_MAX_OFFSET               0x1000
#define DMA_CH_2_BMON_CTI_SECTION                  0x1000
#define mmDMA_CH_2_USER_CTI_BASE                   0x7FFE426000ull
#define DMA_CH_2_USER_CTI_MAX_OFFSET               0x1000
#define DMA_CH_2_USER_CTI_SECTION                  0x1000
#define mmDMA_CH_2_BMON_0_BASE                     0x7FFE427000ull
#define DMA_CH_2_BMON_0_MAX_OFFSET                 0x1000
#define DMA_CH_2_BMON_0_SECTION                    0x1000
#define mmDMA_CH_2_BMON_1_BASE                     0x7FFE428000ull
#define DMA_CH_2_BMON_1_MAX_OFFSET                 0x1000
#define DMA_CH_2_BMON_1_SECTION                    0x9000
#define mmDMA_CH_3_CS_STM_BASE                     0x7FFE431000ull
#define DMA_CH_3_CS_STM_MAX_OFFSET                 0x1000
#define DMA_CH_3_CS_STM_SECTION                    0x1000
#define mmDMA_CH_3_CS_CTI_BASE                     0x7FFE432000ull
#define DMA_CH_3_CS_CTI_MAX_OFFSET                 0x1000
#define DMA_CH_3_CS_CTI_SECTION                    0x1000
#define mmDMA_CH_3_CS_ETF_BASE                     0x7FFE433000ull
#define DMA_CH_3_CS_ETF_MAX_OFFSET                 0x1000
#define DMA_CH_3_CS_ETF_SECTION                    0x1000
#define mmDMA_CH_3_CS_SPMU_BASE                    0x7FFE434000ull
#define DMA_CH_3_CS_SPMU_MAX_OFFSET                0x1000
#define DMA_CH_3_CS_SPMU_SECTION                   0x1000
#define mmDMA_CH_3_BMON_CTI_BASE                   0x7FFE435000ull
#define DMA_CH_3_BMON_CTI_MAX_OFFSET               0x1000
#define DMA_CH_3_BMON_CTI_SECTION                  0x1000
#define mmDMA_CH_3_USER_CTI_BASE                   0x7FFE436000ull
#define DMA_CH_3_USER_CTI_MAX_OFFSET               0x1000
#define DMA_CH_3_USER_CTI_SECTION                  0x1000
#define mmDMA_CH_3_BMON_0_BASE                     0x7FFE437000ull
#define DMA_CH_3_BMON_0_MAX_OFFSET                 0x1000
#define DMA_CH_3_BMON_0_SECTION                    0x1000
#define mmDMA_CH_3_BMON_1_BASE                     0x7FFE438000ull
#define DMA_CH_3_BMON_1_MAX_OFFSET                 0x1000
#define DMA_CH_3_BMON_1_SECTION                    0x9000
#define mmDMA_CH_4_CS_STM_BASE                     0x7FFE441000ull
#define DMA_CH_4_CS_STM_MAX_OFFSET                 0x1000
#define DMA_CH_4_CS_STM_SECTION                    0x1000
#define mmDMA_CH_4_CS_CTI_BASE                     0x7FFE442000ull
#define DMA_CH_4_CS_CTI_MAX_OFFSET                 0x1000
#define DMA_CH_4_CS_CTI_SECTION                    0x1000
#define mmDMA_CH_4_CS_ETF_BASE                     0x7FFE443000ull
#define DMA_CH_4_CS_ETF_MAX_OFFSET                 0x1000
#define DMA_CH_4_CS_ETF_SECTION                    0x1000
#define mmDMA_CH_4_CS_SPMU_BASE                    0x7FFE444000ull
#define DMA_CH_4_CS_SPMU_MAX_OFFSET                0x1000
#define DMA_CH_4_CS_SPMU_SECTION                   0x1000
#define mmDMA_CH_4_BMON_CTI_BASE                   0x7FFE445000ull
#define DMA_CH_4_BMON_CTI_MAX_OFFSET               0x1000
#define DMA_CH_4_BMON_CTI_SECTION                  0x1000
#define mmDMA_CH_4_USER_CTI_BASE                   0x7FFE446000ull
#define DMA_CH_4_USER_CTI_MAX_OFFSET               0x1000
#define DMA_CH_4_USER_CTI_SECTION                  0x1000
#define mmDMA_CH_4_BMON_0_BASE                     0x7FFE447000ull
#define DMA_CH_4_BMON_0_MAX_OFFSET                 0x1000
#define DMA_CH_4_BMON_0_SECTION                    0x1000
#define mmDMA_CH_4_BMON_1_BASE                     0x7FFE448000ull
#define DMA_CH_4_BMON_1_MAX_OFFSET                 0x1000
#define DMA_CH_4_BMON_1_SECTION                    0x8000
#define mmDMA_CH_FUNNEL_6_1_BASE                   0x7FFE450000ull
#define DMA_CH_FUNNEL_6_1_MAX_OFFSET               0x1000
#define DMA_CH_FUNNEL_6_1_SECTION                  0x11000
#define mmDMA_MACRO_CS_STM_BASE                    0x7FFE461000ull
#define DMA_MACRO_CS_STM_MAX_OFFSET                0x1000
#define DMA_MACRO_CS_STM_SECTION                   0x1000
#define mmDMA_MACRO_CS_CTI_BASE                    0x7FFE462000ull
#define DMA_MACRO_CS_CTI_MAX_OFFSET                0x1000
#define DMA_MACRO_CS_CTI_SECTION                   0x1000
#define mmDMA_MACRO_CS_ETF_BASE                    0x7FFE463000ull
#define DMA_MACRO_CS_ETF_MAX_OFFSET                0x1000
#define DMA_MACRO_CS_ETF_SECTION                   0x1000
#define mmDMA_MACRO_CS_SPMU_BASE                   0x7FFE464000ull
#define DMA_MACRO_CS_SPMU_MAX_OFFSET               0x1000
#define DMA_MACRO_CS_SPMU_SECTION                  0x1000
#define mmDMA_MACRO_BMON_CTI_BASE                  0x7FFE465000ull
#define DMA_MACRO_BMON_CTI_MAX_OFFSET              0x1000
#define DMA_MACRO_BMON_CTI_SECTION                 0x1000
#define mmDMA_MACRO_USER_CTI_BASE                  0x7FFE466000ull
#define DMA_MACRO_USER_CTI_MAX_OFFSET              0x1000
#define DMA_MACRO_USER_CTI_SECTION                 0x1000
#define mmDMA_MACRO_BMON_0_BASE                    0x7FFE467000ull
#define DMA_MACRO_BMON_0_MAX_OFFSET                0x1000
#define DMA_MACRO_BMON_0_SECTION                   0x1000
#define mmDMA_MACRO_BMON_1_BASE                    0x7FFE468000ull
#define DMA_MACRO_BMON_1_MAX_OFFSET                0x1000
#define DMA_MACRO_BMON_1_SECTION                   0x1000
#define mmDMA_MACRO_BMON_2_BASE                    0x7FFE469000ull
#define DMA_MACRO_BMON_2_MAX_OFFSET                0x1000
#define DMA_MACRO_BMON_2_SECTION                   0x1000
#define mmDMA_MACRO_BMON_3_BASE                    0x7FFE46A000ull
#define DMA_MACRO_BMON_3_MAX_OFFSET                0x1000
#define DMA_MACRO_BMON_3_SECTION                   0x1000
#define mmDMA_MACRO_BMON_4_BASE                    0x7FFE46B000ull
#define DMA_MACRO_BMON_4_MAX_OFFSET                0x1000
#define DMA_MACRO_BMON_4_SECTION                   0x1000
#define mmDMA_MACRO_BMON_5_BASE                    0x7FFE46C000ull
#define DMA_MACRO_BMON_5_MAX_OFFSET                0x1000
#define DMA_MACRO_BMON_5_SECTION                   0x1000
#define mmDMA_MACRO_BMON_6_BASE                    0x7FFE46D000ull
#define DMA_MACRO_BMON_6_MAX_OFFSET                0x1000
#define DMA_MACRO_BMON_6_SECTION                   0x1000
#define mmDMA_MACRO_BMON_7_BASE                    0x7FFE46E000ull
#define DMA_MACRO_BMON_7_MAX_OFFSET                0x1000
#define DMA_MACRO_BMON_7_SECTION                   0x2000
#define mmDMA_MACRO_FUNNEL_3_1_BASE                0x7FFE470000ull
#define DMA_MACRO_FUNNEL_3_1_MAX_OFFSET            0x1000
#define DMA_MACRO_FUNNEL_3_1_SECTION               0x10000
#define mmCPU_ROM_TABLE_BASE                       0x7FFE480000ull
#define CPU_ROM_TABLE_MAX_OFFSET                   0x1000
#define CPU_ROM_TABLE_SECTION                      0x1000
#define mmCPU_ETF_0_BASE                           0x7FFE481000ull
#define CPU_ETF_0_MAX_OFFSET                       0x1000
#define CPU_ETF_0_SECTION                          0x1000
#define mmCPU_ETF_1_BASE                           0x7FFE482000ull
#define CPU_ETF_1_MAX_OFFSET                       0x1000
#define CPU_ETF_1_SECTION                          0x2000
#define mmCPU_CTI_BASE                             0x7FFE484000ull
#define CPU_CTI_MAX_OFFSET                         0x1000
#define CPU_CTI_SECTION                            0x1000
#define mmCPU_FUNNEL_BASE                          0x7FFE485000ull
#define CPU_FUNNEL_MAX_OFFSET                      0x1000
#define CPU_FUNNEL_SECTION                         0x1000
#define mmCPU_STM_BASE                             0x7FFE486000ull
#define CPU_STM_MAX_OFFSET                         0x1000
#define CPU_STM_SECTION                            0x1000
#define mmCPU_CTI_TRACE_BASE                       0x7FFE487000ull
#define CPU_CTI_TRACE_MAX_OFFSET                   0x1000
#define CPU_CTI_TRACE_SECTION                      0x1000
#define mmCPU_ETF_TRACE_BASE                       0x7FFE488000ull
#define CPU_ETF_TRACE_MAX_OFFSET                   0x1000
#define CPU_ETF_TRACE_SECTION                      0x1000
#define mmCPU_WR_BMON_BASE                         0x7FFE489000ull
#define CPU_WR_BMON_MAX_OFFSET                     0x1000
#define CPU_WR_BMON_SECTION                        0x1000
#define mmCPU_RD_BMON_BASE                         0x7FFE48A000ull
#define CPU_RD_BMON_MAX_OFFSET                     0x1000
#define CPU_RD_BMON_SECTION                        0x37000
#define mmMMU_CS_STM_BASE                          0x7FFE4C1000ull
#define MMU_CS_STM_MAX_OFFSET                      0x1000
#define MMU_CS_STM_SECTION                         0x1000
#define mmMMU_CS_CTI_BASE                          0x7FFE4C2000ull
#define MMU_CS_CTI_MAX_OFFSET                      0x1000
#define MMU_CS_CTI_SECTION                         0x1000
#define mmMMU_CS_ETF_BASE                          0x7FFE4C3000ull
#define MMU_CS_ETF_MAX_OFFSET                      0x1000
#define MMU_CS_ETF_SECTION                         0x1000
#define mmMMU_CS_SPMU_BASE                         0x7FFE4C4000ull
#define MMU_CS_SPMU_MAX_OFFSET                     0x1000
#define MMU_CS_SPMU_SECTION                        0x1000
#define mmMMU_BMON_CTI_BASE                        0x7FFE4C5000ull
#define MMU_BMON_CTI_MAX_OFFSET                    0x1000
#define MMU_BMON_CTI_SECTION                       0x1000
#define mmMMU_USER_CTI_BASE                        0x7FFE4C6000ull
#define MMU_USER_CTI_MAX_OFFSET                    0x1000
#define MMU_USER_CTI_SECTION                       0x1000
#define mmMMU_BMON_0_BASE                          0x7FFE4C7000ull
#define MMU_BMON_0_MAX_OFFSET                      0x1000
#define MMU_BMON_0_SECTION                         0x1000
#define mmMMU_BMON_1_BASE                          0x7FFE4C8000ull
#define MMU_BMON_1_MAX_OFFSET                      0x1000
#define MMU_BMON_1_SECTION                         0x338000
#define mmCA53_BASE                                0x7FFE800000ull
#define CA53_MAX_OFFSET                            0x1000
#define CA53_SECTION                               0x400000
#define mmPCI_ROM_TABLE_BASE                       0x7FFEC00000ull
#define PCI_ROM_TABLE_MAX_OFFSET                   0x1000
#define PCI_ROM_TABLE_SECTION                      0x1000
#define mmPCIE_STM_BASE                            0x7FFEC01000ull
#define PCIE_STM_MAX_OFFSET                        0x1000
#define PCIE_STM_SECTION                           0x1000
#define mmPCIE_ETF_BASE                            0x7FFEC02000ull
#define PCIE_ETF_MAX_OFFSET                        0x1000
#define PCIE_ETF_SECTION                           0x1000
#define mmPCIE_CTI_0_BASE                          0x7FFEC03000ull
#define PCIE_CTI_0_MAX_OFFSET                      0x1000
#define PCIE_CTI_0_SECTION                         0x1000
#define mmPCIE_SPMU_BASE                           0x7FFEC04000ull
#define PCIE_SPMU_MAX_OFFSET                       0x1000
#define PCIE_SPMU_SECTION                          0x1000
#define mmPCIE_CTI_1_BASE                          0x7FFEC05000ull
#define PCIE_CTI_1_MAX_OFFSET                      0x1000
#define PCIE_CTI_1_SECTION                         0x1000
#define mmPCIE_FUNNEL_BASE                         0x7FFEC06000ull
#define PCIE_FUNNEL_MAX_OFFSET                     0x1000
#define PCIE_FUNNEL_SECTION                        0x1000
#define mmPCIE_BMON_MSTR_WR_BASE                   0x7FFEC07000ull
#define PCIE_BMON_MSTR_WR_MAX_OFFSET               0x1000
#define PCIE_BMON_MSTR_WR_SECTION                  0x1000
#define mmPCIE_BMON_MSTR_RD_BASE                   0x7FFEC08000ull
#define PCIE_BMON_MSTR_RD_MAX_OFFSET               0x1000
#define PCIE_BMON_MSTR_RD_SECTION                  0x1000
#define mmPCIE_BMON_SLV_WR_BASE                    0x7FFEC09000ull
#define PCIE_BMON_SLV_WR_MAX_OFFSET                0x1000
#define PCIE_BMON_SLV_WR_SECTION                   0x1000
#define mmPCIE_BMON_SLV_RD_BASE                    0x7FFEC0A000ull
#define PCIE_BMON_SLV_RD_MAX_OFFSET                0x1000
#define PCIE_BMON_SLV_RD_SECTION                   0x36000
#define mmPSOC_CTI_BASE                            0x7FFEC40000ull
#define PSOC_CTI_MAX_OFFSET                        0x1000
#define PSOC_CTI_SECTION                           0x1000
#define mmPSOC_STM_BASE                            0x7FFEC41000ull
#define PSOC_STM_MAX_OFFSET                        0x1000
#define PSOC_STM_SECTION                           0x1000
#define mmPSOC_FUNNEL_BASE                         0x7FFEC42000ull
#define PSOC_FUNNEL_MAX_OFFSET                     0x1000
#define PSOC_FUNNEL_SECTION                        0x1000
#define mmPSOC_ETR_BASE                            0x7FFEC43000ull
#define PSOC_ETR_MAX_OFFSET                        0x1000
#define PSOC_ETR_SECTION                           0x1000
#define mmPSOC_ETF_BASE                            0x7FFEC44000ull
#define PSOC_ETF_MAX_OFFSET                        0x1000
#define PSOC_ETF_SECTION                           0x1000
#define mmPSOC_TS_CTI_BASE                         0x7FFEC45000ull
#define PSOC_TS_CTI_MAX_OFFSET                     0x1000
#define PSOC_TS_CTI_SECTION                        0xB000
#define mmTOP_ROM_TABLE_BASE                       0x7FFEC50000ull
#define TOP_ROM_TABLE_MAX_OFFSET                   0x1000
#define TOP_ROM_TABLE_SECTION                      0x1F0000
#define mmTPC1_RTR_FUNNEL_BASE                     0x7FFEE40000ull
#define TPC1_RTR_FUNNEL_MAX_OFFSET                 0x1000
#define TPC1_RTR_FUNNEL_SECTION                    0x40000
#define mmTPC2_RTR_FUNNEL_BASE                     0x7FFEE80000ull
#define TPC2_RTR_FUNNEL_MAX_OFFSET                 0x1000
#define TPC2_RTR_FUNNEL_SECTION                    0x40000
#define mmTPC3_RTR_FUNNEL_BASE                     0x7FFEEC0000ull
#define TPC3_RTR_FUNNEL_MAX_OFFSET                 0x1000
#define TPC3_RTR_FUNNEL_SECTION                    0x40000
#define mmTPC4_RTR_FUNNEL_BASE                     0x7FFEF00000ull
#define TPC4_RTR_FUNNEL_MAX_OFFSET                 0x1000
#define TPC4_RTR_FUNNEL_SECTION                    0x40000
#define mmTPC5_RTR_FUNNEL_BASE                     0x7FFEF40000ull
#define TPC5_RTR_FUNNEL_MAX_OFFSET                 0x1000
#define TPC5_RTR_FUNNEL_SECTION                    0x40000
#define mmTPC6_RTR_FUNNEL_BASE                     0x7FFEF80000ull
#define TPC6_RTR_FUNNEL_MAX_OFFSET                 0x1000
#define TPC6_RTR_FUNNEL_SECTION                    0x81000
#define mmTPC0_EML_SPMU_BASE                       0x7FFF001000ull
#define TPC0_EML_SPMU_MAX_OFFSET                   0x1000
#define TPC0_EML_SPMU_SECTION                      0x1000
#define mmTPC0_EML_ETF_BASE                        0x7FFF002000ull
#define TPC0_EML_ETF_MAX_OFFSET                    0x1000
#define TPC0_EML_ETF_SECTION                       0x1000
#define mmTPC0_EML_STM_BASE                        0x7FFF003000ull
#define TPC0_EML_STM_MAX_OFFSET                    0x1000
#define TPC0_EML_STM_SECTION                       0x1000
#define mmTPC0_EML_ETM_R4_BASE                     0x7FFF004000ull
#define TPC0_EML_ETM_R4_MAX_OFFSET                 0x0
#define TPC0_EML_ETM_R4_SECTION                    0x1000
#define mmTPC0_EML_CTI_BASE                        0x7FFF005000ull
#define TPC0_EML_CTI_MAX_OFFSET                    0x1000
#define TPC0_EML_CTI_SECTION                       0x1000
#define mmTPC0_EML_FUNNEL_BASE                     0x7FFF006000ull
#define TPC0_EML_FUNNEL_MAX_OFFSET                 0x1000
#define TPC0_EML_FUNNEL_SECTION                    0x1000
#define mmTPC0_EML_BUSMON_0_BASE                   0x7FFF007000ull
#define TPC0_EML_BUSMON_0_MAX_OFFSET               0x1000
#define TPC0_EML_BUSMON_0_SECTION                  0x1000
#define mmTPC0_EML_BUSMON_1_BASE                   0x7FFF008000ull
#define TPC0_EML_BUSMON_1_MAX_OFFSET               0x1000
#define TPC0_EML_BUSMON_1_SECTION                  0x1000
#define mmTPC0_EML_BUSMON_2_BASE                   0x7FFF009000ull
#define TPC0_EML_BUSMON_2_MAX_OFFSET               0x1000
#define TPC0_EML_BUSMON_2_SECTION                  0x1000
#define mmTPC0_EML_BUSMON_3_BASE                   0x7FFF00A000ull
#define TPC0_EML_BUSMON_3_MAX_OFFSET               0x1000
#define TPC0_EML_BUSMON_3_SECTION                  0x36000
#define mmTPC0_EML_CFG_BASE                        0x7FFF040000ull
#define TPC0_EML_CFG_MAX_OFFSET                    0x338
#define TPC0_EML_CFG_SECTION                       0x1BF000
#define mmTPC0_EML_CS_BASE                         0x7FFF1FF000ull
#define TPC0_EML_CS_MAX_OFFSET                     0x1000
#define TPC0_EML_CS_SECTION                        0x2000
#define mmTPC1_EML_SPMU_BASE                       0x7FFF201000ull
#define TPC1_EML_SPMU_MAX_OFFSET                   0x1000
#define TPC1_EML_SPMU_SECTION                      0x1000
#define mmTPC1_EML_ETF_BASE                        0x7FFF202000ull
#define TPC1_EML_ETF_MAX_OFFSET                    0x1000
#define TPC1_EML_ETF_SECTION                       0x1000
#define mmTPC1_EML_STM_BASE                        0x7FFF203000ull
#define TPC1_EML_STM_MAX_OFFSET                    0x1000
#define TPC1_EML_STM_SECTION                       0x1000
#define mmTPC1_EML_ETM_R4_BASE                     0x7FFF204000ull
#define TPC1_EML_ETM_R4_MAX_OFFSET                 0x0
#define TPC1_EML_ETM_R4_SECTION                    0x1000
#define mmTPC1_EML_CTI_BASE                        0x7FFF205000ull
#define TPC1_EML_CTI_MAX_OFFSET                    0x1000
#define TPC1_EML_CTI_SECTION                       0x1000
#define mmTPC1_EML_FUNNEL_BASE                     0x7FFF206000ull
#define TPC1_EML_FUNNEL_MAX_OFFSET                 0x1000
#define TPC1_EML_FUNNEL_SECTION                    0x1000
#define mmTPC1_EML_BUSMON_0_BASE                   0x7FFF207000ull
#define TPC1_EML_BUSMON_0_MAX_OFFSET               0x1000
#define TPC1_EML_BUSMON_0_SECTION                  0x1000
#define mmTPC1_EML_BUSMON_1_BASE                   0x7FFF208000ull
#define TPC1_EML_BUSMON_1_MAX_OFFSET               0x1000
#define TPC1_EML_BUSMON_1_SECTION                  0x1000
#define mmTPC1_EML_BUSMON_2_BASE                   0x7FFF209000ull
#define TPC1_EML_BUSMON_2_MAX_OFFSET               0x1000
#define TPC1_EML_BUSMON_2_SECTION                  0x1000
#define mmTPC1_EML_BUSMON_3_BASE                   0x7FFF20A000ull
#define TPC1_EML_BUSMON_3_MAX_OFFSET               0x1000
#define TPC1_EML_BUSMON_3_SECTION                  0x36000
#define mmTPC1_EML_CFG_BASE                        0x7FFF240000ull
#define TPC1_EML_CFG_MAX_OFFSET                    0x338
#define TPC1_EML_CFG_SECTION                       0x1BF000
#define mmTPC1_EML_CS_BASE                         0x7FFF3FF000ull
#define TPC1_EML_CS_MAX_OFFSET                     0x1000
#define TPC1_EML_CS_SECTION                        0x2000
#define mmTPC2_EML_SPMU_BASE                       0x7FFF401000ull
#define TPC2_EML_SPMU_MAX_OFFSET                   0x1000
#define TPC2_EML_SPMU_SECTION                      0x1000
#define mmTPC2_EML_ETF_BASE                        0x7FFF402000ull
#define TPC2_EML_ETF_MAX_OFFSET                    0x1000
#define TPC2_EML_ETF_SECTION                       0x1000
#define mmTPC2_EML_STM_BASE                        0x7FFF403000ull
#define TPC2_EML_STM_MAX_OFFSET                    0x1000
#define TPC2_EML_STM_SECTION                       0x1000
#define mmTPC2_EML_ETM_R4_BASE                     0x7FFF404000ull
#define TPC2_EML_ETM_R4_MAX_OFFSET                 0x0
#define TPC2_EML_ETM_R4_SECTION                    0x1000
#define mmTPC2_EML_CTI_BASE                        0x7FFF405000ull
#define TPC2_EML_CTI_MAX_OFFSET                    0x1000
#define TPC2_EML_CTI_SECTION                       0x1000
#define mmTPC2_EML_FUNNEL_BASE                     0x7FFF406000ull
#define TPC2_EML_FUNNEL_MAX_OFFSET                 0x1000
#define TPC2_EML_FUNNEL_SECTION                    0x1000
#define mmTPC2_EML_BUSMON_0_BASE                   0x7FFF407000ull
#define TPC2_EML_BUSMON_0_MAX_OFFSET               0x1000
#define TPC2_EML_BUSMON_0_SECTION                  0x1000
#define mmTPC2_EML_BUSMON_1_BASE                   0x7FFF408000ull
#define TPC2_EML_BUSMON_1_MAX_OFFSET               0x1000
#define TPC2_EML_BUSMON_1_SECTION                  0x1000
#define mmTPC2_EML_BUSMON_2_BASE                   0x7FFF409000ull
#define TPC2_EML_BUSMON_2_MAX_OFFSET               0x1000
#define TPC2_EML_BUSMON_2_SECTION                  0x1000
#define mmTPC2_EML_BUSMON_3_BASE                   0x7FFF40A000ull
#define TPC2_EML_BUSMON_3_MAX_OFFSET               0x1000
#define TPC2_EML_BUSMON_3_SECTION                  0x36000
#define mmTPC2_EML_CFG_BASE                        0x7FFF440000ull
#define TPC2_EML_CFG_MAX_OFFSET                    0x338
#define TPC2_EML_CFG_SECTION                       0x1BF000
#define mmTPC2_EML_CS_BASE                         0x7FFF5FF000ull
#define TPC2_EML_CS_MAX_OFFSET                     0x1000
#define TPC2_EML_CS_SECTION                        0x2000
#define mmTPC3_EML_SPMU_BASE                       0x7FFF601000ull
#define TPC3_EML_SPMU_MAX_OFFSET                   0x1000
#define TPC3_EML_SPMU_SECTION                      0x1000
#define mmTPC3_EML_ETF_BASE                        0x7FFF602000ull
#define TPC3_EML_ETF_MAX_OFFSET                    0x1000
#define TPC3_EML_ETF_SECTION                       0x1000
#define mmTPC3_EML_STM_BASE                        0x7FFF603000ull
#define TPC3_EML_STM_MAX_OFFSET                    0x1000
#define TPC3_EML_STM_SECTION                       0x1000
#define mmTPC3_EML_ETM_R4_BASE                     0x7FFF604000ull
#define TPC3_EML_ETM_R4_MAX_OFFSET                 0x0
#define TPC3_EML_ETM_R4_SECTION                    0x1000
#define mmTPC3_EML_CTI_BASE                        0x7FFF605000ull
#define TPC3_EML_CTI_MAX_OFFSET                    0x1000
#define TPC3_EML_CTI_SECTION                       0x1000
#define mmTPC3_EML_FUNNEL_BASE                     0x7FFF606000ull
#define TPC3_EML_FUNNEL_MAX_OFFSET                 0x1000
#define TPC3_EML_FUNNEL_SECTION                    0x1000
#define mmTPC3_EML_BUSMON_0_BASE                   0x7FFF607000ull
#define TPC3_EML_BUSMON_0_MAX_OFFSET               0x1000
#define TPC3_EML_BUSMON_0_SECTION                  0x1000
#define mmTPC3_EML_BUSMON_1_BASE                   0x7FFF608000ull
#define TPC3_EML_BUSMON_1_MAX_OFFSET               0x1000
#define TPC3_EML_BUSMON_1_SECTION                  0x1000
#define mmTPC3_EML_BUSMON_2_BASE                   0x7FFF609000ull
#define TPC3_EML_BUSMON_2_MAX_OFFSET               0x1000
#define TPC3_EML_BUSMON_2_SECTION                  0x1000
#define mmTPC3_EML_BUSMON_3_BASE                   0x7FFF60A000ull
#define TPC3_EML_BUSMON_3_MAX_OFFSET               0x1000
#define TPC3_EML_BUSMON_3_SECTION                  0x36000
#define mmTPC3_EML_CFG_BASE                        0x7FFF640000ull
#define TPC3_EML_CFG_MAX_OFFSET                    0x338
#define TPC3_EML_CFG_SECTION                       0x1BF000
#define mmTPC3_EML_CS_BASE                         0x7FFF7FF000ull
#define TPC3_EML_CS_MAX_OFFSET                     0x1000
#define TPC3_EML_CS_SECTION                        0x2000
#define mmTPC4_EML_SPMU_BASE                       0x7FFF801000ull
#define TPC4_EML_SPMU_MAX_OFFSET                   0x1000
#define TPC4_EML_SPMU_SECTION                      0x1000
#define mmTPC4_EML_ETF_BASE                        0x7FFF802000ull
#define TPC4_EML_ETF_MAX_OFFSET                    0x1000
#define TPC4_EML_ETF_SECTION                       0x1000
#define mmTPC4_EML_STM_BASE                        0x7FFF803000ull
#define TPC4_EML_STM_MAX_OFFSET                    0x1000
#define TPC4_EML_STM_SECTION                       0x1000
#define mmTPC4_EML_ETM_R4_BASE                     0x7FFF804000ull
#define TPC4_EML_ETM_R4_MAX_OFFSET                 0x0
#define TPC4_EML_ETM_R4_SECTION                    0x1000
#define mmTPC4_EML_CTI_BASE                        0x7FFF805000ull
#define TPC4_EML_CTI_MAX_OFFSET                    0x1000
#define TPC4_EML_CTI_SECTION                       0x1000
#define mmTPC4_EML_FUNNEL_BASE                     0x7FFF806000ull
#define TPC4_EML_FUNNEL_MAX_OFFSET                 0x1000
#define TPC4_EML_FUNNEL_SECTION                    0x1000
#define mmTPC4_EML_BUSMON_0_BASE                   0x7FFF807000ull
#define TPC4_EML_BUSMON_0_MAX_OFFSET               0x1000
#define TPC4_EML_BUSMON_0_SECTION                  0x1000
#define mmTPC4_EML_BUSMON_1_BASE                   0x7FFF808000ull
#define TPC4_EML_BUSMON_1_MAX_OFFSET               0x1000
#define TPC4_EML_BUSMON_1_SECTION                  0x1000
#define mmTPC4_EML_BUSMON_2_BASE                   0x7FFF809000ull
#define TPC4_EML_BUSMON_2_MAX_OFFSET               0x1000
#define TPC4_EML_BUSMON_2_SECTION                  0x1000
#define mmTPC4_EML_BUSMON_3_BASE                   0x7FFF80A000ull
#define TPC4_EML_BUSMON_3_MAX_OFFSET               0x1000
#define TPC4_EML_BUSMON_3_SECTION                  0x36000
#define mmTPC4_EML_CFG_BASE                        0x7FFF840000ull
#define TPC4_EML_CFG_MAX_OFFSET                    0x338
#define TPC4_EML_CFG_SECTION                       0x1BF000
#define mmTPC4_EML_CS_BASE                         0x7FFF9FF000ull
#define TPC4_EML_CS_MAX_OFFSET                     0x1000
#define TPC4_EML_CS_SECTION                        0x2000
#define mmTPC5_EML_SPMU_BASE                       0x7FFFA01000ull
#define TPC5_EML_SPMU_MAX_OFFSET                   0x1000
#define TPC5_EML_SPMU_SECTION                      0x1000
#define mmTPC5_EML_ETF_BASE                        0x7FFFA02000ull
#define TPC5_EML_ETF_MAX_OFFSET                    0x1000
#define TPC5_EML_ETF_SECTION                       0x1000
#define mmTPC5_EML_STM_BASE                        0x7FFFA03000ull
#define TPC5_EML_STM_MAX_OFFSET                    0x1000
#define TPC5_EML_STM_SECTION                       0x1000
#define mmTPC5_EML_ETM_R4_BASE                     0x7FFFA04000ull
#define TPC5_EML_ETM_R4_MAX_OFFSET                 0x0
#define TPC5_EML_ETM_R4_SECTION                    0x1000
#define mmTPC5_EML_CTI_BASE                        0x7FFFA05000ull
#define TPC5_EML_CTI_MAX_OFFSET                    0x1000
#define TPC5_EML_CTI_SECTION                       0x1000
#define mmTPC5_EML_FUNNEL_BASE                     0x7FFFA06000ull
#define TPC5_EML_FUNNEL_MAX_OFFSET                 0x1000
#define TPC5_EML_FUNNEL_SECTION                    0x1000
#define mmTPC5_EML_BUSMON_0_BASE                   0x7FFFA07000ull
#define TPC5_EML_BUSMON_0_MAX_OFFSET               0x1000
#define TPC5_EML_BUSMON_0_SECTION                  0x1000
#define mmTPC5_EML_BUSMON_1_BASE                   0x7FFFA08000ull
#define TPC5_EML_BUSMON_1_MAX_OFFSET               0x1000
#define TPC5_EML_BUSMON_1_SECTION                  0x1000
#define mmTPC5_EML_BUSMON_2_BASE                   0x7FFFA09000ull
#define TPC5_EML_BUSMON_2_MAX_OFFSET               0x1000
#define TPC5_EML_BUSMON_2_SECTION                  0x1000
#define mmTPC5_EML_BUSMON_3_BASE                   0x7FFFA0A000ull
#define TPC5_EML_BUSMON_3_MAX_OFFSET               0x1000
#define TPC5_EML_BUSMON_3_SECTION                  0x36000
#define mmTPC5_EML_CFG_BASE                        0x7FFFA40000ull
#define TPC5_EML_CFG_MAX_OFFSET                    0x338
#define TPC5_EML_CFG_SECTION                       0x1BF000
#define mmTPC5_EML_CS_BASE                         0x7FFFBFF000ull
#define TPC5_EML_CS_MAX_OFFSET                     0x1000
#define TPC5_EML_CS_SECTION                        0x2000
#define mmTPC6_EML_SPMU_BASE                       0x7FFFC01000ull
#define TPC6_EML_SPMU_MAX_OFFSET                   0x1000
#define TPC6_EML_SPMU_SECTION                      0x1000
#define mmTPC6_EML_ETF_BASE                        0x7FFFC02000ull
#define TPC6_EML_ETF_MAX_OFFSET                    0x1000
#define TPC6_EML_ETF_SECTION                       0x1000
#define mmTPC6_EML_STM_BASE                        0x7FFFC03000ull
#define TPC6_EML_STM_MAX_OFFSET                    0x1000
#define TPC6_EML_STM_SECTION                       0x1000
#define mmTPC6_EML_ETM_R4_BASE                     0x7FFFC04000ull
#define TPC6_EML_ETM_R4_MAX_OFFSET                 0x0
#define TPC6_EML_ETM_R4_SECTION                    0x1000
#define mmTPC6_EML_CTI_BASE                        0x7FFFC05000ull
#define TPC6_EML_CTI_MAX_OFFSET                    0x1000
#define TPC6_EML_CTI_SECTION                       0x1000
#define mmTPC6_EML_FUNNEL_BASE                     0x7FFFC06000ull
#define TPC6_EML_FUNNEL_MAX_OFFSET                 0x1000
#define TPC6_EML_FUNNEL_SECTION                    0x1000
#define mmTPC6_EML_BUSMON_0_BASE                   0x7FFFC07000ull
#define TPC6_EML_BUSMON_0_MAX_OFFSET               0x1000
#define TPC6_EML_BUSMON_0_SECTION                  0x1000
#define mmTPC6_EML_BUSMON_1_BASE                   0x7FFFC08000ull
#define TPC6_EML_BUSMON_1_MAX_OFFSET               0x1000
#define TPC6_EML_BUSMON_1_SECTION                  0x1000
#define mmTPC6_EML_BUSMON_2_BASE                   0x7FFFC09000ull
#define TPC6_EML_BUSMON_2_MAX_OFFSET               0x1000
#define TPC6_EML_BUSMON_2_SECTION                  0x1000
#define mmTPC6_EML_BUSMON_3_BASE                   0x7FFFC0A000ull
#define TPC6_EML_BUSMON_3_MAX_OFFSET               0x1000
#define TPC6_EML_BUSMON_3_SECTION                  0x36000
#define mmTPC6_EML_CFG_BASE                        0x7FFFC40000ull
#define TPC6_EML_CFG_MAX_OFFSET                    0x338
#define TPC6_EML_CFG_SECTION                       0x1BF000
#define mmTPC6_EML_CS_BASE                         0x7FFFDFF000ull
#define TPC6_EML_CS_MAX_OFFSET                     0x1000
#define TPC6_EML_CS_SECTION                        0x2000
#define mmTPC7_EML_SPMU_BASE                       0x7FFFE01000ull
#define TPC7_EML_SPMU_MAX_OFFSET                   0x1000
#define TPC7_EML_SPMU_SECTION                      0x1000
#define mmTPC7_EML_ETF_BASE                        0x7FFFE02000ull
#define TPC7_EML_ETF_MAX_OFFSET                    0x1000
#define TPC7_EML_ETF_SECTION                       0x1000
#define mmTPC7_EML_STM_BASE                        0x7FFFE03000ull
#define TPC7_EML_STM_MAX_OFFSET                    0x1000
#define TPC7_EML_STM_SECTION                       0x1000
#define mmTPC7_EML_ETM_R4_BASE                     0x7FFFE04000ull
#define TPC7_EML_ETM_R4_MAX_OFFSET                 0x0
#define TPC7_EML_ETM_R4_SECTION                    0x1000
#define mmTPC7_EML_CTI_BASE                        0x7FFFE05000ull
#define TPC7_EML_CTI_MAX_OFFSET                    0x1000
#define TPC7_EML_CTI_SECTION                       0x1000
#define mmTPC7_EML_FUNNEL_BASE                     0x7FFFE06000ull
#define TPC7_EML_FUNNEL_MAX_OFFSET                 0x1000
#define TPC7_EML_FUNNEL_SECTION                    0x1000
#define mmTPC7_EML_BUSMON_0_BASE                   0x7FFFE07000ull
#define TPC7_EML_BUSMON_0_MAX_OFFSET               0x1000
#define TPC7_EML_BUSMON_0_SECTION                  0x1000
#define mmTPC7_EML_BUSMON_1_BASE                   0x7FFFE08000ull
#define TPC7_EML_BUSMON_1_MAX_OFFSET               0x1000
#define TPC7_EML_BUSMON_1_SECTION                  0x1000
#define mmTPC7_EML_BUSMON_2_BASE                   0x7FFFE09000ull
#define TPC7_EML_BUSMON_2_MAX_OFFSET               0x1000
#define TPC7_EML_BUSMON_2_SECTION                  0x1000
#define mmTPC7_EML_BUSMON_3_BASE                   0x7FFFE0A000ull
#define TPC7_EML_BUSMON_3_MAX_OFFSET               0x1000
#define TPC7_EML_BUSMON_3_SECTION                  0x36000
#define mmTPC7_EML_CFG_BASE                        0x7FFFE40000ull
#define TPC7_EML_CFG_MAX_OFFSET                    0x338
#define TPC7_EML_CFG_SECTION                       0x1BF000
#define mmTPC7_EML_CS_BASE                         0x7FFFFFF000ull
#define TPC7_EML_CS_MAX_OFFSET                     0x1000

#endif /* GOYA_BLOCKS_H_ */
