/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2018 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_CPU_PLL_REGS_H_
#define ASIC_REG_CPU_PLL_REGS_H_

/*
 *****************************************
 *   CPU_PLL (Prototype: PLL)
 *****************************************
 */

#define mmCPU_PLL_NR                                                 0x4A2100

#define mmCPU_PLL_NF                                                 0x4A2104

#define mmCPU_PLL_OD                                                 0x4A2108

#define mmCPU_PLL_NB                                                 0x4A210C

#define mmCPU_PLL_CFG                                                0x4A2110

#define mmCPU_PLL_LOSE_MASK                                          0x4A2120

#define mmCPU_PLL_LOCK_INTR                                          0x4A2128

#define mmCPU_PLL_LOCK_BYPASS                                        0x4A212C

#define mmCPU_PLL_DATA_CHNG                                          0x4A2130

#define mmCPU_PLL_RST                                                0x4A2134

#define mmCPU_PLL_SLIP_WD_CNTR                                       0x4A2150

#define mmCPU_PLL_DIV_FACTOR_0                                       0x4A2200

#define mmCPU_PLL_DIV_FACTOR_1                                       0x4A2204

#define mmCPU_PLL_DIV_FACTOR_2                                       0x4A2208

#define mmCPU_PLL_DIV_FACTOR_3                                       0x4A220C

#define mmCPU_PLL_DIV_FACTOR_CMD_0                                   0x4A2220

#define mmCPU_PLL_DIV_FACTOR_CMD_1                                   0x4A2224

#define mmCPU_PLL_DIV_FACTOR_CMD_2                                   0x4A2228

#define mmCPU_PLL_DIV_FACTOR_CMD_3                                   0x4A222C

#define mmCPU_PLL_DIV_SEL_0                                          0x4A2280

#define mmCPU_PLL_DIV_SEL_1                                          0x4A2284

#define mmCPU_PLL_DIV_SEL_2                                          0x4A2288

#define mmCPU_PLL_DIV_SEL_3                                          0x4A228C

#define mmCPU_PLL_DIV_EN_0                                           0x4A22A0

#define mmCPU_PLL_DIV_EN_1                                           0x4A22A4

#define mmCPU_PLL_DIV_EN_2                                           0x4A22A8

#define mmCPU_PLL_DIV_EN_3                                           0x4A22AC

#define mmCPU_PLL_DIV_FACTOR_BUSY_0                                  0x4A22C0

#define mmCPU_PLL_DIV_FACTOR_BUSY_1                                  0x4A22C4

#define mmCPU_PLL_DIV_FACTOR_BUSY_2                                  0x4A22C8

#define mmCPU_PLL_DIV_FACTOR_BUSY_3                                  0x4A22CC

#define mmCPU_PLL_CLK_GATER                                          0x4A2300

#define mmCPU_PLL_CLK_RLX_0                                          0x4A2310

#define mmCPU_PLL_CLK_RLX_1                                          0x4A2314

#define mmCPU_PLL_CLK_RLX_2                                          0x4A2318

#define mmCPU_PLL_CLK_RLX_3                                          0x4A231C

#define mmCPU_PLL_REF_CNTR_PERIOD                                    0x4A2400

#define mmCPU_PLL_REF_LOW_THRESHOLD                                  0x4A2410

#define mmCPU_PLL_REF_HIGH_THRESHOLD                                 0x4A2420

#define mmCPU_PLL_PLL_NOT_STABLE                                     0x4A2430

#define mmCPU_PLL_FREQ_CALC_EN                                       0x4A2440

#endif /* ASIC_REG_CPU_PLL_REGS_H_ */
