/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2018 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_MMU_UP_REGS_H_
#define ASIC_REG_MMU_UP_REGS_H_

/*
 *****************************************
 *   MMU_UP (Prototype: MMU)
 *****************************************
 */

#define mmMMU_UP_MMU_ENABLE                                          0xC1100C

#define mmMMU_UP_FORCE_ORDERING                                      0xC11010

#define mmMMU_UP_FEATURE_ENABLE                                      0xC11014

#define mmMMU_UP_VA_ORDERING_MASK_31_7                               0xC11018

#define mmMMU_UP_VA_ORDERING_MASK_49_32                              0xC1101C

#define mmMMU_UP_LOG2_DDR_SIZE                                       0xC11020

#define mmMMU_UP_SCRAMBLER                                           0xC11024

#define mmMMU_UP_MEM_INIT_BUSY                                       0xC11028

#define mmMMU_UP_SPI_MASK                                            0xC1102C

#define mmMMU_UP_SPI_CAUSE                                           0xC11030

#define mmMMU_UP_PAGE_ERROR_CAPTURE                                  0xC11034

#define mmMMU_UP_PAGE_ERROR_CAPTURE_VA                               0xC11038

#define mmMMU_UP_ACCESS_ERROR_CAPTURE                                0xC1103C

#define mmMMU_UP_ACCESS_ERROR_CAPTURE_VA                             0xC11040

#define mmMMU_UP_SPI_INTERRUPT_CLR                                   0xC11044

#define mmMMU_UP_SPI_INTERRUPT_MASK                                  0xC11048

#define mmMMU_UP_DBG_MEM_WRAP_RM                                     0xC1104C

#define mmMMU_UP_SPI_CAUSE_CLR                                       0xC11050

#define mmMMU_UP_SLICE_CREDIT                                        0xC11054

#define mmMMU_UP_PIPE_CREDIT                                         0xC11058

#define mmMMU_UP_RAZWI_WRITE_VLD                                     0xC1105C

#define mmMMU_UP_RAZWI_WRITE_ID                                      0xC11060

#define mmMMU_UP_RAZWI_READ_VLD                                      0xC11064

#define mmMMU_UP_RAZWI_READ_ID                                       0xC11068

#define mmMMU_UP_MMU_BYPASS                                          0xC1106C

#endif /* ASIC_REG_MMU_UP_REGS_H_ */
