/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_
#define ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_

/*
 *****************************************
 *   DCORE0_RTR0_CTRL
 *   (Prototype: RTR_CTRL)
 *****************************************
 */

#define mmDCORE0_RTR0_CTRL_MEM_NUM 0x4140100

#define mmDCORE0_RTR0_CTRL_MEM_MAP 0x4140104

#define mmDCORE0_RTR0_CTRL_WR_RL_MEM 0x4140108

#define mmDCORE0_RTR0_CTRL_WR_RL_PCI 0x414010C

#define mmDCORE0_RTR0_CTRL_WR_RL_SRAM 0x4140110

#define mmDCORE0_RTR0_CTRL_RD_RL_MEM 0x4140114

#define mmDCORE0_RTR0_CTRL_RD_RL_PCI 0x4140118

#define mmDCORE0_RTR0_CTRL_RD_RL_SRAM 0x414011C

#define mmDCORE0_RTR0_CTRL_WR_RL_MEM_RED 0x4140120

#define mmDCORE0_RTR0_CTRL_RL_MEM_REDUCTION 0x4140124

#define mmDCORE0_RTR0_CTRL_WR_RL_SRAM_RED 0x4140128

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_CFG_0 0x4140400

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_CFG_1 0x4140404

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_SHIFT_0 0x4140408

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_SHIFT_1 0x414040C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_0 0x4140410

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_1 0x4140414

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_2 0x4140418

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_3 0x414041C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_4 0x4140420

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_5 0x4140424

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_6 0x4140428

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_7 0x414042C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_8 0x4140430

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_9 0x4140434

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_10 0x4140438

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_11 0x414043C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_12 0x4140440

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_13 0x4140444

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_14 0x4140448

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_15 0x414044C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_0 0x4140450

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_1 0x4140454

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_2 0x4140458

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_3 0x414045C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_4 0x4140460

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_5 0x4140464

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_6 0x4140468

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_7 0x414046C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_8 0x4140470

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_9 0x4140474

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_10 0x4140478

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_11 0x414047C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_12 0x4140480

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_13 0x4140484

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_14 0x4140488

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_15 0x414048C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_0 0x4140490

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_1 0x4140494

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_2 0x4140498

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_3 0x414049C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_4 0x41404A0

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_5 0x41404A4

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_6 0x41404A8

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_7 0x41404AC

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_8 0x41404B0

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_9 0x41404B4

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_10 0x41404B8

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_11 0x41404BC

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_12 0x41404C0

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_13 0x41404C4

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_14 0x41404C8

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_15 0x41404CC

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_WDT_0 0x41404D0

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_WDT_1 0x41404D4

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_DEC_TOKEN_0 0x41404D8

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_DEC_TOKEN_1 0x41404DC

#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_HI_ADDR 0x4140AB8

#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_LO_ADDR 0x4140ABC

#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET 0x4140AC0

#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_HI_ADDR 0x4140AC4

#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_LO_ADDR 0x4140AC8

#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_SET 0x4140ACC

#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_ADDR 0x4140AD0

#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_SET 0x4140AD4

#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_ADDR 0x4140AD8

#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_SET 0x4140ADC

#define mmDCORE0_RTR0_CTRL_RGL_MEM_CFG_0 0x4140AE4

#define mmDCORE0_RTR0_CTRL_RGL_MEM_CFG_1 0x4140AE8

#define mmDCORE0_RTR0_CTRL_RGL_MEM_SHIFT_0 0x4140AEC

#define mmDCORE0_RTR0_CTRL_RGL_MEM_SHIFT_1 0x4140AF0

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_0 0x4140AF4

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_1 0x4140AF8

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_2 0x4140AFC

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_3 0x4140B00

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_4 0x4140B04

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_5 0x4140B08

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_6 0x4140B0C

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_7 0x4140B10

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_8 0x4140B14

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_9 0x4140B18

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_10 0x4140B1C

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_11 0x4140B20

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_12 0x4140B24

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_13 0x4140B28

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_14 0x4140B2C

#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_15 0x4140B30

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_0 0x4140B34

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_1 0x4140B38

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_2 0x4140B3C

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_3 0x4140B40

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_4 0x4140B44

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_5 0x4140B48

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_6 0x4140B4C

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_7 0x4140B50

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_8 0x4140B54

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_9 0x4140B58

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_10 0x4140B5C

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_11 0x4140B60

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_12 0x4140B64

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_13 0x4140B68

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_14 0x4140B6C

#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_15 0x4140B70

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_0 0x4140B74

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_1 0x4140B78

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_2 0x4140B7C

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_3 0x4140B80

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_4 0x4140B84

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_5 0x4140B88

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_6 0x4140B8C

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_7 0x4140B90

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_8 0x4140B94

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_9 0x4140B98

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_10 0x4140B9C

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_11 0x4140BA0

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_12 0x4140BA4

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_13 0x4140BA8

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_14 0x4140BAC

#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_15 0x4140BB0

#define mmDCORE0_RTR0_CTRL_RGL_MEM_WDT_0 0x4140BB4

#define mmDCORE0_RTR0_CTRL_RGL_MEM_WDT_1 0x4140BB8

#define mmDCORE0_RTR0_CTRL_RGL_WR_RED_CNT 0x4140BBC

#define mmDCORE0_RTR0_CTRL_RGL_MEM_DEC_TOKEN_0 0x4140BC0

#define mmDCORE0_RTR0_CTRL_RGL_MEM_DEC_TOKEN_1 0x4140BC4

#endif /* ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_ */
