/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2018 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_SRAM_Y0_X2_RTR_REGS_H_
#define ASIC_REG_SRAM_Y0_X2_RTR_REGS_H_

/*
 *****************************************
 *   SRAM_Y0_X2_RTR (Prototype: IC_RTR)
 *****************************************
 */

#define mmSRAM_Y0_X2_RTR_HBW_RD_RQ_E_ARB                             0x209100

#define mmSRAM_Y0_X2_RTR_HBW_RD_RQ_W_ARB                             0x209104

#define mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB                             0x209110

#define mmSRAM_Y0_X2_RTR_HBW_E_ARB_MAX                               0x209120

#define mmSRAM_Y0_X2_RTR_HBW_W_ARB_MAX                               0x209124

#define mmSRAM_Y0_X2_RTR_HBW_L_ARB_MAX                               0x209130

#define mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB                              0x209140

#define mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB                              0x209144

#define mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB                              0x209148

#define mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB                             0x209160

#define mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB                             0x209164

#define mmSRAM_Y0_X2_RTR_HBW_WR_RS_L_ARB                             0x209168

#define mmSRAM_Y0_X2_RTR_LBW_RD_RQ_E_ARB                             0x209200

#define mmSRAM_Y0_X2_RTR_LBW_RD_RQ_W_ARB                             0x209204

#define mmSRAM_Y0_X2_RTR_LBW_RD_RQ_L_ARB                             0x209210

#define mmSRAM_Y0_X2_RTR_LBW_E_ARB_MAX                               0x209220

#define mmSRAM_Y0_X2_RTR_LBW_W_ARB_MAX                               0x209224

#define mmSRAM_Y0_X2_RTR_LBW_L_ARB_MAX                               0x209230

#define mmSRAM_Y0_X2_RTR_LBW_DATA_E_ARB                              0x209240

#define mmSRAM_Y0_X2_RTR_LBW_DATA_W_ARB                              0x209244

#define mmSRAM_Y0_X2_RTR_LBW_DATA_L_ARB                              0x209248

#define mmSRAM_Y0_X2_RTR_LBW_WR_RS_E_ARB                             0x209260

#define mmSRAM_Y0_X2_RTR_LBW_WR_RS_W_ARB                             0x209264

#define mmSRAM_Y0_X2_RTR_LBW_WR_RS_L_ARB                             0x209268

#define mmSRAM_Y0_X2_RTR_DBG_E_ARB                                   0x209300

#define mmSRAM_Y0_X2_RTR_DBG_W_ARB                                   0x209304

#define mmSRAM_Y0_X2_RTR_DBG_L_ARB                                   0x209310

#define mmSRAM_Y0_X2_RTR_DBG_E_ARB_MAX                               0x209320

#define mmSRAM_Y0_X2_RTR_DBG_W_ARB_MAX                               0x209324

#define mmSRAM_Y0_X2_RTR_DBG_L_ARB_MAX                               0x209330

#endif /* ASIC_REG_SRAM_Y0_X2_RTR_REGS_H_ */
