/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_REGS_H_
#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_REGS_H_

/*
 *****************************************
 *   DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT
 *   (Prototype: MME_TENSOR)
 *****************************************
 */

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_0 0x40CB0F0

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_1 0x40CB0F4

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_2 0x40CB0F8

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_3 0x40CB0FC

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_4 0x40CB100

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_0 0x40CB104

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_1 0x40CB108

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_2 0x40CB10C

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_3 0x40CB110

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_4 0x40CB114

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_0 0x40CB118

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_1 0x40CB11C

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_2 0x40CB120

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_3 0x40CB124

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_0 0x40CB128

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_1 0x40CB12C

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_2 0x40CB130

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_3 0x40CB134

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_0 0x40CB138

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_1 0x40CB13C

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_2 0x40CB140

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_3 0x40CB144

#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_REGS_H_ */
