/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2018 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_PSOC_PCI_PLL_REGS_H_
#define ASIC_REG_PSOC_PCI_PLL_REGS_H_

/*
 *****************************************
 *   PSOC_PCI_PLL (Prototype: PLL)
 *****************************************
 */

#define mmPSOC_PCI_PLL_NR                                            0xC72100

#define mmPSOC_PCI_PLL_NF                                            0xC72104

#define mmPSOC_PCI_PLL_OD                                            0xC72108

#define mmPSOC_PCI_PLL_NB                                            0xC7210C

#define mmPSOC_PCI_PLL_CFG                                           0xC72110

#define mmPSOC_PCI_PLL_LOSE_MASK                                     0xC72120

#define mmPSOC_PCI_PLL_LOCK_INTR                                     0xC72128

#define mmPSOC_PCI_PLL_LOCK_BYPASS                                   0xC7212C

#define mmPSOC_PCI_PLL_DATA_CHNG                                     0xC72130

#define mmPSOC_PCI_PLL_RST                                           0xC72134

#define mmPSOC_PCI_PLL_SLIP_WD_CNTR                                  0xC72150

#define mmPSOC_PCI_PLL_DIV_FACTOR_0                                  0xC72200

#define mmPSOC_PCI_PLL_DIV_FACTOR_1                                  0xC72204

#define mmPSOC_PCI_PLL_DIV_FACTOR_2                                  0xC72208

#define mmPSOC_PCI_PLL_DIV_FACTOR_3                                  0xC7220C

#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_0                              0xC72220

#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_1                              0xC72224

#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_2                              0xC72228

#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_3                              0xC7222C

#define mmPSOC_PCI_PLL_DIV_SEL_0                                     0xC72280

#define mmPSOC_PCI_PLL_DIV_SEL_1                                     0xC72284

#define mmPSOC_PCI_PLL_DIV_SEL_2                                     0xC72288

#define mmPSOC_PCI_PLL_DIV_SEL_3                                     0xC7228C

#define mmPSOC_PCI_PLL_DIV_EN_0                                      0xC722A0

#define mmPSOC_PCI_PLL_DIV_EN_1                                      0xC722A4

#define mmPSOC_PCI_PLL_DIV_EN_2                                      0xC722A8

#define mmPSOC_PCI_PLL_DIV_EN_3                                      0xC722AC

#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_0                             0xC722C0

#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_1                             0xC722C4

#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_2                             0xC722C8

#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_3                             0xC722CC

#define mmPSOC_PCI_PLL_CLK_GATER                                     0xC72300

#define mmPSOC_PCI_PLL_CLK_RLX_0                                     0xC72310

#define mmPSOC_PCI_PLL_CLK_RLX_1                                     0xC72314

#define mmPSOC_PCI_PLL_CLK_RLX_2                                     0xC72318

#define mmPSOC_PCI_PLL_CLK_RLX_3                                     0xC7231C

#define mmPSOC_PCI_PLL_REF_CNTR_PERIOD                               0xC72400

#define mmPSOC_PCI_PLL_REF_LOW_THRESHOLD                             0xC72410

#define mmPSOC_PCI_PLL_REF_HIGH_THRESHOLD                            0xC72420

#define mmPSOC_PCI_PLL_PLL_NOT_STABLE                                0xC72430

#define mmPSOC_PCI_PLL_FREQ_CALC_EN                                  0xC72440

#endif /* ASIC_REG_PSOC_PCI_PLL_REGS_H_ */
