/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2018 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_TPC2_CMDQ_REGS_H_
#define ASIC_REG_TPC2_CMDQ_REGS_H_

/*
 *****************************************
 *   TPC2_CMDQ (Prototype: CMDQ)
 *****************************************
 */

#define mmTPC2_CMDQ_GLBL_CFG0                                        0xE89000

#define mmTPC2_CMDQ_GLBL_CFG1                                        0xE89004

#define mmTPC2_CMDQ_GLBL_PROT                                        0xE89008

#define mmTPC2_CMDQ_GLBL_ERR_CFG                                     0xE8900C

#define mmTPC2_CMDQ_GLBL_ERR_ADDR_LO                                 0xE89010

#define mmTPC2_CMDQ_GLBL_ERR_ADDR_HI                                 0xE89014

#define mmTPC2_CMDQ_GLBL_ERR_WDATA                                   0xE89018

#define mmTPC2_CMDQ_GLBL_SECURE_PROPS                                0xE8901C

#define mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS                            0xE89020

#define mmTPC2_CMDQ_GLBL_STS0                                        0xE89024

#define mmTPC2_CMDQ_GLBL_STS1                                        0xE89028

#define mmTPC2_CMDQ_CQ_CFG0                                          0xE890B0

#define mmTPC2_CMDQ_CQ_CFG1                                          0xE890B4

#define mmTPC2_CMDQ_CQ_ARUSER                                        0xE890B8

#define mmTPC2_CMDQ_CQ_PTR_LO                                        0xE890C0

#define mmTPC2_CMDQ_CQ_PTR_HI                                        0xE890C4

#define mmTPC2_CMDQ_CQ_TSIZE                                         0xE890C8

#define mmTPC2_CMDQ_CQ_CTL                                           0xE890CC

#define mmTPC2_CMDQ_CQ_PTR_LO_STS                                    0xE890D4

#define mmTPC2_CMDQ_CQ_PTR_HI_STS                                    0xE890D8

#define mmTPC2_CMDQ_CQ_TSIZE_STS                                     0xE890DC

#define mmTPC2_CMDQ_CQ_CTL_STS                                       0xE890E0

#define mmTPC2_CMDQ_CQ_STS0                                          0xE890E4

#define mmTPC2_CMDQ_CQ_STS1                                          0xE890E8

#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_EN                                0xE890F0

#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN                         0xE890F4

#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_SAT                               0xE890F8

#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_TOUT                              0xE890FC

#define mmTPC2_CMDQ_CQ_IFIFO_CNT                                     0xE89108

#define mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_LO                             0xE89120

#define mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_HI                             0xE89124

#define mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_LO                             0xE89128

#define mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_HI                             0xE8912C

#define mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_LO                             0xE89130

#define mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_HI                             0xE89134

#define mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_LO                             0xE89138

#define mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_HI                             0xE8913C

#define mmTPC2_CMDQ_CP_LDMA_TSIZE_OFFSET                             0xE89140

#define mmTPC2_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET                       0xE89144

#define mmTPC2_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET                       0xE89148

#define mmTPC2_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET                       0xE8914C

#define mmTPC2_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET                       0xE89150

#define mmTPC2_CMDQ_CP_LDMA_COMMIT_OFFSET                            0xE89154

#define mmTPC2_CMDQ_CP_FENCE0_RDATA                                  0xE89158

#define mmTPC2_CMDQ_CP_FENCE1_RDATA                                  0xE8915C

#define mmTPC2_CMDQ_CP_FENCE2_RDATA                                  0xE89160

#define mmTPC2_CMDQ_CP_FENCE3_RDATA                                  0xE89164

#define mmTPC2_CMDQ_CP_FENCE0_CNT                                    0xE89168

#define mmTPC2_CMDQ_CP_FENCE1_CNT                                    0xE8916C

#define mmTPC2_CMDQ_CP_FENCE2_CNT                                    0xE89170

#define mmTPC2_CMDQ_CP_FENCE3_CNT                                    0xE89174

#define mmTPC2_CMDQ_CP_STS                                           0xE89178

#define mmTPC2_CMDQ_CP_CURRENT_INST_LO                               0xE8917C

#define mmTPC2_CMDQ_CP_CURRENT_INST_HI                               0xE89180

#define mmTPC2_CMDQ_CP_BARRIER_CFG                                   0xE89184

#define mmTPC2_CMDQ_CP_DBG_0                                         0xE89188

#define mmTPC2_CMDQ_CQ_BUF_ADDR                                      0xE89308

#define mmTPC2_CMDQ_CQ_BUF_RDATA                                     0xE8930C

#endif /* ASIC_REG_TPC2_CMDQ_REGS_H_ */
