#ifndef __GSGPU_DC_REG_H__
#define __GSGPU_DC_REG_H__

#define DC_REG_INCREASE 0x10
#define CURRENT_REG(x, link)  ((x) + (link * DC_REG_INCREASE))

#define HT1LO_PCICFG_BASE 0xefdfe000000UL
#define LS7A_PCH_CFG_SPACE_REG (TO_UNCAC(HT1LO_PCICFG_BASE)|0x0000a810)
#define LS7A_PCH_CFG_REG_BASE ((*(volatile unsigned int *)(LS7A_PCH_CFG_SPACE_REG))&0xfffffff0)
#define LS_PIX0_PLL (LS7A_PCH_CFG_REG_BASE + 0x04b0)
#define LS_PIX1_PLL (LS7A_PCH_CFG_REG_BASE + 0x04c0)
#define DC_IO_PIX_PLL 0x04B0

/* CRTC */
#define DC_CRTC_CFG_REG			0x1240
#define CRTC_CFG_FORMAT_MASK	0x7
#define CRTC_CFG_FORMAT32	(1 << 2)
#define CRTC_CFG_FORMAT16	(11 << 0)
#define CRTC_CFG_FORMAT15	(1 << 1)
#define CRTC_CFG_FORMAT12	(1 << 0)
#define CRTC_CFG_TILE4x4	BIT(4)
#define CRTC_CFG_LINEAR		~BIT(4)
#define CRTC_CFG_FB_SWITCH	BIT(7)
#define CRTC_CFG_ENABLE		BIT(8)
#define CRTC_CFG_SWITCH_PANEL	BIT(9)
#define CRTC_CFG_DMA_MASK	(0x3 << 16)
#define CRTC_CFG_DMA_32		(0x3 << 16)
#define CRTC_CFG_DMA_64		(0x2 << 16)
#define CRTC_CFG_DMA_128	(0x1 << 16)
#define CRTC_CFG_DMA_256	(0x0 << 16)
#define CRTC_CFG_GAMMA		BIT(12)
#define CRTC_CFG_RESET		BIT(20)

#define DC_CRTC_FBADDR0_LO_REG		(0x1260)
#define DC_CRTC_FBADDR1_LO_REG		(0x1580)
#define DC_CRTC_FBADDR0_HI_REG		(0x15A0)
#define DC_CRTC_FBADDR1_HI_REG		(0x15C0)
#define DC_CRTC_STRIDE_REG		(0x1280)
#define DC_CRTC_FBORIGIN_REG		(0x1300)

#define DC_CRTC_DITCFG_REG		(0x1360)
#define DC_CRTC_DITTAB_LO_REG		(0x1380)
#define DC_CRTC_DITTAB_HI_REG		(0x13A0)

#define DC_CRTC_PANELCFG_REG		(0x13C0)
#define CRTC_PANCFG_BASE	0x80001010
#define CRTC_PANCFG_DE		BIT(0)
#define CRTC_PANCFG_DEPOL	BIT(1)
#define CRTC_PANCFG_CLKEN	BIT(8)
#define CRTC_PANCFG_CLKPOL	BIT(9)
#define DC_CRTC_PANELTIM_REG		(0x13E0)

#define DC_CRTC_HDISPLAY_REG		(0x1400)
#define CRTC_HPIXEL_SHIFT	0
#define CRTC_HPIXEL_MASK	0xFFFF
#define CRTC_HTOTAL_SHIFT	16
#define CRTC_HTOTAL_MASK	0xFFFF

#define DC_CRTC_HSYNC_REG		(0x1420)
#define CRTC_HSYNC_START_SHIFT	0
#define CRTC_HSYNC_START_MASK	0xFFFF
#define CRTC_HSYNC_END_MASK	0x3FFF
#define CRTC_HSYNC_END_SHIFT	16
#define CRTC_HSYNC_POLSE	BIT(30)
#define CRTC_HSYNC_POL		BIT(31)

#define DC_CRTC_VDISPLAY_REG		(0x1480)
#define CRTC_VPIXEL_SHIFT	0
#define CRTC_VPIXEL_MASK	0xFFFF
#define CRTC_VTOTAL_SHIFT	16
#define CRTC_VTOTAL_MASK	0xFFFF

#define DC_CRTC_VSYNC_REG		(0x14A0)
#define CRTC_VSYNC_START_SHIFT	0
#define CRTC_VSYNC_START_MASK	0xFFFF
#define CRTC_VSYNC_END_SHIFT	16
#define CRTC_VSYNC_END_MASK	0x3FFF
#define CRTC_VSYNC_POLSE	BIT(30)
#define CRTC_VSYNC_POL		BIT(31)

#define DC_CRTC_GAMINDEX_REG		(0x14E0)
#define DC_CRTC_GAMDATA_REG		(0x1500)
#define CRTC_GAMMA_BLUE_SHIFT	0
#define CRTC_GAMMA_BLUE_MASK	0xFF
#define CRTC_GAMMA_GREEN_SHIFT	8
#define CRTC_GAMMA_GREEN_MASK	0xFF
#define CRTC_GAMMA_RED_SHIFT	16
#define CRTC_GAMMA_RED_MASK	0xFF

#define DC_CRTC_SYNCDEV_REG		(0x1B80)
#define DC_CRTC_DISPLAY_POS_REG		(0x14C0)
#define DC_VSYNC_COUNTER_REG		(0x1A00)

#define DC_INT_REG			(0x1570)
#define INT_VSYNC1_ENABLE	BIT(16)
#define INT_VSYNC0_ENABLE	BIT(18)

/* CURSOR */
#define DC_CURSOR0_CFG_REG		0x1520
#define DC_CURSOR1_CFG_REG		0x1670
#define DC_CURSOR_FORMAT_SHIFT	0
#define DC_CURSOR_FORMAT_MASK	0x3
#define DC_CURSOR_MODE_CLEAN	~(1 << 2)
#define DC_CURSOR_MODE_32x32	(0 << 2)
#define DC_CURSOR_MODE_64x64	(1 << 2)
#define DC_CURSOR_DISPLAY_SHIFT	4
#define DC_CURSOR_DISPLAY_MASK	0x1
#define DC_CURSOR_POS_HOT_Y_SHIFT 8
#define DC_CURSOR_POS_HOT_Y_MASK  0x1F
#define DC_CURSOR_POS_HOT_X_SHIFT 16
#define DC_CURSOR_POS_HOT_X_MASK  0x1F

#define DC_CURSOR0_LADDR_REG		0x1530
#define DC_CURSOR0_HADDR_REG		0x15E0
#define DC_CURSOR0_POSITION_REG		0x1540
#define DC_CURSOR1_LADDR_REG		0x1680
#define DC_CURSOR1_HADDR_REG		0x16E0
#define DC_CURSOR1_POSITION_REG		0x1690
#define DC_CURSOR_POS_Y_SHIFT	16
#define DC_CURSOR_POS_Y_MASK	0xFFF
#define DC_CURSOR_POS_X_SHIFT	0
#define DC_CURSOR_POS_X_MASK	0xFFF
#define DC_CURSOR0_BACK_REG		0x1550
#define DC_CURSOR0_FORE_REG		0x1560
#define DC_CURSOR1_BACK_REG		0x16A0
#define DC_CURSOR1_FORE_REG		0x16B0

/* META */
#define DC_CRTC_META0_REG_L		(0x1B00)
#define DC_CRTC_META0_REG_H		(0x1B20)
#define DC_CRTC_META1_REG_L		(0x1B40)
#define DC_CRTC_META1_REG_H		(0x1B60)

/* HDMI */
#define DC_HDMI_ZONEIDLE_REG 		(0x1700)
#define DC_HDMI_CTRL_REG		(0x1720)
#define HDMI_CTRL_ENABLE	(1 << 0)
#define DC_HDMI_PHY_CTRL_REG		(0x1800)
#define HDMI_PHY_CTRL_ENABLE	(1 << 0)
#define DC_HDMI_PHY_PLLCFG_REG		(0x1820)
#define DC_HDMI_PHY_PEC0_REG		(0x1840)
#define DC_HDMI_PHY_PEC1_REG		(0x1860)
#define DC_HDMI_PHY_PEC2_REG		(0x1880)
#define DC_HDMI_PHY_RSVR_REG		(0x18A0)
#define DC_HDMI_PHY_CALCTRL_REG		(0x18C0)
#define DC_HDMI_PHY_CALOUT_REG		(0x1AC0)

#define DC_HDMI_AVI_CONT0_REG		(0x18E0)
#define DC_HDMI_AVI_CONT1_REG		(0x1900)
#define DC_HDMI_AVI_CONT2_REG		(0x1920)
#define DC_HDMI_AVI_CONT3_REG		(0x1940)
#define DC_HDMI_AVI_CTRL_REG		(0x1960)
#define HDMI_AVI_ENABLE_PACKET	(1 << 0)
#define HDMI_AVI_FREQ_EACH_FRAME (0 << 1)
#define HDMI_AVI_FREQ_TWO_FRAME	(1 << 1)
#define HDMI_AVI_UPDATE		(1 << 2)
#define DC_HDMI_VSI_CFG_REG		(0x1980)

/* AUDIO */
#define DC_HDMI_AUDIO_BUF_REG		(0x1740)
#define DC_HDMI_AUDIO_NCFG_REG		(0x1760)
#define DC_HDMI_AUDIO_CTSCFG_REG	(0x1780)
#define DC_HDMI_AUDIO_CTSCALCFG_REG	(0x17A0)
#define DC_HDMI_AUDIO_INFOFRAME_REG	(0x17C0)
#define DC_HDMI_AUDIO_SAMPLE_REG	(0x17E0)

#endif /* __GSGPU_DC_REG_H__ */
