/* GENERATED FILE - DO NOT EDIT */
/*
 * Copyright Altera Corporation (C) 2012-2014. All rights reserved
 *
 * SPDX-License-Identifier:    BSD-3-Clause
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in the
 *      documentation and/or other materials provided with the distribution.
 *    * Neither the name of Altera Corporation nor the
 *      names of its contributors may be used to endorse or promote products
 *      derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <common.h>

/* pin MUX configuration data */
static unsigned long sys_mgr_init_table[] = {
	0,			/* EMACIO0 */
	2,			/* EMACIO1 */
	2,			/* EMACIO2 */
	2,			/* EMACIO3 */
	2,			/* EMACIO4 */
	2,			/* EMACIO5 */
	2,			/* EMACIO6 */
	2,			/* EMACIO7 */
	2,			/* EMACIO8 */
	0,			/* EMACIO9 */
	2,			/* EMACIO10 */
	2,			/* EMACIO11 */
	2,			/* EMACIO12 */
	2,			/* EMACIO13 */
	0,			/* EMACIO14 */
	0,			/* EMACIO15 */
	0,			/* EMACIO16 */
	0,			/* EMACIO17 */
	0,			/* EMACIO18 */
	0,			/* EMACIO19 */
	3,			/* FLASHIO0 */
	0,			/* FLASHIO1 */
	3,			/* FLASHIO2 */
	3,			/* FLASHIO3 */
	0,			/* FLASHIO4 */
	0,			/* FLASHIO5 */
	0,			/* FLASHIO6 */
	0,			/* FLASHIO7 */
	0,			/* FLASHIO8 */
	3,			/* FLASHIO9 */
	3,			/* FLASHIO10 */
	3,			/* FLASHIO11 */
	3,			/* GENERALIO0 */
	3,			/* GENERALIO1 */
	3,			/* GENERALIO2 */
	3,			/* GENERALIO3 */
	3,			/* GENERALIO4 */
	3,			/* GENERALIO5 */
	3,			/* GENERALIO6 */
	3,			/* GENERALIO7 */
	3,			/* GENERALIO8 */
	3,			/* GENERALIO9 */
	3,			/* GENERALIO10 */
	3,			/* GENERALIO11 */
	3,			/* GENERALIO12 */
	2,			/* GENERALIO13 */
	2,			/* GENERALIO14 */
	3,			/* GENERALIO15 */
	3,			/* GENERALIO16 */
	2,			/* GENERALIO17 */
	2,			/* GENERALIO18 */
	0,			/* GENERALIO19 */
	0,			/* GENERALIO20 */
	0,			/* GENERALIO21 */
	0,			/* GENERALIO22 */
	0,			/* GENERALIO23 */
	0,			/* GENERALIO24 */
	0,			/* GENERALIO25 */
	0,			/* GENERALIO26 */
	0,			/* GENERALIO27 */
	0,			/* GENERALIO28 */
	0,			/* GENERALIO29 */
	0,			/* GENERALIO30 */
	0,			/* GENERALIO31 */
	2,			/* MIXED1IO0 */
	2,			/* MIXED1IO1 */
	2,			/* MIXED1IO2 */
	2,			/* MIXED1IO3 */
	2,			/* MIXED1IO4 */
	2,			/* MIXED1IO5 */
	2,			/* MIXED1IO6 */
	2,			/* MIXED1IO7 */
	2,			/* MIXED1IO8 */
	2,			/* MIXED1IO9 */
	2,			/* MIXED1IO10 */
	2,			/* MIXED1IO11 */
	2,			/* MIXED1IO12 */
	2,			/* MIXED1IO13 */
	0,			/* MIXED1IO14 */
	3,			/* MIXED1IO15 */
	3,			/* MIXED1IO16 */
	3,			/* MIXED1IO17 */
	3,			/* MIXED1IO18 */
	3,			/* MIXED1IO19 */
	3,			/* MIXED1IO20 */
	0,			/* MIXED1IO21 */
	0,			/* MIXED2IO0 */
	0,			/* MIXED2IO1 */
	0,			/* MIXED2IO2 */
	0,			/* MIXED2IO3 */
	0,			/* MIXED2IO4 */
	0,			/* MIXED2IO5 */
	0,			/* MIXED2IO6 */
	0,			/* MIXED2IO7 */
	0,			/* GPLINMUX48 */
	0,			/* GPLINMUX49 */
	0,			/* GPLINMUX50 */
	0,			/* GPLINMUX51 */
	0,			/* GPLINMUX52 */
	0,			/* GPLINMUX53 */
	0,			/* GPLINMUX54 */
	0,			/* GPLINMUX55 */
	0,			/* GPLINMUX56 */
	0,			/* GPLINMUX57 */
	0,			/* GPLINMUX58 */
	0,			/* GPLINMUX59 */
	0,			/* GPLINMUX60 */
	0,			/* GPLINMUX61 */
	0,			/* GPLINMUX62 */
	0,			/* GPLINMUX63 */
	0,			/* GPLINMUX64 */
	0,			/* GPLINMUX65 */
	0,			/* GPLINMUX66 */
	0,			/* GPLINMUX67 */
	0,			/* GPLINMUX68 */
	0,			/* GPLINMUX69 */
	0,			/* GPLINMUX70 */
	1,			/* GPLMUX0 */
	1,			/* GPLMUX1 */
	1,			/* GPLMUX2 */
	1,			/* GPLMUX3 */
	1,			/* GPLMUX4 */
	1,			/* GPLMUX5 */
	1,			/* GPLMUX6 */
	1,			/* GPLMUX7 */
	1,			/* GPLMUX8 */
	1,			/* GPLMUX9 */
	1,			/* GPLMUX10 */
	1,			/* GPLMUX11 */
	1,			/* GPLMUX12 */
	1,			/* GPLMUX13 */
	1,			/* GPLMUX14 */
	1,			/* GPLMUX15 */
	1,			/* GPLMUX16 */
	1,			/* GPLMUX17 */
	1,			/* GPLMUX18 */
	1,			/* GPLMUX19 */
	1,			/* GPLMUX20 */
	1,			/* GPLMUX21 */
	1,			/* GPLMUX22 */
	1,			/* GPLMUX23 */
	1,			/* GPLMUX24 */
	1,			/* GPLMUX25 */
	1,			/* GPLMUX26 */
	1,			/* GPLMUX27 */
	1,			/* GPLMUX28 */
	1,			/* GPLMUX29 */
	1,			/* GPLMUX30 */
	1,			/* GPLMUX31 */
	1,			/* GPLMUX32 */
	1,			/* GPLMUX33 */
	1,			/* GPLMUX34 */
	1,			/* GPLMUX35 */
	1,			/* GPLMUX36 */
	1,			/* GPLMUX37 */
	1,			/* GPLMUX38 */
	1,			/* GPLMUX39 */
	1,			/* GPLMUX40 */
	1,			/* GPLMUX41 */
	1,			/* GPLMUX42 */
	1,			/* GPLMUX43 */
	1,			/* GPLMUX44 */
	1,			/* GPLMUX45 */
	1,			/* GPLMUX46 */
	1,			/* GPLMUX47 */
	1,			/* GPLMUX48 */
	1,			/* GPLMUX49 */
	1,			/* GPLMUX50 */
	1,			/* GPLMUX51 */
	1,			/* GPLMUX52 */
	1,			/* GPLMUX53 */
	1,			/* GPLMUX54 */
	1,			/* GPLMUX55 */
	1,			/* GPLMUX56 */
	1,			/* GPLMUX57 */
	1,			/* GPLMUX58 */
	1,			/* GPLMUX59 */
	1,			/* GPLMUX60 */
	1,			/* GPLMUX61 */
	1,			/* GPLMUX62 */
	1,			/* GPLMUX63 */
	1,			/* GPLMUX64 */
	1,			/* GPLMUX65 */
	1,			/* GPLMUX66 */
	1,			/* GPLMUX67 */
	1,			/* GPLMUX68 */
	1,			/* GPLMUX69 */
	1,			/* GPLMUX70 */
	0,			/* NANDUSEFPGA */
	0,			/* UART0USEFPGA */
	0,			/* RGMII1USEFPGA */
	0,			/* SPIS0USEFPGA */
	0,			/* CAN0USEFPGA */
	0,			/* I2C0USEFPGA */
	0,			/* SDMMCUSEFPGA */
	0,			/* QSPIUSEFPGA */
	0,			/* SPIS1USEFPGA */
	0,			/* RGMII0USEFPGA */
	0,			/* UART1USEFPGA */
	0,			/* CAN1USEFPGA */
	0,			/* USB1USEFPGA */
	0,			/* I2C3USEFPGA */
	0,			/* I2C2USEFPGA */
	0,			/* I2C1USEFPGA */
	0,			/* SPIM1USEFPGA */
	0,			/* USB0USEFPGA */
	0			/* SPIM0USEFPGA */
};
