/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Device Tree binding constants for Actions Semi S500 Reset Management Unit
 *
 * Copyright (c) 2014 Actions Semi Inc.
 * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
 */

#ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H
#define __DT_BINDINGS_ACTIONS_S500_RESET_H

#define RESET_DMAC				0
#define RESET_NORIF				1
#define RESET_DDR				2
#define RESET_NANDC				3
#define RESET_SD0				4
#define RESET_SD1				5
#define RESET_PCM1				6
#define RESET_DE				7
#define RESET_LCD				8
#define RESET_SD2				9
#define RESET_DSI				10
#define RESET_CSI				11
#define RESET_BISP				12
#define RESET_KEY				13
#define RESET_GPIO				14
#define RESET_AUDIO				15
#define RESET_PCM0				16
#define RESET_VDE				17
#define RESET_VCE				18
#define RESET_GPU3D				19
#define RESET_NIC301				20
#define RESET_LENS				21
#define RESET_PERIPHRESET			22
#define RESET_USB2_0				23
#define RESET_TVOUT				24
#define RESET_HDMI				25
#define RESET_HDCP2TX				26
#define RESET_UART6				27
#define RESET_UART0				28
#define RESET_UART1				29
#define RESET_UART2				30
#define RESET_SPI0				31
#define RESET_SPI1				32
#define RESET_SPI2				33
#define RESET_SPI3				34
#define RESET_I2C0				35
#define RESET_I2C1				36
#define RESET_USB3				37
#define RESET_UART3				38
#define RESET_UART4				39
#define RESET_UART5				40
#define RESET_I2C2				41
#define RESET_I2C3				42
#define RESET_ETHERNET				43
#define RESET_CHIPID				44
#define RESET_USB2_1				45
#define RESET_WD0RESET				46
#define RESET_WD1RESET				47
#define RESET_WD2RESET				48
#define RESET_WD3RESET				49
#define RESET_DBG0RESET				50
#define RESET_DBG1RESET				51
#define RESET_DBG2RESET				52
#define RESET_DBG3RESET				53

#endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */
