// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
//
// Device Tree binding constants for Actions Semi S900 Reset Management Unit
//
// Copyright (c) 2018 Linaro Ltd.

#ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H
#define __DT_BINDINGS_ACTIONS_S900_RESET_H

#define RESET_CHIPID				0
#define RESET_CPU_SCNT				1
#define RESET_SRAMI				2
#define RESET_DDR_CTL_PHY			3
#define RESET_DMAC				4
#define RESET_GPIO				5
#define RESET_BISP_AXI				6
#define RESET_CSI0				7
#define RESET_CSI1				8
#define RESET_DE				9
#define RESET_DSI				10
#define RESET_GPU3D_PA				11
#define RESET_GPU3D_PB				12
#define RESET_HDE				13
#define RESET_I2C0				14
#define RESET_I2C1				15
#define RESET_I2C2				16
#define RESET_I2C3				17
#define RESET_I2C4				18
#define RESET_I2C5				19
#define RESET_IMX				20
#define RESET_NANDC0				21
#define RESET_NANDC1				22
#define RESET_SD0				23
#define RESET_SD1				24
#define RESET_SD2				25
#define RESET_SD3				26
#define RESET_SPI0				27
#define RESET_SPI1				28
#define RESET_SPI2				29
#define RESET_SPI3				30
#define RESET_UART0				31
#define RESET_UART1				32
#define RESET_UART2				33
#define RESET_UART3				34
#define RESET_UART4				35
#define RESET_UART5				36
#define RESET_UART6				37
#define RESET_HDMI				38
#define RESET_LVDS				39
#define RESET_EDP				40
#define RESET_USB2HUB				41
#define RESET_USB2HSIC				42
#define RESET_USB3				43
#define RESET_PCM1				44
#define RESET_AUDIO				45
#define RESET_PCM0				46
#define RESET_SE				47
#define RESET_GIC				48
#define RESET_DDR_CTL_PHY_AXI			49
#define RESET_CMU_DDR				50
#define RESET_DMM				51
#define RESET_HDCP2TX				52
#define RESET_ETHERNET				53

#endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */
